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arm: socfpga: arria10: Setting image magic value to romcode initswstate reg

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The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Tien Fong Chee 2021-11-07 23:08:54 +08:00
parent 5b20efeafe
commit 2f27754eb7
2 changed files with 11 additions and 2 deletions
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3
arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
*/
#ifndef _SYSTEM_MANAGER_ARRIA10_H_
@ -31,6 +31,7 @@
#define SYSMGR_A10_NOC_IDLEACK 0xd0
#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC

10
arch/arm/mach-socfpga/spl_a10.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012-2019 Altera Corporation <www.altera.com>
* Copyright (C) 2012-2021 Altera Corporation <www.altera.com>
*/
#include <common.h>
@ -32,6 +32,7 @@
#include <memalign.h>
#define FPGA_BUFSIZ 16 * 1024
#define FSBL_IMAGE_IS_VALID 0x49535756
DECLARE_GLOBAL_DATA_PTR;
@ -169,3 +170,10 @@ void board_init_f(ulong dummy)
config_dedicated_pins(gd->fdt_blob);
WATCHDOG_RESET();
}
/* board specific function prior loading SSBL / U-Boot proper */
void spl_board_prepare_for_boot(void)
{
writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
SYSMGR_A10_ROMCODE_INITSWSTATE);
}