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ARM: dts: synquacer: Add device trees for DeveloperBox

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Add device trees for 96boards EE DeveloperBox and basement SynQuacer
SoC dtsi. These files are imported from EDK2

commit 83d38b0b4c0f240d4488c600bbe87cea391f3922

as-is (except for the changes #include path and some macros).

And add U-Boot specific changes in synquacer-sc2a11-developerbox-u-boot.dtsi

Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
This commit is contained in:
Masami Hiramatsu 2021-06-04 18:44:59 +09:00 committed by Tom Rini
parent 4483fbab81
commit 2f1f797efa
5 changed files with 800 additions and 0 deletions
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1
arch/arm/dts/Makefile
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@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9130-crb-A.dtb \
cn9130-crb-B.dtb
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
dtb-$(CONFIG_ARCH_UNIPHIER_LD11) += \
uniphier-ld11-global.dtb \
uniphier-ld11-ref.dtb

73
arch/arm/dts/synquacer-sc2a11-caches.dtsi Normal file
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@ -0,0 +1,73 @@
/** @file
* Copyright (c) 2018, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*/
#define __L1(cpuref, l2ref) \
cpuref { \
i-cache-size = <0x8000>; \
i-cache-line-size = <64>; \
i-cache-sets = <256>; \
d-cache-size = <0x8000>; \
d-cache-line-size = <64>; \
d-cache-sets = <128>; \
l2-cache = <l2ref>; \
};
#define __L2(idx) \
L2_##idx: l2-cache##idx { \
cache-size = <0x40000>; \
cache-line-size = <64>; \
cache-sets = <256>; \
cache-unified; \
next-level-cache = <&L3>; \
};
/ {
__L2(0)
__L2(1)
__L2(2)
__L2(3)
__L2(4)
__L2(5)
__L2(6)
__L2(7)
__L2(8)
__L2(9)
__L2(10)
__L2(11)
L3: l3-cache {
cache-level = <3>;
cache-size = <0x400000>;
cache-line-size = <64>;
cache-sets = <4096>;
cache-unified;
};
};
__L1(&CPU0, &L2_0)
__L1(&CPU1, &L2_0)
__L1(&CPU2, &L2_1)
__L1(&CPU3, &L2_1)
__L1(&CPU4, &L2_2)
__L1(&CPU5, &L2_2)
__L1(&CPU6, &L2_3)
__L1(&CPU7, &L2_3)
__L1(&CPU8, &L2_4)
__L1(&CPU9, &L2_4)
__L1(&CPU10, &L2_5)
__L1(&CPU11, &L2_5)
__L1(&CPU12, &L2_6)
__L1(&CPU13, &L2_6)
__L1(&CPU14, &L2_7)
__L1(&CPU15, &L2_7)
__L1(&CPU16, &L2_8)
__L1(&CPU17, &L2_8)
__L1(&CPU18, &L2_9)
__L1(&CPU19, &L2_9)
__L1(&CPU20, &L2_10)
__L1(&CPU21, &L2_10)
__L1(&CPU22, &L2_11)
__L1(&CPU23, &L2_11)

75
arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi Normal file
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@ -0,0 +1,75 @@
// SPDX-License-Identifier: BSD-2-Clause-Patent
//
// Copyright (c) 2021, Linaro Limited. All rights reserved.
//
/ {
aliases {
spi_nor = &spi_nor;
i2c0 = &i2c0;
};
spi_nor: spi@54800000 {
compatible = "socionext,synquacer-spi";
reg = <0x00 0x54800000 0x00 0x1000>;
interrupts = <0x00 0x9c 0x04 0x00 0x9d 0x04 0x00 0x9e 0x04>;
clocks = <&clk_alw_1_8>;
clock-names = "iHCLK";
socionext,use-rtm;
socionext,set-aces;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
active_clk_edges;
chipselect_num = <1>;
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <31250000>;
spi-rx-bus-width = <0x1>;
spi-tx-bus-width = <0x1>;
};
};
i2c0: i2c@51200000 {
compatible = "socionext,synquacer-i2c";
reg = <0x0 0x51200000 0x0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_i2c>;
clock-names = "pclk";
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
firmware {
optee {
status = "okay";
};
};
};
&smmu {
status = "okay";
};
&pcie0 {
status = "okay";
};
&pcie1 {
status = "okay";
};
&sdhci {
status = "okay";
};

56
arch/arm/dts/synquacer-sc2a11-developerbox.dts Normal file
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@ -0,0 +1,56 @@
/** @file
* Copyright (c) 2017, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*/
/dts-v1/;
#include "synquacer-sc2a11.dtsi"
#define KEY_POWER 116
/ {
model = "Socionext Developer Box";
compatible = "socionext,developer-box", "socionext,synquacer";
gpio-keys {
compatible = "gpio-keys";
interrupt-parent = <&exiu>;
power {
label = "Power Button";
linux,code = <KEY_POWER>;
interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
};
#ifdef TPM2_ENABLE
&tpm {
status = "okay";
};
#endif
&gpio {
gpio-line-names = "DSW3-PIN1", "DSW3-PIN2", "DSW3-PIN3", "DSW3-PIN4",
"DSW3-PIN5", "DSW3-PIN6", "DSW3-PIN7", "DSW3-PIN8",
"PSIN#", "PWROFF#", "GPIO-A", "GPIO-B",
"GPIO-C", "GPIO-D", "PCIE1EXTINT", "PCIE0EXTINT",
"PHY2-INT#", "PHY1-INT#", "GPIO-E", "GPIO-F",
"GPIO-G", "GPIO-H", "GPIO-I", "GPIO-J",
"GPIO-K", "GPIO-L", "PEC-PD26", "PEC-PD27",
"PEC-PD28", "PEC-PD29", "PEC-PD30", "PEC-PD31";
};
&netsec {
phy-mode = "rgmii-id";
};
&mdio_netsec {
phy_netsec: ethernet-phy@7 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <7>;
};
};

595
arch/arm/dts/synquacer-sc2a11.dtsi Normal file
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@ -0,0 +1,595 @@
/** @file
* Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*/
/* These are added for U-Boot to avoid compilation error */
#define PcdNetsecEepromBase 0x08080000
#define FixedPcdGet32(n) n
#define GIC_SPI 0
#define GIC_PPI 1
#define IRQ_TYPE_NONE 0
#define IRQ_TYPE_EDGE_RISING 1
#define IRQ_TYPE_EDGE_FALLING 2
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 4
#define IRQ_TYPE_LEVEL_LOW 8
#define GPIO_ACTIVE_HIGH 0
#define GPIO_ACTIVE_LOW 1
/ {
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&gic>;
aliases {
serial0 = &soc_uart0;
serial1 = &fuart;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x200>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x201>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x300>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x301>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU8: cpu@400 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x400>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU9: cpu@401 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x401>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU10: cpu@500 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x500>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU11: cpu@501 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x501>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU12: cpu@600 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x600>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU13: cpu@601 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x601>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU14: cpu@700 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x700>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU15: cpu@701 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x701>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU16: cpu@800 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x800>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU17: cpu@801 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x801>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU18: cpu@900 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x900>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU19: cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0x901>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU20: cpu@a00 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0xa00>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU21: cpu@a01 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0xa01>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU22: cpu@b00 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0xb00>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
CPU23: cpu@b01 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
reg = <0xb01>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
};
cluster1 {
core0 {
cpu = <&CPU2>;
};
core1 {
cpu = <&CPU3>;
};
};
cluster2 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
};
cluster3 {
core0 {
cpu = <&CPU6>;
};
core1 {
cpu = <&CPU7>;
};
};
cluster4 {
core0 {
cpu = <&CPU8>;
};
core1 {
cpu = <&CPU9>;
};
};
cluster5 {
core0 {
cpu = <&CPU10>;
};
core1 {
cpu = <&CPU11>;
};
};
cluster6 {
core0 {
cpu = <&CPU12>;
};
core1 {
cpu = <&CPU13>;
};
};
cluster7 {
core0 {
cpu = <&CPU14>;
};
core1 {
cpu = <&CPU15>;
};
};
cluster8 {
core0 {
cpu = <&CPU16>;
};
core1 {
cpu = <&CPU17>;
};
};
cluster9 {
core0 {
cpu = <&CPU18>;
};
core1 {
cpu = <&CPU19>;
};
};
cluster10 {
core0 {
cpu = <&CPU20>;
};
core1 {
cpu = <&CPU21>;
};
};
cluster11 {
core0 {
cpu = <&CPU22>;
};
core1 {
cpu = <&CPU23>;
};
};
};
};
idle-states {
entry-method = "arm,psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <300>;
exit-latency-us = <1200>;
min-residency-us = <2000>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x1010000>;
entry-latency-us = <400>;
exit-latency-us = <1200>;
min-residency-us = <2500>;
local-timer-stop;
};
};
gic: interrupt-controller@30000000 {
compatible = "arm,gic-v3";
reg = <0x0 0x30000000 0x0 0x10000>, // GICD
<0x0 0x30400000 0x0 0x300000>, // GICR
<0x0 0x2c000000 0x0 0x2000>, // GICC
<0x0 0x2c010000 0x0 0x1000>, // GICH
<0x0 0x2c020000 0x0 0x10000>; // GICV
#interrupt-cells = <3>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
its: gic-its@30020000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x30020000 0x0 0x20000>;
#msi-cells = <1>;
msi-controller;
socionext,synquacer-pre-its = <0x58000000 0x200000>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, // secure
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, // non-secure
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, // virtual
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; // HYP
};
mmio-timer@2a810000 {
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x2a810000 0x0 0x10000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
frame@2a830000 {
frame-number = <0>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x2a830000 0x0 0x10000>;
};
};
pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
clk_uart: refclk62500khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
clock-output-names = "uartclk";
};
clk_apb: refclk100mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "apb_pclk";
};
soc_uart0: uart@2a400000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x0 0x2a400000 0x0 0x1000>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart>, <&clk_apb>;
clock-names = "uartclk", "apb_pclk";
};
fuart: uart@51040000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x51040000 0x0 0x1000>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_uart>, <&clk_apb>;
clock-names = "baudclk", "apb_pclk";
reg-io-width = <4>;
reg-shift = <2>;
};
clk_netsec: refclk250mhz {
compatible = "fixed-clock";
clock-frequency = <250000000>;
#clock-cells = <0>;
};
netsec: ethernet@522d0000 {
compatible = "socionext,synquacer-netsec";
reg = <0 0x522d0000 0x0 0x10000>,
<0 FixedPcdGet32 (PcdNetsecEepromBase) 0x0 0x10000>;
interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_netsec>;
clock-names = "phy_ref_clk";
max-speed = <1000>;
max-frame-size = <9000>;
phy-handle = <&phy_netsec>;
dma-coherent;
mdio_netsec: mdio {
#address-cells = <1>;
#size-cells = <0>;
};
};
smmu: iommu@582c0000 {
compatible = "arm,mmu-500", "arm,smmu-v2";
reg = <0x0 0x582c0000 0x0 0x10000>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <1>;
status = "disabled";
};
pcie0: pcie@60000000 {
compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
device_type = "pci";
reg = <0x0 0x60000000 0x0 0x7f00000>;
bus-range = <0x0 0x7e>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x1000000 0x00 0x00000000 0x00 0x67f00000 0x0 0x00010000>,
<0x2000000 0x00 0x68000000 0x00 0x68000000 0x0 0x08000000>,
<0x3000000 0x3e 0x00000000 0x3e 0x00000000 0x1 0x00000000>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0x000 &its 0x0 0x7f00>;
dma-coherent;
status = "disabled";
};
pcie1: pcie@70000000 {
compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
device_type = "pci";
reg = <0x0 0x70000000 0x0 0x7f00000>;
bus-range = <0x0 0x7e>;
#address-cells = <3>;
#size-cells = <2>;
ranges = <0x1000000 0x00 0x00000000 0x00 0x77f00000 0x0 0x00010000>,
<0x2000000 0x00 0x78000000 0x00 0x78000000 0x0 0x08000000>,
<0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
#interrupt-cells = <0x1>;
interrupt-map-mask = <0x0 0x0 0x0 0x0>;
interrupt-map = <0x0 0x0 0x0 0x0 &gic 0x0 0x0 GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
msi-map = <0x0 &its 0x10000 0x7f00>;
dma-coherent;
status = "disabled";
};
gpio: gpio@51000000 {
compatible = "socionext,synquacer-gpio", "fujitsu,mb86s70-gpio";
reg = <0x0 0x51000000 0x0 0x100>;
gpio-controller;
#gpio-cells = <2>;
clocks = <&clk_apb>;
base = <0>;
};
exiu: interrupt-controller@510c0000 {
compatible = "socionext,synquacer-exiu";
reg = <0x0 0x510c0000 0x0 0x20>;
interrupt-controller;
interrupt-parent = <&gic>;
#interrupt-cells = <3>;
socionext,spi-base = <112>;
};
clk_alw_b_0: bclk200 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
clock-output-names = "sd_bclk";
};
clk_alw_c_0: sd4clk800 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <800000000>;
clock-output-names = "sd_sd4clk";
};
sdhci: sdhci@52300000 {
compatible = "socionext,synquacer-sdhci", "fujitsu,mb86s70-sdhci-3.0";
reg = <0 0x52300000 0x0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
bus-width = <8>;
cap-mmc-highspeed;
fujitsu,cmd-dat-delay-select;
clocks = <&clk_alw_c_0 &clk_alw_b_0>;
clock-names = "core", "iface";
dma-coherent;
status = "disabled";
};
clk_alw_1_8: spi_ihclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
clock-output-names = "iHCLK";
};
spi: spi@54810000 {
compatible = "socionext,synquacer-spi";
reg = <0x0 0x54810000 0x0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_alw_1_8>;
clock-names = "iHCLK";
socionext,use-rtm;
socionext,set-aces;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
clk_i2c: i2c_pclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
clock-output-names = "pclk";
};
i2c: i2c@51210000 {
compatible = "socionext,synquacer-i2c";
reg = <0x0 0x51210000 0x0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_i2c>;
clock-names = "pclk";
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
};
tpm: tpm_tis@10000000 {
compatible = "socionext,synquacer-tpm-mmio";
reg = <0x0 0x10000000 0x0 0x5000>;
status = "disabled";
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
status = "disabled";
};
};
};
#include "synquacer-sc2a11-caches.dtsi"