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Merge tag 'u-boot-imx-20191209' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
Fixes for 2020.01
-----------------

- imx8qxp_mek: increase buffer sizes and args number
- Fixes for imx7ulp
- imx8mm: Fix the first root clock in imx8mm_ahb_sels[]
- colibri_imx7: reserve DDR memory for Cortex-M4
- vining2000: fixes and convert to ethernet DM
- imx8m: fix rom version check to unbreak some B0 chips
- tbs2910: Disable VxWorks image booting support
This commit is contained in:
Tom Rini
2019-12-09 10:32:08 -05:00
parent b38c3a641f 6a4b07e086
commit 2f02845817
24 changed files with 1455 additions and 1071 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
arch/arm/dts/imx6sx-softing-vining-2000.dts
View File

@@ -270,6 +270,17 @@
status = "okay";
};
&reg_pcie {
regulator-always-on;
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpios>;
@@ -360,6 +371,12 @@
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x10b0
>;
};
pinctrl_pwm1: pwm1grp-1 {
fsl,pins = <
/* blue LED */

157
arch/arm/dts/imx7ulp-evk.dts
View File

@@ -15,7 +15,7 @@
compatible = "fsl,imx7ulp-evk", "fsl,imx7ulp", "Generic DT based system";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0010,115200";
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x402D0000,115200";
stdout-path = &lpuart4;
};
@@ -66,7 +66,7 @@
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
pinctrl-0 = <&pinctrl_usbotg1_vbus>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -84,22 +84,6 @@
enable-active-high;
};
reg_vsd_3v3b: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "VSD_3V3B";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
extcon_usb1: extcon_usb1 {
compatible = "linux,extcon-usb-gpio";
id-gpio = <&gpio0 8 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_extcon_usb1>;
};
pf1550-rpmsg {
@@ -166,134 +150,135 @@
imx7ulp-evk {
pinctrl_hog_1: hoggrp-1 {
fsl,pins = <
ULP1_PAD_PTC10__PTC10 0x30100 /* USDHC0 CD */
ULP1_PAD_PTC1__PTC1 0x20100
ULP1_PAD_PTD0__PTD0 0x30100 /* USDHC0 RST */
ULP1_PAD_PTE13__PTE13 0x30103 /* USDHC1 CD */
ULP1_PAD_PTE12__PTE12 0x30103 /* USDHC1 WP */
ULP1_PAD_PTE14__SDHC1_VS 0x843 /* USDHC1 VSEL */
IMX7ULP_PAD_PTC1__PTC1 0x20000
>;
};
pinctrl_backlight: backlight_grp {
fsl,pins = <
ULP1_PAD_PTF2__PTF2 0x20100
IMX7ULP_PAD_PTF2__PTF2 0x20100
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
ULP1_PAD_PTC4__LPI2C5_SCL 0x527
ULP1_PAD_PTC5__LPI2C5_SDA 0x527
IMX7ULP_PAD_PTC4__LPI2C5_SCL 0x27
IMX7ULP_PAD_PTC5__LPI2C5_SDA 0x27
>;
};
pinctrl_mipi_dsi_reset: mipi_dsi_reset_grp {
fsl,pins = <
ULP1_PAD_PTC19__PTC19 0x20103
IMX7ULP_PAD_PTC19__PTC19 0x20003
>;
};
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
ULP1_PAD_PTC3__LPUART4_RX 0x400
ULP1_PAD_PTC2__LPUART4_TX 0x400
IMX7ULP_PAD_PTC3__LPUART4_RX 0x3
IMX7ULP_PAD_PTC2__LPUART4_TX 0x3
>;
};
pinctrl_lpuart6: lpuart6grp {
fsl,pins = <
ULP1_PAD_PTE10__LPUART6_TX 0x400
ULP1_PAD_PTE11__LPUART6_RX 0x400
ULP1_PAD_PTE9__LPUART6_RTS_B 0x400
ULP1_PAD_PTE8__LPUART6_CTS_B 0x400
ULP1_PAD_PTE7__PTE7 0x00 /* BT_REG_ON */
IMX7ULP_PAD_PTE10__LPUART6_TX 0x3
IMX7ULP_PAD_PTE11__LPUART6_RX 0x3
IMX7ULP_PAD_PTE9__LPUART6_RTS_B 0x3
IMX7ULP_PAD_PTE8__LPUART6_CTS_B 0x3
IMX7ULP_PAD_PTE7__PTE7 0x20000 /* BT_REG_ON */
>;
};
pinctrl_lpuart7: lpuart7grp {
fsl,pins = <
ULP1_PAD_PTF14__LPUART7_TX 0x400
ULP1_PAD_PTF15__LPUART7_RX 0x400
ULP1_PAD_PTF13__LPUART7_RTS_B 0x400
ULP1_PAD_PTF12__LPUART7_CTS_B 0x400
IMX7ULP_PAD_PTF14__LPUART7_TX 0x3
IMX7ULP_PAD_PTF15__LPUART7_RX 0x3
IMX7ULP_PAD_PTF13__LPUART7_RTS_B 0x3
IMX7ULP_PAD_PTF12__LPUART7_CTS_B 0x3
>;
};
pinctrl_usdhc0: usdhc0grp {
fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843
ULP1_PAD_PTD2__SDHC0_CLK 0x10843
ULP1_PAD_PTD7__SDHC0_D3 0x843
ULP1_PAD_PTD8__SDHC0_D2 0x843
ULP1_PAD_PTD9__SDHC0_D1 0x843
ULP1_PAD_PTD10__SDHC0_D0 0x843
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTC10__PTC10 0x10000 /* USDHC0 CD */
IMX7ULP_PAD_PTD0__PTD0 0x20000 /* USDHC0 RST */
>;
};
pinctrl_usdhc0_8bit: usdhc0grp_8bit {
fsl,pins = <
ULP1_PAD_PTD1__SDHC0_CMD 0x843
ULP1_PAD_PTD2__SDHC0_CLK 0x843
ULP1_PAD_PTD3__SDHC0_D7 0x843
ULP1_PAD_PTD4__SDHC0_D6 0x843
ULP1_PAD_PTD5__SDHC0_D5 0x843
ULP1_PAD_PTD6__SDHC0_D4 0x843
ULP1_PAD_PTD7__SDHC0_D3 0x843
ULP1_PAD_PTD8__SDHC0_D2 0x843
ULP1_PAD_PTD9__SDHC0_D1 0x843
ULP1_PAD_PTD10__SDHC0_D0 0x843
IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43
IMX7ULP_PAD_PTD2__SDHC0_CLK 0x10042
IMX7ULP_PAD_PTD3__SDHC0_D7 0x43
IMX7ULP_PAD_PTD4__SDHC0_D6 0x43
IMX7ULP_PAD_PTD5__SDHC0_D5 0x43
IMX7ULP_PAD_PTD6__SDHC0_D4 0x43
IMX7ULP_PAD_PTD7__SDHC0_D3 0x43
IMX7ULP_PAD_PTD8__SDHC0_D2 0x43
IMX7ULP_PAD_PTD9__SDHC0_D1 0x43
IMX7ULP_PAD_PTD10__SDHC0_D0 0x43
IMX7ULP_PAD_PTD11__SDHC0_DQS 0x42
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
ULP1_PAD_PTF12__LPI2C7_SCL 0x527
ULP1_PAD_PTF13__LPI2C7_SDA 0x527
IMX7ULP_PAD_PTF12__LPI2C7_SCL 0x27
IMX7ULP_PAD_PTF13__LPI2C7_SDA 0x27
>;
};
pinctrl_lpspi3: lpspi3grp {
fsl,pins = <
ULP1_PAD_PTF16__LPSPI3_SIN 0x300
ULP1_PAD_PTF17__LPSPI3_SOUT 0x300
ULP1_PAD_PTF18__LPSPI3_SCK 0x300
ULP1_PAD_PTF19__LPSPI3_PCS0 0x300
IMX7ULP_PAD_PTF16__LPSPI3_SIN 0x0
IMX7ULP_PAD_PTF17__LPSPI3_SOUT 0x0
IMX7ULP_PAD_PTF18__LPSPI3_SCK 0x0
IMX7ULP_PAD_PTF19__LPSPI3_PCS0 0x0
>;
};
pinctrl_usb_otg1: usbotg1grp {
pinctrl_usbotg1_vbus: otg1vbusgrp {
fsl,pins = <
ULP1_PAD_PTC0__PTC0 0x30100
IMX7ULP_PAD_PTC0__PTC0 0x20000
>;
};
pinctrl_extcon_usb1: extcon1grp {
pinctrl_usbotg1_id: otg1idgrp {
fsl,pins = <
ULP1_PAD_PTC8__PTC8 0x30103
IMX7ULP_PAD_PTC13__USB0_ID 0x10003
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
ULP1_PAD_PTE3__SDHC1_CMD 0x843
ULP1_PAD_PTE2__SDHC1_CLK 0x843
ULP1_PAD_PTE1__SDHC1_D0 0x843
ULP1_PAD_PTE0__SDHC1_D1 0x843
ULP1_PAD_PTE5__SDHC1_D2 0x843
ULP1_PAD_PTE4__SDHC1_D3 0x843
IMX7ULP_PAD_PTE3__SDHC1_CMD 0x43
IMX7ULP_PAD_PTE2__SDHC1_CLK 0x10042
IMX7ULP_PAD_PTE1__SDHC1_D0 0x43
IMX7ULP_PAD_PTE0__SDHC1_D1 0x43
IMX7ULP_PAD_PTE5__SDHC1_D2 0x43
IMX7ULP_PAD_PTE4__SDHC1_D3 0x43
>;
};
pinctrl_usdhc1_rst: usdhc1grp_rst {
fsl,pins = <
ULP1_PAD_PTE11__PTE11 0x30100 /* USDHC1 RST */
IMX7ULP_PAD_PTE11__PTE11 0x20000 /* USDHC1 RST */
IMX7ULP_PAD_PTE13__PTE13 0x10003 /* USDHC1 CD */
IMX7ULP_PAD_PTE12__PTE12 0x10003 /* USDHC1 WP */
IMX7ULP_PAD_PTE14__SDHC1_VS 0x43 /* USDHC1 VSEL */
>;
};
pinctrl_wifi: wifigrp {
pinctrl_dsi_hdmi: dsi_hdmi_grp {
fsl,pins = <
ULP1_PAD_PTE6__PTE6 0x43 /* WL_REG_ON */
IMX7ULP_PAD_PTC18__PTC18 0x10003 /* DSI_HDMI_INT */
>;
};
};
@@ -304,7 +289,7 @@
disp-dev = "mipi_dsi_northwest";
display = <&display0>;
display0: display {
display0: display@0 {
bits-per-pixel = <16>;
bus-width = <24>;
@@ -343,21 +328,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
fxas2100x@20 {
compatible = "fsl,fxas2100x";
reg = <0x20>;
};
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
};
};
&lpspi3 {
@@ -406,13 +376,18 @@
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
extcon = <0>, <&extcon_usb1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1_id>;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbphy1 {
fsl,tx-d-cal = <88>;
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc0>;

1748
arch/arm/dts/imx7ulp-pinfunc.h
View File

File diff suppressed because it is too large Load Diff

28
arch/arm/dts/imx7ulp.dtsi
View File

@@ -16,10 +16,12 @@
interrupt-parent = <&intc>;
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
gpio0 = &gpio4;
gpio1 = &gpio5;
gpio2 = &gpio0;
gpio3 = &gpio1;
gpio4 = &gpio2;
gpio5 = &gpio3;
mmc0 = &usdhc0;
mmc1 = &usdhc1;
serial0 = &lpuart4;
@@ -27,10 +29,12 @@
serial2 = &lpuart6;
serial3 = &lpuart7;
usbphy0 = &usbphy1;
usb0 = &usbotg1;
i2c4 = &lpi2c4;
i2c5 = &lpi2c5;
i2c6 = &lpi2c6;
i2c7 = &lpi2c7;
spi0 = &qspi1;
};
cpus {
@@ -503,6 +507,22 @@
fsl,mux_mask = <0xf00>;
};
gpio4: gpio@4103f000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x4103f000 0x1000 0x4100F000 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&iomuxc 0 0 32>;
};
gpio5: gpio@41040000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x41040000 0x1000 0x4100F040 0x40>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&iomuxc 0 32 32>;
};
gpio0: gpio@40ae0000 {
compatible = "fsl,imx7ulp-gpio";
reg = <0x40ae0000 0x1000 0x400F0000 0x40>;

8
arch/arm/include/asm/arch-mx6/sys_proto.h
View File

@@ -20,6 +20,14 @@
int imx6_pcie_toggle_power(void);
int imx6_pcie_toggle_reset(void);
enum ldo_reg {
LDO_ARM,
LDO_SOC,
LDO_PU,
};
int set_ldo_voltage(enum ldo_reg ldo, u32 mv);
/**
* iomuxc_set_rgmii_io_voltage - set voltage level of RGMII/USB pins
*

1
arch/arm/include/asm/arch-mx7ulp/scg.h
View File

@@ -331,7 +331,6 @@ u32 decode_pll(enum pll_clocks pll);
void scg_a7_rccr_init(void);
void scg_a7_spll_init(void);
void scg_a7_ddrclk_init(void);
void scg_a7_apll_init(void);
void scg_a7_firc_init(void);
void scg_a7_nicclk_init(void);
void scg_a7_sys_clk_sel(enum scg_sys_src clk);

2
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@@ -153,6 +153,8 @@ void init_src(void);
void init_snvs(void);
void imx_wdog_disable_powerdown(void);
int arch_auxiliary_core_check_up(u32 core_id);
int board_mmc_get_env_dev(int devno);
int nxp_board_rev(void);

1
arch/arm/mach-imx/imx8m/soc.c
View File

@@ -217,6 +217,7 @@ u32 get_cpu_rev(void)
readl((void __iomem *)ROM_VERSION_A0);
if (rom_version != CHIP_REV_1_0) {
rom_version = readl((void __iomem *)ROM_VERSION_B0);
rom_version &= 0xff;
if (rom_version == CHIP_REV_2_0)
reg = CHIP_REV_2_0;
}

1
arch/arm/mach-imx/mx6/Kconfig
View File

@@ -558,6 +558,7 @@ config TARGET_SOFTING_VINING_2000
select DM
select DM_THERMAL
select MX6SX
select SUPPORT_SPL
imply CMD_DM
config TARGET_WANDBOARD

43
arch/arm/mach-imx/mx6/soc.c
View File

@@ -24,12 +24,6 @@
#include <imx_thermal.h>
#include <mmc.h>
enum ldo_reg {
LDO_ARM,
LDO_SOC,
LDO_PU,
};
struct scu_regs {
u32 ctrl;
u32 config;
@@ -255,7 +249,7 @@ static void clear_ldo_ramp(void)
* Possible values are from 0.725V to 1.450V in steps of
* 0.025V (25mV).
*/
static int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
int set_ldo_voltage(enum ldo_reg ldo, u32 mv)
{
struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
u32 val, step, old, reg = readl(&anatop->reg_core);
@@ -375,6 +369,37 @@ static void init_bandgap(void)
}
}
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
static void noc_setup(void)
{
enable_ipu_clock();
writel(0x80000201, 0xbb0608);
/* Bypass IPU1 QoS generator */
writel(0x00000002, 0x00bb048c);
/* Bypass IPU2 QoS generator */
writel(0x00000002, 0x00bb050c);
/* Bandwidth THR for of PRE0 */
writel(0x00000200, 0x00bb0690);
/* Bandwidth THR for of PRE1 */
writel(0x00000200, 0x00bb0710);
/* Bandwidth THR for of PRE2 */
writel(0x00000200, 0x00bb0790);
/* Bandwidth THR for of PRE3 */
writel(0x00000200, 0x00bb0810);
/* Saturation THR for of PRE0 */
writel(0x00000010, 0x00bb0694);
/* Saturation THR for of PRE1 */
writel(0x00000010, 0x00bb0714);
/* Saturation THR for of PRE2 */
writel(0x00000010, 0x00bb0794);
/* Saturation THR for of PRE */
writel(0x00000010, 0x00bb0814);
disable_ipu_clock();
}
#endif
int arch_cpu_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
@@ -452,6 +477,10 @@ int arch_cpu_init(void)
init_src();
#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QDL)
if (is_mx6dqp())
noc_setup();
#endif
return 0;
}

5
arch/arm/mach-imx/mx7ulp/Kconfig
View File

@@ -3,6 +3,11 @@ if ARCH_MX7ULP
config SYS_SOC
default "mx7ulp"
config LDO_ENABLED_MODE
bool "i.MX7ULP LDO Enabled Mode"
help
Select this option to enable the PMC1 LDO.
config MX7ULP
bool

61
arch/arm/mach-imx/mx7ulp/scg.c
View File

@@ -949,67 +949,6 @@ void scg_a7_ddrclk_init(void)
/* Clock source is System OSC <<0 */
#define SCG1_APLL_CFG_CLKSRC_NUM ((0x0) << SCG_PLL_CFG_CLKSRC_SHIFT)
/*
* A7 APLL = 24MHz / 1 * 22 / 1 / 1 = 528MHz,
* system PLL is sourced from APLL,
* APLL clock source is system OSC (24MHz)
*/
#define SCG1_APLL_CFG_NUM_24M_OSC (SCG1_APLL_CFG_POSTDIV2_NUM | \
SCG1_APLL_CFG_POSTDIV1_NUM | \
(22 << SCG_PLL_CFG_MULT_SHIFT) | \
SCG1_APLL_CFG_PFDSEL_NUM | \
SCG1_APLL_CFG_PREDIV_NUM | \
SCG1_APLL_CFG_BYPASS_NUM | \
SCG1_APLL_CFG_PLLSEL_NUM | \
SCG1_APLL_CFG_CLKSRC_NUM)
/* PFD0 Freq = A7 APLL(528MHz) * 18 / 27 = 352MHz */
#define SCG1_APLL_PFD0_FRAC_NUM (27)
void scg_a7_apll_init(void)
{
u32 val = 0;
/* Disable A7 Auxiliary PLL */
val = readl(&scg1_regs->apllcsr);
val &= ~SCG_APLL_CSR_APLLEN_MASK;
writel(val, &scg1_regs->apllcsr);
/* Gate off A7 APLL PFD0 ~ PDF4 */
val = readl(&scg1_regs->apllpfd);
val |= 0x80808080;
writel(val, &scg1_regs->apllpfd);
/* ================ A7 APLL Configuration Start ============== */
/* Configure A7 Auxiliary PLL */
writel(SCG1_APLL_CFG_NUM_24M_OSC, &scg1_regs->apllcfg);
/* Enable A7 Auxiliary PLL */
val = readl(&scg1_regs->apllcsr);
val |= SCG_APLL_CSR_APLLEN_MASK;
writel(val, &scg1_regs->apllcsr);
/* Wait for A7 APLL clock ready */
while (!(readl(&scg1_regs->apllcsr) & SCG_APLL_CSR_APLLVLD_MASK))
;
/* Configure A7 APLL PFD0 */
val = readl(&scg1_regs->apllpfd);
val &= ~SCG_PLL_PFD0_FRAC_MASK;
val |= SCG1_APLL_PFD0_FRAC_NUM;
writel(val, &scg1_regs->apllpfd);
/* Un-gate A7 APLL PFD0 */
val = readl(&scg1_regs->apllpfd);
val &= ~SCG_PLL_PFD0_GATE_MASK;
writel(val, &scg1_regs->apllpfd);
/* Wait for A7 APLL PFD0 clock being valid */
while (!(readl(&scg1_regs->apllpfd) & SCG_PLL_PFD0_VALID_MASK))
;
}
/* SCG1(A7) FIRC DIV configurations */
/* Disable FIRC DIV3 */
#define SCG1_FIRCDIV_DIV3_NUM ((0x0) << SCG_FIRCDIV_DIV3_SHIFT)

78
arch/arm/mach-imx/mx7ulp/soc.c
View File

@@ -10,6 +10,22 @@
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/hab.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
#define PMC0_CTRL_LDOEN BIT(31)
#define PMC0_CTRL_LDOOKDIS BIT(30)
#define PMC0_CTRL_PMC1ON BIT(24)
#define PMC1_BASE_ADDR 0x40400000
#define PMC1_RUN 0x8
#define PMC1_STOP 0x10
#define PMC1_VLPS 0x14
#define PMC1_LDOVL_SHIFT 16
#define PMC1_LDOVL_MASK (0x3f << PMC1_LDOVL_SHIFT)
#define PMC1_LDOVL_900 0x1e
#define PMC1_LDOVL_950 0x23
#define PMC1_STATUS 0x20
#define PMC1_STATUS_LDOVLF BIT(8)
static char *get_reset_cause(char *);
#if defined(CONFIG_IMX_HAB)
@@ -101,6 +117,44 @@ void init_wdog(void)
disable_wdog(WDG2_RBASE);
}
#if defined(CONFIG_LDO_ENABLED_MODE)
static void init_ldo_mode(void)
{
unsigned int reg;
/* Set LDOOKDIS */
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOOKDIS);
/* Set LDOVL to 0.95V in PMC1_RUN */
reg = readl(PMC1_BASE_ADDR + PMC1_RUN);
reg &= ~PMC1_LDOVL_MASK;
reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_RUN, reg);
/* Wait for LDOVLF to be cleared */
reg = readl(PMC1_BASE_ADDR + PMC1_STATUS);
while (reg & PMC1_STATUS_LDOVLF)
;
/* Set LDOVL to 0.95V in PMC1_STOP */
reg = readl(PMC1_BASE_ADDR + PMC1_STOP);
reg &= ~PMC1_LDOVL_MASK;
reg |= (PMC1_LDOVL_950 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_STOP, reg);
/* Set LDOVL to 0.90V in PMC1_VLPS */
reg = readl(PMC1_BASE_ADDR + PMC1_VLPS);
reg &= ~PMC1_LDOVL_MASK;
reg |= (PMC1_LDOVL_900 << PMC1_LDOVL_SHIFT);
writel(PMC1_BASE_ADDR + PMC1_VLPS, reg);
/* Set LDOEN bit */
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_LDOEN);
/* Set the PMC1ON bit */
setbits_le32(PMC0_BASE_ADDR + PMC0_CTRL, PMC0_CTRL_PMC1ON);
}
#endif
void s_init(void)
{
@@ -114,6 +168,10 @@ void s_init(void)
/* enable dumb pmic */
writel((readl(SNVS_LP_LPCR) | SNVS_LPCR_DPEN), SNVS_LP_LPCR);
}
#if defined(CONFIG_LDO_ENABLED_MODE)
init_ldo_mode();
#endif
return;
}
@@ -132,6 +190,21 @@ const char *get_imx_type(u32 imxtype)
return "7ULP";
}
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
#define PMC0_CTRL_LDOEN BIT(31)
static bool ldo_mode_is_enabled(void)
{
unsigned int reg;
reg = readl(PMC0_BASE_ADDR + PMC0_CTRL);
if (reg & PMC0_CTRL_LDOEN)
return true;
else
return false;
}
int print_cpuinfo(void)
{
u32 cpurev;
@@ -160,6 +233,11 @@ int print_cpuinfo(void)
break;
}
if (ldo_mode_is_enabled())
printf("PMC1: LDO enabled mode\n");
else
printf("PMC1: LDO bypass mode\n");
return 0;
}
#endif