Merge branch 'master' of git://git.denx.de/u-boot-mmc
This commit is contained in:
commit
2ed3f91143
@ -172,11 +172,24 @@ void spl_mmc_load_image(void)
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err = mmc_load_image_raw_sector(mmc,
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err = mmc_load_image_raw_sector(mmc,
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
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CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR);
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#endif
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#endif
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} else {
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}
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#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
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puts("spl: wrong MMC boot mode\n");
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switch(boot_mode){
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case MMCSD_MODE_RAW:
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#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
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case MMCSD_MODE_FS:
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#endif
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#endif
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hang();
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#ifdef CONFIG_SUPPORT_EMMC_BOOT
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case MMCSD_MODE_EMMCBOOT:
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#endif
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/* Boot mode is ok. Nothing to do. */
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break;
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case MMCSD_MODE_UNDEFINED:
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default:
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#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT
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puts("spl: wrong MMC boot mode\n");
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#endif
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hang();
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}
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}
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if (err)
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if (err)
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@ -1,7 +1,7 @@
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/*
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/*
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* Marvell MMC/SD/SDIO driver
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* Marvell MMC/SD/SDIO driver
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*
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*
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* (C) Copyright 2012
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* (C) Copyright 2012-2014
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* Marvell Semiconductor <www.marvell.com>
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Maen Suleiman, Gerald Kerma
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* Written-by: Maen Suleiman, Gerald Kerma
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*
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*
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@ -23,6 +23,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define MVEBU_TARGET_DRAM 0
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#define MVEBU_TARGET_DRAM 0
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#define TIMEOUT_DELAY 5*CONFIG_SYS_HZ /* wait 5 seconds */
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static void mvebu_mmc_write(u32 offs, u32 val)
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static void mvebu_mmc_write(u32 offs, u32 val)
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{
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{
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writel(val, CONFIG_SYS_MMC_BASE + (offs));
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writel(val, CONFIG_SYS_MMC_BASE + (offs));
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@ -63,37 +65,47 @@ static int mvebu_mmc_setup_data(struct mmc_data *data)
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static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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struct mmc_data *data)
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{
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{
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int timeout = 10;
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ulong start;
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ushort waittype = 0;
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ushort waittype = 0;
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ushort resptype = 0;
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ushort resptype = 0;
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ushort xfertype = 0;
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ushort xfertype = 0;
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ushort resp_indx = 0;
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ushort resp_indx = 0;
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debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
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debug("%s: cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
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cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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DRIVER_NAME, cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
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udelay(10*1000);
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debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
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debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
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cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
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cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
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/* Checking if card is busy */
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/*
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while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
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* Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
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if (timeout == 0) {
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* register is sometimes not set before a while when some
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printf("%s: card busy!\n", DRIVER_NAME);
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* "unusual" data block sizes are used (such as with the SWITCH
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return -1;
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* command), even despite the fact that the XFER_DONE interrupt
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}
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* was raised. And if another data transfer starts before
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timeout--;
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* this bit comes to good sense (which eventually happens by
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udelay(1000);
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* itself) then the new transfer simply fails with a timeout.
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*/
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if (!(mvebu_mmc_read(SDIO_HW_STATE) & CMD_FIFO_EMPTY)) {
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ushort hw_state, count = 0;
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start = get_timer(0);
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do {
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hw_state = mvebu_mmc_read(SDIO_HW_STATE);
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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printf("%s : FIFO_EMPTY bit missing\n",
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DRIVER_NAME);
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break;
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}
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count++;
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} while (!(hw_state & CMD_FIFO_EMPTY));
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debug("%s *** wait for FIFO_EMPTY bit (hw=0x%04x, count=%d, jiffies=%ld)\n",
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DRIVER_NAME, hw_state, count, (get_timer(0) - (start)));
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}
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}
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/* Set up for a data transfer if we have one */
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/* Clear status */
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if (data) {
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mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
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int err = mvebu_mmc_setup_data(data);
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mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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if (err)
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return err;
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}
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resptype = SDIO_CMD_INDEX(cmd->cmdidx);
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resptype = SDIO_CMD_INDEX(cmd->cmdidx);
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@ -119,6 +131,14 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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}
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}
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if (data) {
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if (data) {
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int err = mvebu_mmc_setup_data(data);
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if (err) {
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debug("%s: command DATA error :%x\n",
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DRIVER_NAME, err);
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return err;
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}
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resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
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resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
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xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
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xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
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if (data->flags & MMC_DATA_READ) {
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if (data->flags & MMC_DATA_READ) {
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@ -138,17 +158,10 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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/* Setting Xfer mode */
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/* Setting Xfer mode */
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mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
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mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
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mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
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mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
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/* Sending command */
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/* Sending command */
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mvebu_mmc_write(SDIO_CMD, resptype);
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mvebu_mmc_write(SDIO_CMD, resptype);
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mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
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start = get_timer(0);
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mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
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/* Waiting for completion */
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timeout = 1000000;
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while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
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while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
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if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
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if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
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@ -156,21 +169,20 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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DRIVER_NAME, cmd->cmdidx,
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DRIVER_NAME, cmd->cmdidx,
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mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
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mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT)) {
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debug("%s: command READ timed out\n",
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DRIVER_NAME);
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return TIMEOUT;
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return TIMEOUT;
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}
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debug("%s: command READ error\n", DRIVER_NAME);
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return COMM_ERR;
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return COMM_ERR;
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}
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}
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timeout--;
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if ((get_timer(0) - start) > TIMEOUT_DELAY) {
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udelay(1);
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debug("%s: command timed out\n", DRIVER_NAME);
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if (timeout <= 0) {
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printf("%s: command timed out\n", DRIVER_NAME);
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return TIMEOUT;
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return TIMEOUT;
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}
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}
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}
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}
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
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return TIMEOUT;
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/* Handling response */
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/* Handling response */
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if (cmd->resp_type & MMC_RSP_136) {
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if (cmd->resp_type & MMC_RSP_136) {
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@ -204,6 +216,11 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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cmd->response[1] = ((response[0] & 0xfc00) >> 10);
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cmd->response[1] = ((response[0] & 0xfc00) >> 10);
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cmd->response[2] = 0;
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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cmd->response[3] = 0;
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} else {
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cmd->response[0] = 0;
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cmd->response[1] = 0;
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cmd->response[2] = 0;
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cmd->response[3] = 0;
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}
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}
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debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
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debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
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@ -213,6 +230,10 @@ static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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debug("[0x%x] ", cmd->response[3]);
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debug("[0x%x] ", cmd->response[3]);
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debug("\n");
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debug("\n");
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if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
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(SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
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return TIMEOUT;
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return 0;
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return 0;
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}
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}
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@ -251,9 +272,8 @@ static void mvebu_mmc_set_clk(unsigned int clock)
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if (m > MVEBU_MMC_BASE_DIV_MAX)
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if (m > MVEBU_MMC_BASE_DIV_MAX)
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m = MVEBU_MMC_BASE_DIV_MAX;
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m = MVEBU_MMC_BASE_DIV_MAX;
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mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
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mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
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debug("%s: clock (%d) div : %d\n", DRIVER_NAME, clock, m);
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}
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}
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udelay(10*1000);
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}
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}
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static void mvebu_mmc_set_bus(unsigned int bus)
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static void mvebu_mmc_set_bus(unsigned int bus)
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@ -293,7 +313,6 @@ static void mvebu_mmc_set_bus(unsigned int bus)
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"high-speed" : "");
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"high-speed" : "");
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mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
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mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
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udelay(10*1000);
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}
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}
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static void mvebu_mmc_set_ios(struct mmc *mmc)
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static void mvebu_mmc_set_ios(struct mmc *mmc)
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@ -355,7 +374,7 @@ static void mvebu_window_setup(void)
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static int mvebu_mmc_initialize(struct mmc *mmc)
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static int mvebu_mmc_initialize(struct mmc *mmc)
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{
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{
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debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
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debug("%s: mvebu_mmc_initialize\n", DRIVER_NAME);
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/*
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/*
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* Setting host parameters
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* Setting host parameters
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@ -384,8 +403,6 @@ static int mvebu_mmc_initialize(struct mmc *mmc)
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/* SW reset */
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/* SW reset */
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mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
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udelay(10*1000);
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return 0;
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return 0;
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}
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}
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@ -79,6 +79,7 @@
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#define CMD_INHIBIT (1 << 0)
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#define CMD_INHIBIT (1 << 0)
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#define CMD_TXACTIVE (1 << 8)
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#define CMD_TXACTIVE (1 << 8)
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#define CMD_RXACTIVE (1 << 9)
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#define CMD_RXACTIVE (1 << 9)
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#define CMD_FIFO_EMPTY (1 << 13)
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#define CMD_AUTOCMD12ACTIVE (1 << 14)
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#define CMD_AUTOCMD12ACTIVE (1 << 14)
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#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
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#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
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CMD_RXACTIVE | \
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CMD_RXACTIVE | \
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