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meson: use the clock driver

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Use the clk framework to initialize clocks from drivers that need them
instead of having hardcoded frequencies and initializations from board
code.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Beniamino Galvani
2018-06-14 13:43:40 +02:00
committed by Tom Rini
parent c0fc1e215c
commit 2e668af553
5 changed files with 18 additions and 22 deletions
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10
arch/arm/include/asm/arch-meson/gx.h
View File

@@ -56,14 +56,4 @@
/* Ethernet memory power domain */
#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
/* Clock gates */
#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50)
#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51)
#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52)
#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53)
#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54)
#define GX_GCLK_MPEG_0_I2C BIT(9)
#define GX_GCLK_MPEG_1_ETH BIT(3)
#endif /* __GX_H__ */

3
arch/arm/mach-meson/eth.c
View File

@@ -48,7 +48,6 @@ void meson_gx_eth_init(phy_interface_t mode, unsigned int flags)
return;
}
/* Enable power and clock gate */
setbits_le32(GX_GCLK_MPEG_1, GX_GCLK_MPEG_1_ETH);
/* Enable power gate */
clrbits_le32(GX_MEM_PD_REG_0, GX_MEM_PD_REG_0_ETH_MASK);
}