leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rockchip: clk: Add rv1108 SARADC clock support

Browse Source 
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
David Wu
2017-09-20 14:28:18 +08:00
committed by Philipp Tomsich
parent ae3ed042ed
commit 2e4ce50d1a
3 changed files with 39 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
arch/arm/include/asm/arch-rockchip/cru_rv1108.h
View File

@@ -90,6 +90,11 @@ enum {
CORE_CLK_DIV_SHIFT = 0,
CORE_CLK_DIV_MASK = 0x1f << CORE_CLK_DIV_SHIFT,
/* CLKSEL_CON22 */
CLK_SARADC_DIV_CON_SHIFT= 0,
CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
CLK_SARADC_DIV_CON_WIDTH= 10,
/* CLKSEL24_CON */
MAC_PLL_SEL_SHIFT = 12,
MAC_PLL_SEL_MASK = 1 << MAC_PLL_SEL_SHIFT,