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u-boot-imx-20220413

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i.MX patches for 2022.07
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11710
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Merge tag 'u-boot-imx-20220413' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20220413

i.MX patches for 2022.07

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/11710
This commit is contained in:
Tom Rini 2022-04-13 08:00:11 -04:00
commit 2ddf84679d
365 changed files with 19857 additions and 2200 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
MAINTAINERS
View File

@ -883,6 +883,12 @@ T: git https://source.denx.de/u-boot/custodians/u-boot-fsl-qoriq.git
F: drivers/watchdog/sp805_wdt.c
F: drivers/watchdog/sbsa_gwdt.c
GATEWORKS_SC
M: Tim Harvey <tharvey@gateworks.com>
S: Maintained
F: drivers/misc/gsc.c
F: include/gsc.h
I2C
M: Heiko Schocher <hs@denx.de>
S: Maintained
@ -1413,3 +1419,9 @@ T: git https://source.denx.de/u-boot/u-boot.git
F: configs/tools-only_defconfig
F: *
F: */
CAAM
M: Gaurav Jain <gaurav.jain@nxp.com>
S: Maintained
F: drivers/crypto/fsl/
F: include/fsl_sec.h

9
arch/arm/Kconfig
View File

@ -853,6 +853,9 @@ config ARCH_LPC32XX
config ARCH_IMX8
bool "NXP i.MX8 platform"
select ARM64
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select DM
select GPIO_EXTRA_HEADER
select MACH_IMX
@ -865,7 +868,7 @@ config ARCH_IMX8M
select ARM64
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select SYS_I2C_MXC
@ -923,7 +926,7 @@ config ARCH_MX7ULP
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select ROM_UNIFIED_SECTIONS
@ -936,7 +939,7 @@ config ARCH_MX7
select CPU_V7A
select GPIO_EXTRA_HEADER
select MACH_IMX
select SYS_FSL_HAS_SEC if IMX_HAB
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
imply BOARD_EARLY_INIT_F

18
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -20,6 +21,7 @@
#include <config.h>
#include <fsl_wdog.h>
#include <linux/delay.h>
#include <dm.h>
#include "fsl_epu.h"
@ -397,3 +399,19 @@ void arch_preboot_os(void)
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
#endif

11
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2020 NXP
* Copyright 2017-2021 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*/
@ -49,6 +49,7 @@
#endif
#endif
#include <linux/mii.h>
#include <dm.h>
DECLARE_GLOBAL_DATA_PTR;
@ -1652,6 +1653,14 @@ __weak int serdes_misc_init(void)
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
serdes_misc_init();
return 0;

5
arch/arm/dts/Makefile
View File

@ -900,19 +900,24 @@ dtb-$(CONFIG_ARCH_IMX8ULP) += \
imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-data-modul-edm-sbc.dtb \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-mx8menlo.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
imx8mm-venice-gw73xx-0x.dtb \
imx8mm-venice-gw7901.dtb \
imx8mm-venice-gw7902.dtb \
imx8mm-venice-gw7903.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \

61
arch/arm/dts/fsl-imx8dx.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -261,6 +261,30 @@
power-domains = <&pd_dma>;
};
};
pd_caam: PD_CAAM {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_caam_jr1: PD_CAAM_JR1 {
reg = <SC_R_CAAM_JR1>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr2: PD_CAAM_JR2 {
reg = <SC_R_CAAM_JR2>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr3: PD_CAAM_JR3 {
reg = <SC_R_CAAM_JR3>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
};
};
i2c0: i2c@5a800000 {
@ -609,6 +633,41 @@
};
};
};
crypto: caam@0x31400000 {
compatible = "fsl,sec-v4.0";
reg = <0 0x31400000 0 0x400000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x31400000 0x400000>;
fsl,first-jr-index = <2>;
fsl,sec-era = <9>;
sec_jr1: jr1@0x20000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr1>;
status = "disabled";
};
sec_jr2: jr2@30000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x30000 0x1000>;
interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr2>;
status = "okay";
};
sec_jr3: jr3@40000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x40000 0x1000>;
interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr3>;
status = "okay";
};
};
};
&A35_0 {

34
arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
&{/imx8qm-pm} {
@ -80,6 +80,22 @@
u-boot,dm-spl;
};
&pd_caam {
u-boot,dm-spl;
};
&pd_caam_jr1 {
u-boot,dm-spl;
};
&pd_caam_jr2 {
u-boot,dm-spl;
};
&pd_caam_jr3 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&sec_jr3 {
u-boot,dm-spl;
};

61
arch/arm/dts/fsl-imx8qm.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@ -235,6 +235,30 @@
wakeup-irq = <349>;
};
};
pd_caam: PD_CAAM {
compatible = "nxp,imx8-pd";
reg = <SC_R_NONE>;
#power-domain-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
pd_caam_jr1: PD_CAAM_JR1 {
reg = <SC_R_CAAM_JR1>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr2: PD_CAAM_JR2 {
reg = <SC_R_CAAM_JR2>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
pd_caam_jr3: PD_CAAM_JR3 {
reg = <SC_R_CAAM_JR3>;
#power-domain-cells = <0>;
power-domains = <&pd_caam>;
};
};
};
i2c0: i2c@5a800000 {
@ -556,6 +580,41 @@
power-domains = <&pd_conn_enet1>;
status = "disabled";
};
crypto: caam@0x31400000 {
compatible = "fsl,sec-v4.0";
reg = <0 0x31400000 0 0x400000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x31400000 0x400000>;
fsl,first-jr-index = <2>;
fsl,sec-era = <9>;
sec_jr1: jr1@0x20000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr1>;
status = "disabled";
};
sec_jr2: jr2@30000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x30000 0x1000>;
interrupts = <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr2>;
status = "okay";
};
sec_jr3: jr3@40000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x40000 0x1000>;
interrupts = <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_caam_jr3>;
status = "okay";
};
};
};
&A53_0 {

34
arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
&{/imx8qx-pm} {
@ -80,6 +80,22 @@
u-boot,dm-spl;
};
&pd_caam {
u-boot,dm-spl;
};
&pd_caam_jr1 {
u-boot,dm-spl;
};
&pd_caam_jr2 {
u-boot,dm-spl;
};
&pd_caam_jr3 {
u-boot,dm-spl;
};
&gpio0 {
u-boot,dm-spl;
};
@ -126,3 +142,19 @@
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&sec_jr3 {
u-boot,dm-spl;
};

46
arch/arm/dts/fsl-ls1012a.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright 2016 Freescale Semiconductor
*/
@ -71,6 +71,50 @@
bus-width = <4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
gpio0: gpio@2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;

45
arch/arm/dts/fsl-ls1043a.dtsi
View File

@ -2,7 +2,7 @@
/*
* Device Tree Include file for NXP Layerscape-1043A family SoC.
*
* Copyright 2020 NXP
* Copyright 2020-2021 NXP
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
@ -125,6 +125,49 @@
interrupts = <0 43 0x4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <3>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

44
arch/arm/dts/fsl-ls1046a.dtsi
View File

@ -3,6 +3,7 @@
* Device Tree Include file for Freescale Layerscape-1046A family SoC.
*
* Copyright (C) 2016, Freescale Semiconductor
* Copyright 2021 NXP
*
* Mingkai Hu <mingkai.hu@nxp.com>
*/
@ -124,6 +125,49 @@
interrupts = <0 43 0x4>;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
"fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x1700000 0x100000>;
reg = <0x00 0x1700000 0x0 0x100000>;
interrupts = <0 75 0x4>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 71 0x4>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 72 0x4>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 73 0x4>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.4-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 74 0x4>;
};
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;

39
arch/arm/dts/fsl-ls1088a.dtsi
View File

@ -174,6 +174,45 @@
dr_mode = "host";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
pcie1: pcie@3400000 {
compatible = "fsl,ls-pcie", "snps,dw-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */

39
arch/arm/dts/fsl-ls2080a.dtsi
View File

@ -239,6 +239,45 @@
status = "disabled";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <8>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <0 139 0x4>; /* Level high type */
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <0 140 0x4>; /* Level high type */
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <0 141 0x4>; /* Level high type */
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <0 142 0x4>; /* Level high type */
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <0 143 0x4>; /* Level high type */
};
};
fsl_mc: fsl-mc@80c000000 {
compatible = "fsl,qoriq-mc", "simple-mfd";
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */

41
arch/arm/dts/fsl-lx2160a.dtsi
View File

@ -2,7 +2,7 @@
/*
* NXP lx2160a SOC common device tree source
*
* Copyright 2018-2020 NXP
* Copyright 2018-2021 NXP
*
*/
@ -27,6 +27,45 @@
clock-output-names = "sysclk";
};
crypto: crypto@8000000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <10>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x00 0x8000000 0x100000>;
reg = <0x00 0x8000000 0x0 0x100000>;
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
dma-coherent;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
};
};
clockgen: clocking@1300000 {
compatible = "fsl,ls2080a-clockgen";
reg = <0 0x1300000 0 0xa0000>;

17
arch/arm/dts/imx6q-tbs2910-u-boot.dtsi Normal file
View File

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0+
&aips1 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
&soc {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};

4
arch/arm/dts/imx6qdl.dtsi
View File

@ -139,7 +139,7 @@
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
@ -283,7 +283,7 @@
status = "disabled";
};
bus@2000000 { /* AIPS1 */
aips1: bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

1
arch/arm/dts/imx6ull-colibri.dts
View File

@ -15,6 +15,7 @@
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
fsl,use-minimum-ecc;
nand-on-flash-bbt;
nand-ecc-mode = "hw";
nand-ecc-strength = <8>;

34
arch/arm/dts/imx6ull-colibri.dtsi
View File

@ -41,9 +41,9 @@
regulator-max-microvolt = <5000000>;
};
reg_sd1_vmmc: regulator-sd1-vmmc {
reg_sd1_vqmmc: regulator-sd1-vqmmc {
compatible = "regulator-gpio";
gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_snvs_reg_sd>;
regulator-always-on;
@ -64,6 +64,18 @@
gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; /* USBH_PEN */
vin-supply = <&reg_5v0>;
};
reg_eth_phy: regulator-eth-phy {
compatible = "regulator-fixed-clock";
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "eth_phy";
regulator-type = "voltage";
vin-supply = <&reg_module_3v3>;
clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
startup-delay-us = <150000>;
};
};
&adc1 {
@ -84,6 +96,7 @@
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-supply = <&reg_eth_phy>;
status = "okay";
mdio {
@ -220,12 +233,15 @@
assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
assigned-clock-rates = <0>, <198000000>;
bus-width = <4>;
cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* MMC_CD */
disable-wp;
no-1-8-v;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_sd1_vmmc>;
vqmmc-supply = <&reg_sd1_vqmmc>;
status = "okay";
};
@ -460,8 +476,8 @@
pinctrl_usdhc1: usdhc1-grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
@ -471,8 +487,8 @@
pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
@ -482,8 +498,8 @@
pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp {
fsl,pins = <
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9

16
arch/arm/dts/imx7s-warp-u-boot.dtsi
View File

@ -8,3 +8,19 @@
stdout-path = &uart1;
};
};
&aips3 {
u-boot,dm-pre-reloc;
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
&soc {
u-boot,dm-pre-reloc;
};
&uart1 {
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/imx7s.dtsi
View File

@ -184,7 +184,7 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
};
soc {
soc: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";

24
arch/arm/dts/imx7ulp.dtsi
View File

@ -1,5 +1,6 @@
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
@ -198,6 +199,29 @@
};
};
crypto: crypto@40240000 {
compatible = "fsl,sec-v4.0";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40240000 0x10000>;
ranges = <0 0x40240000 0x10000>;
clocks = <&clks IMX7ULP_CLK_CAAM>,
<&clks IMX7ULP_CLK_NIC1_BUS_DIV>;
clock-names = "aclk", "ipg";
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
};
tpm5: tpm@40260000 {
compatible = "fsl,imx7ulp-tpm";
reg = <0x40260000 0x1000>;

12
arch/arm/dts/imx8mm-cl-iot-gate.dts
View File

@ -17,6 +17,11 @@
stdout-path = &uart3;
};
aliases {
eeprom0 = &i2c_eeprom0;
eeprom1 = &i2c_eeprom1;
};
reg_vusb_5v: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VUSB_5V";
@ -79,7 +84,7 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
eeprom@54 {
i2c_eeprom0: eeprom@54 {
compatible = "atmel,24c08";
reg = <0x54>;
pagesize = <16>;
@ -92,6 +97,11 @@
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
i2c_eeprom1: eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
rtc@69 {
compatible = "abracon,ab1805";
reg = <0x69>;

116
arch/arm/dts/imx8mm-data-modul-edm-sbc-u-boot.dtsi Normal file
View File

@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
eeprom0 = &eeprom;
mmc0 = &usdhc3; /* eMMC */
mmc1 = &usdhc2; /* MicroSD */
};
config {
dmo,ram-coding-gpios = <&gpio2 8 0>, <&gpio2 1 0>, <&gpio2 0 0>;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&buck4_reg {
u-boot,dm-spl;
};
&buck5_reg {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_hog_sbc {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1_gpio {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_uart3 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&pmic {
u-boot,dm-spl;
regulators {
u-boot,dm-spl;
};
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};
&usbotg1 {
dr_mode = "peripheral";
};
&usdhc2 {
u-boot,dm-spl;
sd-uhs-sdr104;
sd-uhs-ddr50;
};
&usdhc3 {
u-boot,dm-spl;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
};
&wdog1 {
u-boot,dm-spl;
};

996
arch/arm/dts/imx8mm-data-modul-edm-sbc.dts Normal file
View File

@ -0,0 +1,996 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Marek Vasut <marex@denx.de>
*/
/dts-v1/;
#include <dt-bindings/net/qca-ar803x.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
model = "Data Modul i.MX8M Mini eDM SBC";
compatible = "dmo,imx8mm-data-modul-edm-sbc", "fsl,imx8mm";
aliases {
rtc0 = &rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart3;
};
memory@40000000 {
device_type = "memory";
/* There are 1/2/4 GiB options, adjusted by bootloader. */
reg = <0x0 0x40000000 0 0x40000000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_backlight>;
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
clk_xtal25: clk-xtal25 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
panel: panel {
backlight = <&backlight>;
power-supply = <&reg_panel_vcc>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_panel_vcc: regulator-panel-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_vcc_reg>;
regulator-name = "PANEL_VCC";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio3 6 0>;
enable-active-high;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
reg_usdhc2_vcc: regulator-usdhc2-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vcc_reg>;
regulator-name = "V_3V3_SD";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 0>;
enable-active-high;
};
watchdog-gpio {
/* TPS3813 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_watchdog_gpio>;
compatible = "linux,wdt-gpio";
always-enabled;
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
hw_algo = "level";
/* Reset triggers in 2..3 seconds */
hw_margin_ms = <1500>;
/* Disabled by default */
status = "disabled";
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
flash@0 { /* W25Q128FVSI */
compatible = "jedec,spi-nor";
m25p,fast-read;
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&ecspi2 { /* Feature connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless feature board plugged in. */
status = "disabled";
};
&ecspi3 { /* Display connector SPI */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&fec1_phy>;
phy-supply = <&buck4_reg>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
/* Atheros AR8031 PHY */
fec1_phy: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/*
* Dedicated ENET_WOL# signal is unused, the PHY
* can wake the SoC up via INT signal as well.
*/
interrupts-extended = <&gpio1 15 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <10000>;
qca,clk-out-frequency = <125000000>;
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
qca,keep-pll-enabled;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-name = "VDDIO";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vddh: vddh-regulator {
regulator-name = "VDDH";
};
};
};
};
&gpio1 {
gpio-line-names =
"", "ENET_RST#", "WDOG_B#", "PMIC_INT#",
"", "M2-B_PCIE_RST#", "M2-B_PCIE_WAKE#", "RTC_IRQ#",
"WDOG_KICK#", "M2-B_PCIE_CLKREQ#",
"USB1_OTG_ID_3V3", "ENET_WOL#",
"", "", "", "ENET_INT#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"MEMCFG2", "MEMCFG1", "DSI_RESET_1V8#", "DSI_IRQ_1V8#",
"M2-B_FULL_CARD_PWROFF_1V8#", "EEPROM_WP_1V8#",
"PCIE_CLK_GEN_CLKPWRGD_PD_1V8#", "GRAPHICS_PRSNT_1V8#",
"MEMCFG0", "WDOG_EN",
"M2-B_W_DISABLE1_WWAN_1V8#", "M2-B_W_DISABLE2_GPS_1V8#",
"", "", "", "",
"", "", "", "SD2_RESET#", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"BL_ENABLE_1V8", "PG_V_IN_VAR#", "", "",
"", "", "TFT_ENABLE_1V8", "GRAPHICS_GPIO0_1V8",
"CSI_PD_1V8", "CSI_RESET_1V8#", "", "",
"", "", "", "",
"", "", "", "M2-B_WAKE_WWAN_1V8#",
"M2-B_RESET_1V8#", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"NC0", "NC1", "BOOTCFG0", "BOOTCFG1",
"BOOTCFG2", "BOOTCFG3", "BOOTCFG4", "BOOTCFG5",
"BOOTCFG6", "BOOTCFG7", "NC10", "NC11",
"BOOTCFG8", "BOOTCFG9", "BOOTCFG10", "BOOTCFG11",
"BOOTCFG12", "BOOTCFG13", "BOOTCFG14", "BOOTCFG15",
"NC20", "", "", "",
"", "CAN_INT#", "CAN_RST#", "GPIO4_IO27",
"DIS_USB_DN2", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "DIS_USB_DN1", "USBHUB_RESET#", "GPIO5_IO03",
"GPIO5_IO04", "", "", "",
"", "SPI1_CS#", "", "",
"", "SPI2_CS#", "I2C1_SCL_3V3", "I2C1_SDA_3V3",
"I2C2_SCL_3V3", "I2C2_SDA_3V3", "I2C3_SCL_3V3", "I2C3_SDA_3V3",
"I2C4_SCL_3V3", "I2C4_SDA_3V3", "", "",
"", "SPI3_CS#", "", "", "", "", "", "";
};
&i2c1 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pmic: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
rohm,reset-snvs-powered;
/*
* i.MX 8M Mini Data Sheet for Consumer Products
* 3.1.3 Operating ranges
* MIMX8MM4DVTLZAA
*/
regulators {
/* VDD_SOC */
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
/* VDD_ARM */
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1050000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <950000>;
};
/* VDD_DRAM, BUCK5 */
buck3_reg: BUCK3 {
regulator-name = "buck3";
/* 1.5 GHz DDR bus clock */
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
/* 3V3_VDD, BUCK6 */
buck4_reg: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_VDD, BUCK7 */
buck5_reg: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V1_NVCC_DRAM, BUCK8 */
buck6_reg: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_NVCC_SNVS */
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 0V8_VDD_SNVS */
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V8_VDDA */
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
/* 0V9_VDD_PHY */
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* 1V2_VDD_PHY */
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
usb-hub@2c {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
compatible = "microchip,usb2514bi";
reg = <0x2c>;
individual-port-switching;
reset-gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
self-powered;
};
eeprom: eeprom@50 {
compatible = "atmel,24c32";
reg = <0x50>;
pagesize = <32>;
};
rtc: rtc@68 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
compatible = "st,m41t62";
reg = <0x68>;
interrupts-extended = <&gpio1 7 IRQ_TYPE_LEVEL_LOW>;
};
pcieclk: clk@6a {
compatible = "renesas,9fgv0241";
reg = <0x6a>;
clocks = <&clk_xtal25>;
#clock-cells = <1>;
};
};
&i2c3 { /* Display connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&i2c4 { /* Feature connector I2C */
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <320000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog_feature>, <&pinctrl_hog_misc>,
<&pinctrl_hog_panel>, <&pinctrl_hog_sbc>,
<&pinctrl_panel_expansion>;
pinctrl_ecspi1: ecspi1-grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x44
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x44
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x44
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
>;
};
pinctrl_ecspi2: ecspi2-grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x44
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x44
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x44
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40
>;
};
pinctrl_ecspi3: ecspi3-grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x44
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x44
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x44
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x40
>;
};
pinctrl_fec1: fec1-grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
/* ENET_RST# */
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x6
/* ENET_WOL# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000090
/* ENET_INT# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000090
>;
};
pinctrl_hog_feature: hog-feature-grp {
fsl,pins = <
/* GPIO4_IO27 */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000006
/* GPIO5_IO03 */
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000006
/* GPIO5_IO04 */
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000006
/* CAN_INT# */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000090
/* CAN_RST# */
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x26
>;
};
pinctrl_hog_panel: hog-panel-grp {
fsl,pins = <
/* GRAPHICS_GPIO0_1V8 */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x26
>;
};
pinctrl_hog_misc: hog-misc-grp {
fsl,pins = <
/* PG_V_IN_VAR# */
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000000
/* CSI_PD_1V8 */
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x0
/* CSI_RESET_1V8# */
MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x0
/* DIS_USB_DN1 */
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x0
/* DIS_USB_DN2 */
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x0
/* EEPROM_WP_1V8# */
MX8MM_IOMUXC_SD1_DATA3_GPIO2_IO5 0x100
/* PCIE_CLK_GEN_CLKPWRGD_PD_1V8# */
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x0
/* GRAPHICS_PRSNT_1V8# */
MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x40000000
/* CLK_CCM_CLKO1_3V3 */
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x10
>;
};
pinctrl_hog_sbc: hog-sbc-grp {
fsl,pins = <
/* MEMCFG[0..2] straps */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000140
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000140
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000140
/* BOOT_CFG[0..15] straps */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x40000000
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000000
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000000
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x40000000
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x40000000
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000000
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x40000000
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x40000000
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000000
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x40000000
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000000
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x40000000
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x40000000
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x40000000
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x40000000
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x40000000
/* Not connected pins */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x0
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x0
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x0
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x0
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x0
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000084
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000084
>;
};
pinctrl_i2c1_gpio: i2c1-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x84
MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x84
>;
};
pinctrl_i2c2: i2c2-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000084
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000084
>;
};
pinctrl_i2c2_gpio: i2c2-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x84
MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x84
>;
};
pinctrl_i2c3: i2c3-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000084
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000084
>;
};
pinctrl_i2c3_gpio: i2c3-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x84
MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x84
>;
};
pinctrl_i2c4: i2c4-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000084
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000084
>;
};
pinctrl_i2c4_gpio: i2c4-gpio-grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x84
MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x84
>;
};
pinctrl_panel_backlight: panel-backlight-grp {
fsl,pins = <
/* BL_ENABLE_1V8 */
MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x104
>;
};
pinctrl_panel_expansion: panel-expansion-grp {
fsl,pins = <
/* DSI_RESET_1V8# */
MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x2
/* DSI_IRQ_1V8# */
MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x40000090
>;
};
pinctrl_panel_vcc_reg: panel-vcc-grp {
fsl,pins = <
/* TFT_ENABLE_1V8 */
MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x104
>;
};
pinctrl_panel_pwm: panel-pwm-grp {
fsl,pins = <
/* BL_PWM_3V3 */
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x12
>;
};
pinctrl_pcie0: pcie-grp {
fsl,pins = <
/* M2-B_RESET_1V8# */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x102
/* M2-B_PCIE_RST# */
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x2
/* M2-B_FULL_CARD_PWROFF_1V8# */
MX8MM_IOMUXC_SD1_DATA2_GPIO2_IO4 0x102
/* M2-B_W_DISABLE1_WWAN_1V8# */
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x102
/* M2-B_W_DISABLE2_GPS_1V8# */
MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x102
/* CLK_M2_32K768 */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x14
/* M2-B_WAKE_WWAN_1V8# */
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x40000140
/* M2-B_PCIE_WAKE# */
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000140
/* M2-B_PCIE_CLKREQ# */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000140
>;
};
pinctrl_pmic: pmic-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x40000090
>;
};
pinctrl_rtc: rtc-grp {
fsl,pins = <
/* RTC_IRQ# */
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000090
>;
};
pinctrl_sai5: sai5-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0x100
MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x0
MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x100
MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x100
MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x100
>;
};
pinctrl_uart1: uart1-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x90
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x90
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x50
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x50
>;
};
pinctrl_uart2: uart2-grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x50
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x90
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x50
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x90
>;
};
pinctrl_uart3: uart3-grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x40
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x40
>;
};
pinctrl_uart4: uart4-grp {
fsl,pins = <
MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x40
MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x40
>;
};
pinctrl_usb_hub: usb-hub-grp {
fsl,pins = <
/* USBHUB_RESET# */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x4
>;
};
pinctrl_usb_otg1: usb-otg1-grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000000
MX8MM_IOMUXC_GPIO1_IO12_USB1_OTG_PWR 0x4
MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x40000090
>;
};
pinctrl_usdhc2_vcc_reg: usdhc2-vcc-reg-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x4
>;
};
pinctrl_usdhc2: usdhc2-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_WP_USDHC2_WP 0x400000d6
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0d6
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhz-grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B 0x40
>;
};
pinctrl_watchdog_gpio: watchdog-gpio-grp {
fsl,pins = <
/* WDOG_B# */
MX8MM_IOMUXC_GPIO1_IO02_GPIO1_IO2 0x26
/* WDOG_EN -- ungate WDT RESET# signal propagation */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x6
/* WDOG_KICK# / WDI */
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x26
>;
};
};
&pcie_phy {
fsl,clkreq-unsupported; /* CLKREQ_B is not connected to suitable input */
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
clocks = <&pcieclk 0>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio1 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcieclk 0>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel_pwm>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&sai5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai5>;
fsl,sai-mclk-direction-output;
/* Input into codec PLL */
assigned-clocks = <&clk IMX8MM_CLK_SAI5>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL2_OUT>;
assigned-clock-rates = <22579200>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "disabled";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "disabled";
};
&uart3 { /* A53 Debug */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 { /* M4 Debug */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
/* UART4 is reserved for CM and RDC blocks CA access to UART4. */
status = "disabled";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 { /* MicroSD */
assigned-clocks = <&clk IMX8MM_CLK_USDHC2_ROOT>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vcc>;
status = "okay";
};
&usdhc3 { /* eMMC */
assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
assigned-clock-rates = <400000000>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
vmmc-supply = <&buck4_reg>;
vqmmc-supply = <&buck5_reg>;
status = "okay";
};
&wdog1 {
status = "okay";
};

18
arch/arm/dts/imx8mm-evk-u-boot.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include "imx8mm-u-boot.dtsi"
@ -68,6 +68,22 @@
u-boot,dm-spl;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

21
arch/arm/dts/imx8mm-evk.dtsi
View File

@ -41,6 +41,15 @@
enable-active-high;
};
backlight: backlight {
status = "disabled";
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <250>;
};
ir-receiver {
compatible = "gpio-ir-receiver";
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
@ -350,6 +359,12 @@
status = "okay";
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
status = "disabled";
};
&iomuxc {
pinctrl_fec1: fec1grp {
fsl,pins = <
@ -491,4 +506,10 @@
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
>;
};
pinctrl_backlight: backlightgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x06
>;
};
};

38
arch/arm/dts/imx8mm-mx8menlo-u-boot.dtsi Normal file
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@ -0,0 +1,38 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021-2022 Marek Vasut <marex@denx.de>
*/
#include "imx8mm-verdin-u-boot.dtsi"
/ {
chosen {
stdout-path = &uart2;
};
aliases {
/delete-property/ eeprom1;
/delete-property/ eeprom2;
usbphy0 = &usbphynop1;
usbphy1 = &usbphynop2;
};
};
&i2c4 {
/delete-node/ codec@1a;
};
&pinctrl_uart1 {
/delete-property/ u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&uart1 {
/delete-property/ u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};

325
arch/arm/dts/imx8mm-mx8menlo.dts Normal file
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@ -0,0 +1,325 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2021-2022 Marek Vasut <marex@denx.de>
*/
#include "imx8mm-verdin.dts"
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
compatible = "menlo,mx8menlo",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
/delete-node/ gpio-keys;
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_led>;
user1 {
label = "TestLed601";
gpios = <&gpio4 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
user2 {
label = "TestLed602";
gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
beeper {
compatible = "gpio-beeper";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
};
};
&ecspi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
status = "okay";
/* CAN controller on the baseboard */
canfd: can@0 {
compatible = "microchip,mcp2518fd";
clocks = <&clk20m>;
gpio-controller;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
reg = <0>;
spi-max-frequency = <2000000>;
status = "okay";
};
};
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&ethphy0 {
max-speed = <100>;
};
&fec1 {
status = "okay";
};
&flexspi {
status = "okay";
flash@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <66000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <4>;
};
};
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "DISP_reset", "KBD_intI",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
/*
* CPLD_D[n] is ARM_CPLD[n] in schematic
* CPLD_int is SA_INTERRUPT in schematic
* CPLD_reset is RESET_SOFT in schematic
*/
gpio-line-names =
"CPLD_D[1]", "CPLD_int", "CPLD_reset", "",
"", "CPLD_D[0]", "", "",
"", "", "", "CPLD_D[2]",
"CPLD_D[3]", "CPLD_D[4]", "CPLD_D[5]", "CPLD_D[6]",
"CPLD_D[7]", "", "", "",
"", "", "", "",
"", "", "", "KBD_intK",
"", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio_expander_21 {
status = "okay";
};
&i2c1 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
};
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
};
&i2c3 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
status = "okay";
};
&i2c4 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
/delete-node/ bridge@2c;
/delete-node/ hwmon@40;
/delete-node/ hdmi@48;
/delete-node/ touch@4a;
/delete-node/ hwmontemp@4f;
/delete-node/ eeprom@50;
/delete-node/ eeprom@57;
};
&iomuxc {
pinctrl-0 = <&pinctrl_gpio7>, <&pinctrl_gpio_hog1>,
<&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>;
pinctrl_beeper: beepergrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x1c4
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x4
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x4
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x1c4
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x1c4
>;
};
pinctrl_led: ledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4
MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4
>;
};
pinctrl_uart4_rts: uart4rtsgrp {
fsl,pins = <
/* SODIMM 222 */
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184
>;
};
};
&pinctrl_gpio1 {
fsl,pins = <
/* SODIMM 206 */
MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x1c4
>;
};
&pinctrl_gpio_hog1 {
fsl,pins = <
/* SODIMM 88 */
MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4
/* CPLD_int */
MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4
/* CPLD_reset */
MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4
/* SODIMM 94 */
MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4
/* SODIMM 96 */
MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4
/* CPLD_D[7] */
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4
/* CPLD_D[6] */
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4
/* CPLD_D[5] */
MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4
/* CPLD_D[4] */
MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4
/* CPLD_D[3] */
MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4
/* CPLD_D[2] */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4
/* CPLD_D[1] */
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4
/* CPLD_D[0] */
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4
/* KBD_intK */
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x1c4
/* DISP_reset */
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x1c4
/* KBD_intI */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x1c4
/* SODIMM 46 */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x1c4
>;
};
&pinctrl_uart1 {
fsl,pins = <
/* SODIMM 149 */
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x1c4
/* SODIMM 147 */
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x1c4
/* SODIMM 210 */
MX8MM_IOMUXC_UART3_RXD_UART1_DTE_RTS_B 0x1c4
/* SODIMM 212 */
MX8MM_IOMUXC_UART3_TXD_UART1_DTE_CTS_B 0x1c4
>;
};
&reg_usb_otg1_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
};
&reg_usb_otg2_vbus {
/delete-property/ enable-active-high;
gpio = <&gpio1 14 GPIO_ACTIVE_LOW>;
};
&sai2 {
status = "disabled";
};
&uart1 {
uart-has-rtscts;
status = "okay";
};
&uart2 {
uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-0 = <&pinctrl_uart4 &pinctrl_uart4_rts>;
linux,rs485-enabled-at-boot-time;
rts-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&usbotg1 {
dr_mode = "gadget";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
&usdhc2 {
status = "okay";
};

2
arch/arm/dts/imx8mm-u-boot.dtsi
View File

@ -109,7 +109,7 @@
atf-blob {
filename = "bl31.bin";
type = "blob-ext";
type = "atf-bl31";
};
};

7
arch/arm/dts/imx8mm-venice-gw7902.dts
View File

@ -348,6 +348,13 @@
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;

28
arch/arm/dts/imx8mm-venice-gw7903-u-boot.dtsi Normal file
View File

@ -0,0 +1,28 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2022 Gateworks Corporation
*/
#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>;
phy-reset-duration = <1>;
phy-reset-post-delay = <300>;
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};

832
arch/arm/dts/imx8mm-venice-gw7903.dts Normal file
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@ -0,0 +1,832 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2022 Gateworks Corporation
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
/ {
model = "Gateworks Venice GW7903 i.MX8MM board";
compatible = "gw,imx8mm-gw7903", "fsl,imx8mm";
aliases {
ethernet0 = &fec1;
usb0 = &usbotg1;
};
chosen {
stdout-path = &uart2;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
};
gpio-keys {
compatible = "gpio-keys";
user-pb {
label = "user_pb";
gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
user-pb1x {
label = "user_pb1x";
linux,code = <BTN_1>;
interrupt-parent = <&gsc>;
interrupts = <0>;
};
key-erased {
label = "key_erased";
linux,code = <BTN_2>;
interrupt-parent = <&gsc>;
interrupts = <1>;
};
eeprom-wp {
label = "eeprom_wp";
linux,code = <BTN_3>;
interrupt-parent = <&gsc>;
interrupts = <2>;
};
switch-hold {
label = "switch_hold";
linux,code = <BTN_5>;
interrupt-parent = <&gsc>;
interrupts = <7>;
};
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led01_red";
gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led01_grn";
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-2 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led02_red";
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-3 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led02_grn";
gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-4 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led03_red";
gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-5 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led03_grn";
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-6 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led04_red";
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-7 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led04_grn";
gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-8 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led05_red";
gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-9 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led05_grn";
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-a {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
label = "led06_red";
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
led-b {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "led06_grn";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
local-mac-address = [00 00 00 00 00 00];
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2500>;
};
};
};
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "rs422_en#", "rs485_en#", "rs232_en#", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names = "dig2_in", "dig2_out#", "", "", "", "", "", "",
"dig1_out#", "dig1_in", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio5 {
gpio-line-names = "", "", "", "", "", "", "", "sim1_det#",
"sim2_det#", "sim2_sel", "", "", "pci_wdis#", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
gsc: gsc@20 {
compatible = "gw,gsc";
reg = <0x20>;
pinctrl-0 = <&pinctrl_gsc>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
adc {
compatible = "gw,gsc-adc";
#address-cells = <1>;
#size-cells = <0>;
channel@6 {
gw,mode = <0>;
reg = <0x06>;
label = "temp";
};
channel@8 {
gw,mode = <1>;
reg = <0x08>;
label = "vdd_bat";
};
channel@82 {
gw,mode = <2>;
reg = <0x82>;
label = "vin";
gw,voltage-divider-ohms = <22100 1000>;
gw,voltage-offset-microvolt = <700000>;
};
channel@84 {
gw,mode = <2>;
reg = <0x84>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@86 {
gw,mode = <2>;
reg = <0x86>;
label = "vdd_3p3";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@88 {
gw,mode = <2>;
reg = <0x88>;
label = "vdd_0p9";
};
channel@8c {
gw,mode = <2>;
reg = <0x8c>;
label = "vdd_soc";
};
channel@8e {
gw,mode = <2>;
reg = <0x8e>;
label = "vdd_arm";
};
channel@90 {
gw,mode = <2>;
reg = <0x90>;
label = "vdd_1p8";
};
channel@92 {
gw,mode = <2>;
reg = <0x92>;
label = "vdd_dram";
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;
label = "vdd_gsc";
gw,voltage-divider-ohms = <10000 10000>;
};
};
};
gpio: gpio@23 {
compatible = "nxp,pca9555";
reg = <0x23>;
gpio-controller;
#gpio-cells = <2>;
interrupt-parent = <&gsc>;
interrupts = <4>;
};
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
pagesize = <16>;
};
eeprom@51 {
compatible = "atmel,24c02";
reg = <0x51>;
pagesize = <16>;
};
eeprom@52 {
compatible = "atmel,24c02";
reg = <0x52>;
pagesize = <16>;
};
eeprom@53 {
compatible = "atmel,24c02";
reg = <0x53>;
pagesize = <16>;
};
rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio3>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
/* vdd_soc: 0.805-0.900V (typ=0.8V) */
BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
/* vdd_arm: 0.805-1.0V (typ=0.9V) */
buck2: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
/* vdd_0p9: 0.805-1.0V (typ=0.9V) */
BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_3p3 */
BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_1p8 */
BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_dram */
BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
/* nvcc_snvs_1p8 */
LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_snvs_0p8 */
LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* vdda_1p8 */
LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
accelerometer@19 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <15 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 11 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
/* off-board RS232/RS485/RS422 */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
cts-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
dtr-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
/* console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&usbotg1 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
vmmc-supply = <&reg_3p3v>;
status = "okay";
};
/* eMMC */
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x40000041 /* RS422# */
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x40000041 /* RS485# */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x40000041 /* RS232# */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x40000041 /* DIG1_IN */
MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* DIG1_OUT */
MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x40000041 /* DIG2_IN */
MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x40000041 /* DIG2_OUT */
MX8MM_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x40000041 /* SIM1DET# */
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x40000041 /* SIM2DET# */
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40000041 /* SIM2SEL */
MX8MM_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x40000041 /* PCI_WDIS# */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x159
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x19 /* IRQ# */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* RST# */
>;
};
pinctrl_gsc: gscgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x159
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x19
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x19
MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x19
MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x41
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x140
MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x140
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x140
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x140
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
pinctrl_usdhc2_gpio: usdhc2-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

423
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi Normal file
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@ -0,0 +1,423 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn.dtsi"
/ {
chosen {
stdout-path = &uart4;
};
fec_supply: fec_supply_en {
compatible = "regulator-fixed";
regulator-name = "tja1101_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vin-supply = <&buck4_reg>;
enable-active-high;
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&fec_supply>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
bd71847: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
/* PMIC_BUCK1 - VDD_SOC */
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
/* PMIC_BUCK2 - VDD_ARM */
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck3_reg: BUCK3 {
/* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
/* PMIC_BUCK6 - VDD_3V3 */
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
/* PMIC_BUCK7 - VDD_1V8 */
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
/* PMIC_BUCK8 - NVCC_DRAM */
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
/* PMIC_LDO1 - NVCC_SNVS_1V8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
/* PMIC_LDO2 - VDD_SNVS_0V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
/* PMIC_LDO3 - VDDA_1V8 */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
/* PMIC_LDO4 - VDD_MIPI_0V9 */
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 {
/* PMIC_LDO6 - VDD_MIPI_1V2 */
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bluetooth>;
shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
};
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
disable-over-current;
status = "okay";
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
mmc-pwrseq = <&usdhc2_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: bcrmf@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
>;
};
pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
>;
};
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
>;
};
};

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@ -0,0 +1,225 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_uart4 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart4 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
1d-imem {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
1d_dmem {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

15
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_gpmi_nand {
u-boot,dm-spl;
};
&gpmi {
u-boot,dm-spl;
};

48
arch/arm/dts/imx8mn-bsh-smm-s2.dts Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
/ {
model = "BSH SMM S2";
compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn";
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x10000000>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
>;
};
};

15
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

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@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
/ {
model = "BSH SMM S2 PRO";
compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
>;
};
};

18
arch/arm/dts/imx8mn-ddr4-evk-u-boot.dtsi
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
/ {
@ -104,6 +104,22 @@
u-boot,dm-spl;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

10
arch/arm/dts/imx8mn-evk.dtsi
View File

@ -53,7 +53,6 @@
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy0>;
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
fsl,magic-packet;
status = "okay";
@ -64,6 +63,15 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};

2
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
View File

@ -200,7 +200,7 @@
atf_blob {
filename = "bl31.bin";
type = "blob-ext";
type = "atf-bl31";
};
};

7
arch/arm/dts/imx8mn-venice-gw7902.dts
View File

@ -347,6 +347,13 @@
gw,voltage-divider-ohms = <10000 10000>;
};
channel@9c {
gw,mode = <2>;
reg = <0x9c>;
label = "vdd_5p0";
gw,voltage-divider-ohms = <10000 10000>;
};
channel@a2 {
gw,mode = <2>;
reg = <0xa2>;

19
arch/arm/dts/imx8mp-evk-u-boot.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
* Copyright 2019, 2021 NXP
*/
#include "imx8mp-u-boot.dtsi"
@ -67,6 +67,22 @@
u-boot,dm-spl;
};
&crypto {
u-boot,dm-spl;
};
&sec_jr0 {
u-boot,dm-spl;
};
&sec_jr1 {
u-boot,dm-spl;
};
&sec_jr2 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
@ -112,7 +128,6 @@
};
&eqos {
compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;

3
arch/arm/dts/imx8mp-u-boot.dtsi
View File

@ -123,8 +123,9 @@
load = <0x970000>;
entry = <0x970000>;
atf_blob: blob-ext {
atf_blob: atf-blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};

1
arch/arm/dts/imx8mp-verdin-u-boot.dtsi
View File

@ -30,7 +30,6 @@
};
&eqos {
compatible = "fsl,imx-eqos";
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;

15
arch/arm/dts/imx8mp.dtsi
View File

@ -761,6 +761,21 @@
status = "disabled";
};
flexspi: spi@30bb0000 {
compatible = "nxp,imx8mp-fspi";
reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
reg-names = "fspi_base", "fspi_mmap";
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
<&clk IMX8MP_CLK_QSPI_ROOT>;
clock-names = "fspi_en", "fspi";
assigned-clock-rates = <80000000>;
assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
sdma1: dma-controller@30bd0000 {
compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
reg = <0x30bd0000 0x10000>;

4
arch/arm/dts/imxrt1020-evk-u-boot.dtsi
View File

@ -22,6 +22,10 @@
u-boot,dm-spl;
};
&anatop {
u-boot,dm-spl;
};
&clks {
u-boot,dm-spl;
};

2
arch/arm/dts/imxrt1020-evk.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "imxrt1020.dtsi"
#include "imxrt1020-evk-u-boot.dtsi"
#include <dt-bindings/pinctrl/pins-imxrt1020.h>
#include "imxrt1020-pinfunc.h"
/ {
model = "NXP IMXRT1020-evk board";

0
include/dt-bindings/pinctrl/pins-imxrt1020.h → arch/arm/dts/imxrt1020-pinfunc.h
View File

5
arch/arm/dts/imxrt1020.dtsi
View File

@ -67,6 +67,11 @@
fsl,mux_mask = <0x7>;
};
anatop: anatop@400d8000 {
compatible = "fsl,imxrt-anatop";
reg = <0x400d8000 0x4000>;
};
clks: ccm@400fc000 {
compatible = "fsl,imxrt1020-ccm";
reg = <0x400fc000 0x4000>;

4
arch/arm/dts/imxrt1050-evk-u-boot.dtsi
View File

@ -22,6 +22,10 @@
u-boot,dm-spl;
};
&anatop {
u-boot,dm-spl;
};
&clks {
u-boot,dm-spl;
};

2
arch/arm/dts/imxrt1050-evk.dts
View File

@ -7,7 +7,7 @@
/dts-v1/;
#include "imxrt1050.dtsi"
#include "imxrt1050-evk-u-boot.dtsi"
#include <dt-bindings/pinctrl/pins-imxrt1050.h>
#include "imxrt1050-pinfunc.h"
/ {
model = "NXP IMXRT1050-evk board";

0
include/dt-bindings/pinctrl/pins-imxrt1050.h → arch/arm/dts/imxrt1050-pinfunc.h
View File

5
arch/arm/dts/imxrt1050.dtsi
View File

@ -59,6 +59,11 @@
fsl,mux_mask = <0x7>;
};
anatop: anatop@400d8000 {
compatible = "fsl,imxrt-anatop";
reg = <0x400d8000 0x4000>;
};
clks: ccm@400fc000 {
compatible = "fsl,imxrt1050-ccm";
reg = <0x400fc000 0x4000>;

40
arch/arm/dts/ls1021a.dtsi
View File

@ -3,6 +3,7 @@
* Freescale ls1021a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include "skeleton.dtsi"
@ -144,6 +145,45 @@
big-endian;
};
crypto: crypto@1700000 {
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <7>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1700000 0x100000>;
ranges = <0x0 0x1700000 0x100000>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
sec_jr0: jr@10000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x10000 0x10000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr1: jr@20000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x20000 0x10000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr2: jr@30000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x30000 0x10000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
};
sec_jr3: jr@40000 {
compatible = "fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x40000 0x10000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
};
};
clockgen: clocking@1ee1000 {
#address-cells = <1>;
#size-cells = <1>;

1
arch/arm/include/asm/arch-imx/cpu.h
View File

@ -47,6 +47,7 @@
#define MXC_CPU_IMX8MP6 0x186 /* dummy ID */
#define MXC_CPU_IMX8MPL 0x187 /* dummy ID */
#define MXC_CPU_IMX8MPD 0x188 /* dummy ID */
#define MXC_CPU_IMX8MPUL 0x189 /* dummy ID */
#define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */
#define MXC_CPU_IMX8QM 0x91 /* dummy ID */
#define MXC_CPU_IMX8QXP 0x92 /* dummy ID */

5
arch/arm/include/asm/arch-imx8/imx-regs.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#ifndef __ASM_ARCH_IMX8_REGS_H__
@ -47,4 +47,7 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#endif /* __ASM_ARCH_IMX8_REGS_H__ */

1
arch/arm/include/asm/arch-imx8m/clock.h
View File

@ -256,6 +256,7 @@ u32 imx_get_fecclk(void);
u32 imx_get_uartclk(void);
int clock_init(void);
void init_clk_usdhc(u32 index);
void init_nand_clk(void);
void init_uart_clk(u32 index);
void init_usb_clk(void);
void init_wdog_clk(void);

24
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -58,6 +58,13 @@
#define SRC_DDRC_RCR_ADDR 0x30391000
#define SRC_DDRC2_RCR_ADDR 0x30391004
#define APBH_DMA_ARB_BASE_ADDR 0x33000000
#define APBH_DMA_ARB_END_ADDR 0x33007FFF
#define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
#define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
#define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
#define DDRC_DDR_SS_GPR0 0x3d000000
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
@ -328,6 +335,23 @@ struct src {
u32 ddr2_rcr;
};
#define PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
#define PWMCR_DOZEEN (1 << 24)
#define PWMCR_WAITEN (1 << 23)
#define PWMCR_DBGEN (1 << 22)
#define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define PWMCR_CLKSRC_IPG (1 << 16)
#define PWMCR_EN (1 << 0)
struct pwm_regs {
u32 cr;
u32 sr;
u32 ir;
u32 sar;
u32 pr;
u32 cnr;
};
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {

8
arch/arm/include/asm/arch-imx8ulp/cgc.h
View File

@ -146,11 +146,11 @@ struct cgc2_regs {
};
u32 cgc_clk_get_rate(enum cgc_clk clk);
void cgc1_pll3_init(void);
void cgc1_pll2_init(void);
void cgc1_pll3_init(ulong freq);
void cgc1_pll2_init(ulong freq);
void cgc1_soscdiv_init(void);
void cgc1_init_core_clk(void);
void cgc2_pll4_init(void);
void cgc1_init_core_clk(ulong freq);
void cgc2_pll4_init(bool pll4_reset);
void cgc2_ddrclk_config(u32 src, u32 div);
void cgc2_ddrclk_wait_unlock(void);
u32 cgc1_sosc_div(enum cgc_clk clk);

8
arch/arm/include/asm/arch-imx8ulp/clock.h
View File

@ -6,6 +6,11 @@
#ifndef _ASM_ARCH_IMX8ULP_CLOCK_H
#define _ASM_ARCH_IMX8ULP_CLOCK_H
#include <asm/arch/pcc.h>
#include <asm/arch/cgc.h>
#define MHZ(X) ((X) * 1000000UL)
/* Mainly for compatible to imx common code. */
enum mxc_clock {
MXC_ARM_CLK = 0,
@ -36,7 +41,8 @@ void init_clk_usdhc(u32 index);
void init_clk_fspi(int index);
void init_clk_ddr(void);
int set_ddr_clk(u32 phy_freq_mhz);
void clock_init(void);
void clock_init_early(void);
void clock_init_late(void);
void cgc1_enet_stamp_sel(u32 clk_src);
void mxs_set_lcdclk(u32 base_addr, u32 freq_in_khz);
void reset_lcdclk(void);

1
arch/arm/include/asm/arch-imx8ulp/imx-regs.h
View File

@ -14,6 +14,7 @@
#define CMC0_RBASE 0x28025000
#define MU0_B_BASE_ADDR 0x29220000
#define CMC1_BASE_ADDR 0x29240000
#define SIM1_BASE_ADDR 0x29290000

1
arch/arm/include/asm/arch-imx8ulp/pcc.h
View File

@ -52,6 +52,7 @@ enum pcc3_entry {
UPOWER_PCC3_SLOT = 40,
WDOG3_PCC3_SLOT = 42,
WDOG4_PCC3_SLOT = 43,
CAAM_PCC3_SLOT = 46,
XRDC_MGR_PCC3_SLOT = 47,
SEMA42_1_PCC3_SLOT = 48,
ROMCP1_PCC3_SLOT = 49,

5
arch/arm/include/asm/arch-imx8ulp/s400_api.h
View File

@ -19,8 +19,9 @@
#define AHAB_READ_FUSE_REQ_CID 0x97
#define AHAB_RELEASE_RDC_REQ_CID 0xC4
#define AHAB_WRITE_FUSE_REQ_CID 0xD6
#define AHAB_CAAM_RELEASE_CID 0xD7
#define S400_MAX_MSG 8U
#define S400_MAX_MSG 255U
struct imx8ulp_s400_msg {
u8 version;
@ -37,5 +38,7 @@ int ahab_verify_image(u32 img_id, u32 *response);
int ahab_forward_lifecycle(u16 life_cycle, u32 *response);
int ahab_write_fuse(u16 fuse_id, u32 fuse_val, bool lock, u32 *response);
int ahab_read_common_fuse(u16 fuse_id, u32 *fuse_words, u32 fuse_num, u32 *response);
int ahab_release_caam(u32 core_did, u32 *response);
int ahab_dump_buffer(u32 *buffer, u32 buffer_length);
#endif

2
arch/arm/include/asm/arch-imx8ulp/sys_proto.h
View File

@ -18,4 +18,6 @@ int xrdc_config_pdac_openacc(u32 bridge, u32 index);
enum boot_device get_boot_device(void);
void set_lpav_qos(void);
void load_lposc_fuse(void);
bool m33_image_booted(void);
int m33_image_handshake(ulong timeout_ms);
#endif

2
arch/arm/include/asm/arch-imxrt/imx-regs.h
View File

@ -15,8 +15,6 @@
#define GPIO4_BASE_ADDR 0x401C4000
#define GPIO5_BASE_ADDR 0x400C0000
#define ANATOP_BASE_ADDR 0x400d8000
#define MXS_LCDIF_BASE 0x402b8000
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))

6
arch/arm/include/asm/mach-imx/sys_proto.h
View File

@ -73,10 +73,11 @@ struct bd_info;
#define is_imx8mnud() (is_cpu_type(MXC_CPU_IMX8MNUD))
#define is_imx8mnus() (is_cpu_type(MXC_CPU_IMX8MNUS))
#define is_imx8mp() (is_cpu_type(MXC_CPU_IMX8MP) || is_cpu_type(MXC_CPU_IMX8MPD) || \
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6))
is_cpu_type(MXC_CPU_IMX8MPL) || is_cpu_type(MXC_CPU_IMX8MP6) || is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8mpd() (is_cpu_type(MXC_CPU_IMX8MPD))
#define is_imx8mpl() (is_cpu_type(MXC_CPU_IMX8MPL))
#define is_imx8mp6() (is_cpu_type(MXC_CPU_IMX8MP6))
#define is_imx8mpul() (is_cpu_type(MXC_CPU_IMX8MPUL))
#define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
@ -159,6 +160,7 @@ enum boot_dev_type_e {
BT_DEV_TYPE_MMC = 2,
BT_DEV_TYPE_NAND = 3,
BT_DEV_TYPE_FLEXSPINOR = 4,
BT_DEV_TYPE_SPI_NOR = 6,
BT_DEV_TYPE_USB = 0xE,
BT_DEV_TYPE_MEM_DEV = 0xF,
@ -228,6 +230,8 @@ int mxs_reset_block(struct mxs_register_32 *reg);
int mxs_wait_mask_set(struct mxs_register_32 *reg, u32 mask, u32 timeout);
int mxs_wait_mask_clr(struct mxs_register_32 *reg, u32 mask, u32 timeout);
void board_late_mmc_env_init(void);
unsigned long call_imx_sip(unsigned long id, unsigned long reg0,
unsigned long reg1, unsigned long reg2,
unsigned long reg3);

1
arch/arm/mach-imx/cmd_dek.c
View File

@ -9,6 +9,7 @@
#include <command.h>
#include <log.h>
#include <malloc.h>
#include <memalign.h>
#include <asm/byteorder.h>
#include <linux/compiler.h>
#include <fsl_sec.h>

2
arch/arm/mach-imx/cpu.c
View File

@ -106,6 +106,8 @@ const char *get_imx_type(u32 imxtype)
return "8MP Lite[4]"; /* Quad-core Lite version of the imx8mp */
case MXC_CPU_IMX8MP6:
return "8MP[6]"; /* Quad-core version of the imx8mp, NPU fused */
case MXC_CPU_IMX8MPUL:
return "8MP UltraLite"; /* Quad-core UltraLite version of the imx8mp */
case MXC_CPU_IMX8MN:
return "8MNano Quad"; /* Quad-core version */
case MXC_CPU_IMX8MND:

7
arch/arm/mach-imx/imx8/Kconfig
View File

@ -8,6 +8,7 @@ config AHAB_BOOT
config IMX8
bool
select HAS_CAAM
config MU_BASE_SPL
hex "MU base address used in SPL"
@ -72,6 +73,9 @@ config TARGET_IMX8QM_MEK
bool "Support i.MX8QM MEK board"
select BOARD_LATE_INIT
select IMX8QM
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_CONGA_QMX8
bool "Support congatec conga-QMX8 board"
@ -89,6 +93,9 @@ config TARGET_IMX8QXP_MEK
bool "Support i.MX8QXP MEK board"
select BOARD_LATE_INIT
select IMX8QXP
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
endchoice

18
arch/arm/mach-imx/imx8/cpu.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
* Copyright 2018, 2021 NXP
*/
#include <common.h>
@ -91,6 +91,22 @@ static int imx8_init_mu(void *ctx, struct event *event)
}
EVENT_SPY(EVT_DM_POST_INIT, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
#endif
int print_bootinfo(void)
{
enum boot_device bt_dev = get_boot_device();

44
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -39,6 +39,9 @@ config TARGET_IMX8MQ_EVK
select BINMAN
select IMX8MQ
select IMX8M_LPDDR4
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_IMX8MQ_PHANBELL
bool "imx8mq_phanbell"
@ -46,12 +49,22 @@ config TARGET_IMX8MQ_PHANBELL
select IMX8MQ
select IMX8M_LPDDR4
config TARGET_IMX8MM_DATA_MODUL_EDM_SBC
bool "Data Modul eDM SBC i.MX8M Mini"
select BINMAN
select IMX8MM
select IMX8M_LPDDR4
select SUPPORT_SPL
config TARGET_IMX8MM_EVK
bool "imx8mm LPDDR4 EVK board"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_IMX8MM_ICORE_MX8MM
bool "Engicam i.Core MX8M Mini SOM"
@ -71,6 +84,13 @@ config TARGET_IMX8MM_ICORE_MX8MM
* i.Core MX8M Mini needs to mount on top of this Carrier board
for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
config TARGET_IMX8MM_MX8MENLO
bool "Support i.MX8M Mini MX8Menlo board based on Toradex Verdin SoM"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_VENICE
bool "Support Gateworks Venice iMX8M Mini module"
select BINMAN
@ -85,12 +105,28 @@ config TARGET_KONTRON_MX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_BSH_SMM_S2
bool "imx8mn-bsh-smm-s2"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_LPDDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
@ -98,6 +134,8 @@ config TARGET_IMX8MN_DDR4_EVK
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
select FSL_CAAM
select SPL_CRYPTO if SPL
config TARGET_IMX8MN_VENICE
bool "Support Gateworks Venice iMX8M Nano module"
@ -112,6 +150,9 @@ config TARGET_IMX8MP_EVK
select IMX8MP
select SUPPORT_SPL
select IMX8M_LPDDR4
select FSL_CAAM
select ARCH_MISC_INIT
select SPL_CRYPTO if SPL
config TARGET_PICO_IMX8MQ
bool "Support Technexion Pico iMX8MQ"
@ -208,7 +249,9 @@ endchoice
source "board/advantech/imx8mp_rsb3720a1/Kconfig"
source "board/beacon/imx8mm/Kconfig"
source "board/beacon/imx8mn/Kconfig"
source "board/bsh/imx8mn_smm_s2/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/data_modul/imx8mm_edm_sbc/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"
source "board/freescale/imx8mm_evk/Kconfig"
@ -218,6 +261,7 @@ source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/pitx_imx8m/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/menlo/mx8menlo/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"

1
arch/arm/mach-imx/imx8m/clock_imx8mm.c
View File

@ -48,6 +48,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
#ifdef CONFIG_SPL_BUILD
static struct imx_int_pll_rate_table imx8mm_fracpll_tbl[] = {
PLL_1443X_RATE(1000000000U, 250, 3, 1, 0),
PLL_1443X_RATE(933000000U, 311, 4, 1, 0),
PLL_1443X_RATE(800000000U, 300, 9, 0, 0),
PLL_1443X_RATE(750000000U, 250, 8, 0, 0),
PLL_1443X_RATE(650000000U, 325, 3, 2, 0),

359
arch/arm/mach-imx/imx8m/soc.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2017-2019 NXP
* Copyright 2017-2019, 2021 NXP
*
* Peng Fan <peng.fan@nxp.com>
*/
@ -21,6 +21,7 @@
#include <asm/ptrace.h>
#include <asm/armv8/mmu.h>
#include <dm/uclass.h>
#include <dm/device.h>
#include <efi_loader.h>
#include <env.h>
#include <env_internal.h>
@ -28,7 +29,6 @@
#include <fdt_support.h>
#include <fsl_wdog.h>
#include <imx_sip.h>
#include <linux/arm-smccc.h>
#include <linux/bitops.h>
DECLARE_GLOBAL_DATA_PTR;
@ -72,7 +72,7 @@ void enable_tzc380(void)
* According to TRM, TZASC_ID_SWAP_BYPASS should be set in
* order to avoid AXI Bus errors when GPU is in use
*/
if (is_imx8mm() || is_imx8mn() || is_imx8mp())
if (is_imx8mq() || is_imx8mm() || is_imx8mn() || is_imx8mp())
setbits_le32(&gpr->gpr[10], GPR_TZASC_ID_SWAP_BYPASS);
/*
@ -188,32 +188,29 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void)
void enable_caches(void)
{
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
if (rom_pointer[1]) {
/*
* TEE are loaded, So the ddr bank structures
* have been modified update mmu table accordingly
*/
int i = 0;
/*
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch
* If OPTEE does not run, still update the MMU table according to dram banks structure
* to set correct dram size from board_phys_sdram_size
*/
int i = 0;
/*
* please make sure that entry initial value matches
* imx8m_mem_map for DRAM1
*/
int entry = imx8m_find_dram_entry_in_mem_map();
u64 attrs = imx8m_mem_map[entry].attrs;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx8m_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
i++; entry++;
}
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8m_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8m_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx8m_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx8m_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8m_mem_map[entry].phys, imx8m_mem_map[entry].size);
i++; entry++;
}
icache_enable();
@ -226,12 +223,15 @@ __weak int board_phys_sdram_size(phys_size_t *size)
return -EINVAL;
*size = PHYS_SDRAM_SIZE;
#ifdef PHYS_SDRAM_2_SIZE
*size += PHYS_SDRAM_2_SIZE;
#endif
return 0;
}
int dram_init(void)
{
unsigned int entry = imx8m_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
@ -245,13 +245,6 @@ int dram_init(void)
else
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
imx8m_mem_map[entry].size = sdram_size;
#ifdef PHYS_SDRAM_2_SIZE
gd->ram_size += PHYS_SDRAM_2_SIZE;
#endif
return 0;
}
@ -260,18 +253,28 @@ int dram_init_banksize(void)
int bank = 0;
int ret;
phys_size_t sdram_size;
phys_size_t sdram_b1_size, sdram_b2_size;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0xc0000000) {
sdram_b1_size = 0xc0000000;
sdram_b2_size = sdram_size - 0xc0000000;
} else {
sdram_b1_size = sdram_size;
sdram_b2_size = 0;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_b1_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
@ -279,35 +282,51 @@ int dram_init_banksize(void)
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_size - gd->bd->bi_dram[bank].start;
sdram_b1_size - gd->bd->bi_dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_size;
gd->bd->bi_dram[bank].size = sdram_b1_size;
}
#ifdef PHYS_SDRAM_2_SIZE
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
if (sdram_b2_size) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough for SDRAM_2\n");
return -1;
}
gd->bd->bi_dram[bank].start = 0x100000000UL;
gd->bd->bi_dram[bank].size = sdram_b2_size;
}
gd->bd->bi_dram[bank].start = PHYS_SDRAM_2;
gd->bd->bi_dram[bank].size = PHYS_SDRAM_2_SIZE;
#endif
return 0;
}
phys_size_t get_effective_memsize(void)
{
/* return the first bank as effective memory */
if (rom_pointer[1])
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
int ret;
phys_size_t sdram_size;
phys_size_t sdram_b1_size;
ret = board_phys_sdram_size(&sdram_size);
if (!ret) {
/* Bank 1 can't cross over 4GB space */
if (sdram_size > 0xc0000000) {
sdram_b1_size = 0xc0000000;
} else {
sdram_b1_size = sdram_size;
}
#ifdef PHYS_SDRAM_2_SIZE
return gd->ram_size - PHYS_SDRAM_2_SIZE;
#else
return gd->ram_size;
#endif
if (rom_pointer[1]) {
/* We will relocate u-boot to Top of dram1. Tee position has two cases:
* 1. At the top of dram1, Then return the size removed optee size.
* 2. In the middle of dram1, return the size of dram1.
*/
if ((rom_pointer[0] + rom_pointer[1]) == (PHYS_SDRAM + sdram_b1_size))
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
}
return sdram_b1_size;
} else {
return PHYS_SDRAM_SIZE;
}
}
ulong board_get_usable_ram_top(ulong total_size)
@ -408,13 +427,27 @@ static u32 get_cpu_variant_type(u32 type)
/* npu disabled*/
if ((value & 0x8) == 0x8)
flag |= (1 << 1);
flag |= BIT(1);
/* isp disabled */
if ((value & 0x3) == 0x3)
flag |= (1 << 2);
flag |= BIT(2);
/* gpu disabled */
if ((value & 0xc0) == 0xc0)
flag |= BIT(3);
/* lvds disabled */
if ((value & 0x180000) == 0x180000)
flag |= BIT(4);
/* mipi dsi disabled */
if ((value & 0x60000) == 0x60000)
flag |= BIT(5);
switch (flag) {
case 0x3f:
return MXC_CPU_IMX8MPUL;
case 7:
return MXC_CPU_IMX8MPL;
case 2:
@ -517,6 +550,11 @@ EVENT_SPY(EVT_DM_POST_INIT, imx8m_check_clock);
int arch_cpu_init(void)
{
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
icache_enable();
#endif
/*
* ROM might disable clock for SCTR,
* enable the clock before timer_init.
@ -599,6 +637,9 @@ enum boot_device get_boot_device(void)
case BT_DEV_TYPE_FLEXSPINOR:
boot_dev = QSPI_BOOT;
break;
case BT_DEV_TYPE_SPI_NOR:
boot_dev = SPI_NOR_BOOT;
break;
case BT_DEV_TYPE_USB:
boot_dev = USB_BOOT;
break;
@ -893,6 +934,90 @@ static int low_drive_gpu_freq(void *blob)
}
#endif
static bool check_remote_endpoint(void *blob, const char *ep1, const char *ep2)
{
int lookup_node;
int nodeoff;
nodeoff = fdt_path_offset(blob, ep1);
if (nodeoff) {
lookup_node = fdtdec_lookup_phandle(blob, nodeoff, "remote-endpoint");
nodeoff = fdt_path_offset(blob, ep2);
if (nodeoff > 0 && nodeoff == lookup_node)
return true;
}
return false;
}
int disable_dsi_lcdif_nodes(void *blob)
{
int ret;
static const char * const dsi_path_8mp[] = {
"/soc@0/bus@32c00000/mipi_dsi@32e60000"
};
static const char * const lcdif_path_8mp[] = {
"/soc@0/bus@32c00000/lcd-controller@32e80000"
};
static const char * const lcdif_ep_path_8mp[] = {
"/soc@0/bus@32c00000/lcd-controller@32e80000/port@0/endpoint"
};
static const char * const dsi_ep_path_8mp[] = {
"/soc@0/bus@32c00000/mipi_dsi@32e60000/port@0/endpoint"
};
ret = disable_fdt_nodes(blob, dsi_path_8mp, ARRAY_SIZE(dsi_path_8mp));
if (ret)
return ret;
if (check_remote_endpoint(blob, dsi_ep_path_8mp[0], lcdif_ep_path_8mp[0])) {
/* Disable lcdif node */
return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
}
return 0;
}
int disable_lvds_lcdif_nodes(void *blob)
{
int ret, i;
static const char * const ldb_path_8mp[] = {
"/soc@0/bus@32c00000/ldb@32ec005c",
"/soc@0/bus@32c00000/phy@32ec0128"
};
static const char * const lcdif_path_8mp[] = {
"/soc@0/bus@32c00000/lcd-controller@32e90000"
};
static const char * const lcdif_ep_path_8mp[] = {
"/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@0",
"/soc@0/bus@32c00000/lcd-controller@32e90000/port@0/endpoint@1"
};
static const char * const ldb_ep_path_8mp[] = {
"/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@0/port@0/endpoint",
"/soc@0/bus@32c00000/ldb@32ec005c/lvds-channel@1/port@0/endpoint"
};
ret = disable_fdt_nodes(blob, ldb_path_8mp, ARRAY_SIZE(ldb_path_8mp));
if (ret)
return ret;
for (i = 0; i < ARRAY_SIZE(ldb_ep_path_8mp); i++) {
if (check_remote_endpoint(blob, ldb_ep_path_8mp[i], lcdif_ep_path_8mp[i])) {
/* Disable lcdif node */
return disable_fdt_nodes(blob, lcdif_path_8mp, ARRAY_SIZE(lcdif_path_8mp));
}
}
return 0;
}
int disable_gpu_nodes(void *blob)
{
static const char * const nodes_path_8mn[] = {
@ -900,7 +1025,15 @@ int disable_gpu_nodes(void *blob)
"/soc@/gpu@38000000"
};
return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
static const char * const nodes_path_8mp[] = {
"/gpu3d@38000000",
"/gpu2d@38008000"
};
if (is_imx8mp())
return disable_fdt_nodes(blob, nodes_path_8mp, ARRAY_SIZE(nodes_path_8mp));
else
return disable_fdt_nodes(blob, nodes_path_8mn, ARRAY_SIZE(nodes_path_8mn));
}
int disable_npu_nodes(void *blob)
@ -1042,6 +1175,37 @@ static int disable_cpu_nodes(void *blob, u32 disabled_cores)
return 0;
}
static int cleanup_nodes_for_efi(void *blob)
{
static const char * const path[][2] = {
{ "/soc@0/bus@32c00000/usb@32e40000", "extcon" },
{ "/soc@0/bus@32c00000/usb@32e50000", "extcon" },
{ "/soc@0/bus@30800000/ethernet@30be0000", "phy-reset-gpios" },
{ "/soc@0/bus@30800000/ethernet@30bf0000", "phy-reset-gpios" }
};
int nodeoff, i, rc;
for (i = 0; i < ARRAY_SIZE(path); i++) {
nodeoff = fdt_path_offset(blob, path[i][0]);
if (nodeoff < 0)
continue; /* Not found, skip it */
debug("Found %s node\n", path[i][0]);
rc = fdt_delprop(blob, nodeoff, path[i][1]);
if (rc == -FDT_ERR_NOTFOUND)
continue;
if (rc) {
printf("Unable to update property %s:%s, err=%s\n",
path[i][0], path[i][1], fdt_strerror(rc));
return rc;
}
printf("Remove %s:%s\n", path[i][0], path[i][1]);
}
return 0;
}
int ft_system_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_IMX8MQ
@ -1156,26 +1320,72 @@ usb_modify_speed:
disable_cpu_nodes(blob, 3);
#elif defined(CONFIG_IMX8MP)
if (is_imx8mpl())
if (is_imx8mpul()) {
/* Disable GPU */
disable_gpu_nodes(blob);
/* Disable DSI */
disable_dsi_lcdif_nodes(blob);
/* Disable LVDS */
disable_lvds_lcdif_nodes(blob);
}
if (is_imx8mpul() || is_imx8mpl())
disable_vpu_nodes(blob);
if (is_imx8mpl() || is_imx8mp6())
if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
disable_npu_nodes(blob);
if (is_imx8mpl())
if (is_imx8mpul() || is_imx8mpl())
disable_isp_nodes(blob);
if (is_imx8mpl() || is_imx8mp6())
if (is_imx8mpul() || is_imx8mpl() || is_imx8mp6())
disable_dsp_nodes(blob);
if (is_imx8mpd())
disable_cpu_nodes(blob, 2);
#endif
cleanup_nodes_for_efi(blob);
return 0;
}
#endif
#ifdef CONFIG_OF_BOARD_FIXUP
#ifndef CONFIG_SPL_BUILD
int board_fix_fdt(void *fdt)
{
if (is_imx8mpul()) {
int i = 0;
int nodeoff, ret;
const char *status = "disabled";
static const char * const dsi_nodes[] = {
"/soc@0/bus@32c00000/mipi_dsi@32e60000",
"/soc@0/bus@32c00000/lcd-controller@32e80000",
"/dsi-host"
};
for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
if (nodeoff > 0) {
set_status:
ret = fdt_setprop(fdt, nodeoff, "status", status,
strlen(status) + 1);
if (ret == -FDT_ERR_NOSPACE) {
ret = fdt_increase_size(fdt, 512);
if (!ret)
goto set_status;
}
}
}
}
return 0;
}
#endif
#endif
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
@ -1193,26 +1403,16 @@ void reset_cpu(void)
#endif
#if defined(CONFIG_ARCH_MISC_INIT)
static void acquire_buildinfo(void)
{
u64 atf_commit = 0;
struct arm_smccc_res res;
/* Get ARM Trusted Firmware commit id */
arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
0, 0, 0, 0, 0, 0, &res);
atf_commit = res.a0;
if (atf_commit == 0xffffffff) {
debug("ATF does not support build info\n");
atf_commit = 0x30; /* Display 0, 0 ascii is 0x30 */
}
printf("\n BuildInfo:\n - ATF %s\n\n", (char *)&atf_commit);
}
int arch_misc_init(void)
{
acquire_buildinfo();
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
@ -1337,6 +1537,7 @@ enum env_location env_get_location(enum env_operation op, int prio)
switch (dev) {
case QSPI_BOOT:
case SPI_NOR_BOOT:
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
return ENVL_SPI_FLASH;
return ENVL_NOWHERE;

7
arch/arm/mach-imx/imx8ulp/Kconfig
View File

@ -2,11 +2,16 @@ if ARCH_IMX8ULP
config IMX8ULP
bool
select ARMV8_SPL_EXCEPTION_VECTORS
config SYS_SOC
default "imx8ulp"
config IMX8ULP_LD_MODE
bool
config IMX8ULP_ND_MODE
bool "i.MX8ULP Low Driver Mode"
choice
prompt "i.MX8ULP board select"
optional

106
arch/arm/mach-imx/imx8ulp/cgc.c
View File

@ -9,9 +9,11 @@
#include <errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/cgc.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <linux/delay.h>
#include <hang.h>
DECLARE_GLOBAL_DATA_PTR;
@ -29,7 +31,7 @@ void cgc1_soscdiv_init(void)
clrbits_le32(&cgc1_regs->frodiv, BIT(7));
}
void cgc1_pll2_init(void)
void cgc1_pll2_init(ulong freq)
{
u32 reg;
@ -44,8 +46,8 @@ void cgc1_pll2_init(void)
while ((readl(&cgc1_regs->pll2csr) & BIT(24)))
;
/* Select SOSC as source, freq = 31 * 24 =744mhz */
reg = 31 << 16;
/* Select SOSC as source */
reg = (freq / MHZ(24)) << 16;
writel(reg, &cgc1_regs->pll2cfg);
/* Enable PLL2 */
@ -74,7 +76,7 @@ static void cgc1_set_a35_clk(u32 clk_src, u32 div_core)
;
}
void cgc1_init_core_clk(void)
void cgc1_init_core_clk(ulong freq)
{
u32 reg = readl(&cgc1_regs->ca35clk);
@ -82,8 +84,7 @@ void cgc1_init_core_clk(void)
if (((reg >> 28) & 0x3) == 0x1)
cgc1_set_a35_clk(0, 1);
/* Set pll2 to 750Mhz for 1V */
cgc1_pll2_init();
cgc1_pll2_init(freq);
/* Set A35 clock to pll2 */
cgc1_set_a35_clk(1, 1);
@ -94,7 +95,7 @@ void cgc1_enet_stamp_sel(u32 clk_src)
writel((clk_src & 0x7) << 24, &cgc1_regs->enetstamp);
}
void cgc1_pll3_init(void)
void cgc1_pll3_init(ulong freq)
{
/* Gate off VCO */
setbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
@ -115,11 +116,15 @@ void cgc1_pll3_init(void)
/* Select SOSC as source */
clrbits_le32(&cgc1_regs->pll3cfg, BIT(0));
//setbits_le32(&cgc1_regs->pll3cfg, 22 << 16);
writel(22 << 16, &cgc1_regs->pll3cfg);
writel(578, &cgc1_regs->pll3num);
writel(1000, &cgc1_regs->pll3denom);
switch (freq) {
case 540672000:
writel(0x16 << 16, &cgc1_regs->pll3cfg);
writel(0x16e3600, &cgc1_regs->pll3denom);
writel(0xc15c00, &cgc1_regs->pll3num);
break;
default:
hang();
}
/* Enable PLL3 */
setbits_le32(&cgc1_regs->pll3csr, BIT(0));
@ -130,23 +135,30 @@ void cgc1_pll3_init(void)
/* Gate on VCO */
clrbits_le32(&cgc1_regs->pll3div_vco, BIT(7));
/*
* PFD0: 380MHz/396/396/328
*/
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 0);
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 3 << 21); /* 195M */
} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
setbits_le32(&cgc1_regs->pll3pfdcfg, 21 << 0);
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(26, 21), 1 << 21); /* 231M */
} else {
setbits_le32(&cgc1_regs->pll3pfdcfg, 30 << 0); /* 324M */
}
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(7));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(6)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 8);
setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 8);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 8);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(15));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(14)))
;
clrbits_le32(&cgc1_regs->pll3pfdcfg, 0x3F << 16);
setbits_le32(&cgc1_regs->pll3pfdcfg, 24 << 16);
setbits_le32(&cgc1_regs->pll3pfdcfg, 25 << 16);
clrbits_le32(&cgc1_regs->pll3pfdcfg, BIT(23));
while (!(readl(&cgc1_regs->pll3pfdcfg) & BIT(22)))
;
@ -166,10 +178,25 @@ void cgc1_pll3_init(void)
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(15));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(23));
clrbits_le32(&cgc1_regs->pll3div_pfd1, BIT(31));
if (!IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) && !IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
/* nicclk select pll3 pfd0 */
clrsetbits_le32(&cgc1_regs->nicclk, GENMASK(29, 28), BIT(28));
while (!(readl(&cgc1_regs->nicclk) & BIT(27)))
;
}
}
void cgc2_pll4_init(void)
void cgc2_pll4_init(bool pll4_reset)
{
/* Check the NICLPAV first to ensure not from PLL4 PFD1 clock */
if ((readl(&cgc2_regs->niclpavclk) & GENMASK(29, 28)) == BIT(28)) {
/* switch to FRO 192 first */
clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28));
while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
;
}
/* Disable PFD DIV and clear DIV */
writel(0x80808080, &cgc2_regs->pll4div_pfd0);
writel(0x80808080, &cgc2_regs->pll4div_pfd1);
@ -177,22 +204,35 @@ void cgc2_pll4_init(void)
/* Gate off and clear PFD */
writel(0x80808080, &cgc2_regs->pll4pfdcfg);
/* Disable PLL4 */
writel(0x0, &cgc2_regs->pll4csr);
if (pll4_reset) {
/* Disable PLL4 */
writel(0x0, &cgc2_regs->pll4csr);
/* Configure PLL4 to 528Mhz and clock source from SOSC */
writel(22 << 16, &cgc2_regs->pll4cfg);
writel(0x1, &cgc2_regs->pll4csr);
/* Configure PLL4 to 528Mhz and clock source from SOSC */
writel(22 << 16, &cgc2_regs->pll4cfg);
writel(0x1, &cgc2_regs->pll4csr);
/* wait for PLL4 output valid */
while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
;
/* wait for PLL4 output valid */
while (!(readl(&cgc2_regs->pll4csr) & BIT(24)))
;
}
/* Enable all 4 PFDs */
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0);
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16);
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24);
setbits_le32(&cgc2_regs->pll4pfdcfg, 18 << 0); /* 528 */
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE)) {
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
/* 99Mhz for NIC_LPAV */
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 3 << 21);
} else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 8);
/* 198Mhz for NIC_LPAV */
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21), 1 << 21);
} else {
setbits_le32(&cgc2_regs->pll4pfdcfg, 30 << 8); /* 316.8Mhz for NIC_LPAV */
clrbits_le32(&cgc2_regs->niclpavclk, GENMASK(26, 21));
}
setbits_le32(&cgc2_regs->pll4pfdcfg, 12 << 16); /* 792 */
setbits_le32(&cgc2_regs->pll4pfdcfg, 24 << 24); /* 396 */
clrbits_le32(&cgc2_regs->pll4pfdcfg, BIT(7) | BIT(15) | BIT(23) | BIT(31));
@ -203,6 +243,10 @@ void cgc2_pll4_init(void)
/* Enable PFD DIV */
clrbits_le32(&cgc2_regs->pll4div_pfd0, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrbits_le32(&cgc2_regs->pll4div_pfd1, BIT(7) | BIT(15) | BIT(23) | BIT(31));
clrsetbits_le32(&cgc2_regs->niclpavclk, GENMASK(29, 28), BIT(28));
while (!(readl(&cgc2_regs->niclpavclk) & BIT(27)))
;
}
void cgc2_pll4_pfd_config(enum cgc_clk pllpfd, u32 pfd)

97
arch/arm/mach-imx/imx8ulp/clock.c
View File

@ -101,8 +101,8 @@ void init_clk_ddr(void)
writel(0xc0000000, PCC5_LPDDR4_ADDR);
/* enable pll4 and ddrclk*/
cgc2_pll4_init();
cgc2_ddrclk_config(1, 1);
cgc2_pll4_init(true);
cgc2_ddrclk_config(4, 1);
/* enable ddr pcc */
writel(0xd0000000, PCC5_LPDDR4_ADDR);
@ -153,30 +153,69 @@ int set_ddr_clk(u32 phy_freq_mhz)
return 0;
}
void clock_init(void)
void clock_init_early(void)
{
cgc1_soscdiv_init();
cgc1_init_core_clk();
init_clk_lpuart();
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
/* Enable upower mu1 clk */
pcc_clock_enable(3, UPOWER_PCC3_SLOT, true);
}
/* This will be invoked after pmic voltage setting */
void clock_init_late(void)
{
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE))
cgc1_init_core_clk(MHZ(500));
else if (IS_ENABLED(CONFIG_IMX8ULP_ND_MODE))
cgc1_init_core_clk(MHZ(750));
else
cgc1_init_core_clk(MHZ(960));
/*
* Audio use this frequency in kernel dts,
* however nic use pll3 pfd0, we have to
* make the freqency same as kernel to make nic
* not being disabled
*/
cgc1_pll3_init(540672000);
if (IS_ENABLED(CONFIG_IMX8ULP_LD_MODE) || IS_ENABLED(CONFIG_IMX8ULP_ND_MODE)) {
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV2);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
} else {
pcc_clock_enable(4, SDHC0_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC0_PCC4_SLOT, PLL3_PFD1_DIV2);
pcc_clock_enable(4, SDHC0_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC0_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC1_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC1_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC1_PCC4_SLOT, false);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, false);
pcc_clock_sel(4, SDHC2_PCC4_SLOT, PLL3_PFD2_DIV1);
pcc_clock_enable(4, SDHC2_PCC4_SLOT, true);
pcc_reset_peripheral(4, SDHC2_PCC4_SLOT, false);
}
/* enable MU0_MUB clock before access the register of MU0_MUB */
pcc_clock_enable(3, MU0_B_PCC3_SLOT, true);
/*
* Enable clock division
@ -237,6 +276,26 @@ u32 imx_get_i2cclk(u32 i2c_num)
}
#endif
#if IS_ENABLED(CONFIG_SYS_I2C_IMX_I3C)
int enable_i3c_clk(unsigned char enable, u32 i3c_num)
{
if (enable) {
pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
pcc_clock_sel(3, I3C2_PCC3_SLOT, SOSC_DIV2);
pcc_clock_enable(3, I3C2_PCC3_SLOT, true);
pcc_reset_peripheral(3, I3C2_PCC3_SLOT, false);
} else {
pcc_clock_enable(3, I3C2_PCC3_SLOT, false);
}
return 0;
}
u32 imx_get_i3cclk(u32 i3c_num)
{
return pcc_clock_get_rate(3, I3C2_PCC3_SLOT);
}
#endif
void enable_usboh3_clk(unsigned char enable)
{
if (enable) {

1
arch/arm/mach-imx/imx8ulp/pcc.c
View File

@ -135,6 +135,7 @@ static struct pcc_entry pcc3_arrays[] = {
{PCC3_RBASE, UPOWER_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, WDOG3_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
{PCC3_RBASE, WDOG4_PCC3_SLOT, CLKSRC_PER_BUS, PCC_HAS_DIV, PCC_HAS_RST_B},
{PCC3_RBASE, CAAM_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_HAS_RST_B},
{PCC3_RBASE, XRDC_MGR_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, SEMA42_1_PCC3_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, ROMCP1_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},

197
arch/arm/mach-imx/imx8ulp/soc.c
View File

@ -26,6 +26,9 @@
#include <dm/uclass-internal.h>
#include <fuse.h>
#include <thermal.h>
#include <linux/iopoll.h>
#include <env.h>
#include <env_internal.h>
DECLARE_GLOBAL_DATA_PTR;
@ -137,6 +140,38 @@ enum bt_mode get_boot_mode(void)
return LOW_POWER_BOOT;
}
bool m33_image_booted(void)
{
u32 gp6;
/* DGO_GP6 */
gp6 = readl(SIM_SEC_BASE_ADDR + 0x28);
if (gp6 & BIT(5))
return true;
return false;
}
int m33_image_handshake(ulong timeout_ms)
{
u32 fsr;
int ret;
ulong timeout_us = timeout_ms * 1000;
/* Notify m33 that it's ready to do init srtm(enable mu receive interrupt and so on) */
setbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0)); /* set FCR F0 flag of MU0_MUB */
/*
* Wait m33 to set FCR F0 flag of MU0_MUA
* Clear FCR F0 flag of MU0_MUB after m33 has set FCR F0 flag of MU0_MUA
*/
ret = readl_poll_sleep_timeout(MU0_B_BASE_ADDR + 0x104, fsr, fsr & BIT(0), 10, timeout_us);
if (!ret)
clrbits_le32(MU0_B_BASE_ADDR + 0x100, BIT(0));
return ret;
}
#define CMC_SRS_TAMPER BIT(31)
#define CMC_SRS_SECURITY BIT(30)
#define CMC_SRS_TZWDG BIT(29)
@ -380,6 +415,17 @@ static struct mm_region imx8ulp_arm64_mem_map[] = {
struct mm_region *mem_map = imx8ulp_arm64_mem_map;
static unsigned int imx8ulp_find_dram_entry_in_mem_map(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++)
if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE)
return i;
hang(); /* Entry not found, this must never happen. */
}
/* simplify the page table size to enhance boot speed */
#define MAX_PTE_ENTRIES 512
#define MAX_MEM_MAP_REGIONS 16
@ -411,19 +457,106 @@ u64 get_page_table_size(void)
void enable_caches(void)
{
/* TODO: add TEE memmap region */
/* If OPTEE runs, remove OPTEE memory from MMU table to avoid speculative prefetch */
if (rom_pointer[1]) {
/*
* TEE are loaded, So the ddr bank structures
* have been modified update mmu table accordingly
*/
int i = 0;
int entry = imx8ulp_find_dram_entry_in_mem_map();
u64 attrs = imx8ulp_arm64_mem_map[entry].attrs;
while (i < CONFIG_NR_DRAM_BANKS &&
entry < ARRAY_SIZE(imx8ulp_arm64_mem_map)) {
if (gd->bd->bi_dram[i].start == 0)
break;
imx8ulp_arm64_mem_map[entry].phys = gd->bd->bi_dram[i].start;
imx8ulp_arm64_mem_map[entry].virt = gd->bd->bi_dram[i].start;
imx8ulp_arm64_mem_map[entry].size = gd->bd->bi_dram[i].size;
imx8ulp_arm64_mem_map[entry].attrs = attrs;
debug("Added memory mapping (%d): %llx %llx\n", entry,
imx8ulp_arm64_mem_map[entry].phys, imx8ulp_arm64_mem_map[entry].size);
i++; entry++;
}
}
icache_enable();
dcache_enable();
}
__weak int board_phys_sdram_size(phys_size_t *size)
{
if (!size)
return -EINVAL;
*size = PHYS_SDRAM_SIZE;
return 0;
}
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
unsigned int entry = imx8ulp_find_dram_entry_in_mem_map();
phys_size_t sdram_size;
int ret;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
/* rom_pointer[1] contains the size of TEE occupies */
if (rom_pointer[1])
gd->ram_size = sdram_size - rom_pointer[1];
else
gd->ram_size = sdram_size;
/* also update the SDRAM size in the mem_map used externally */
imx8ulp_arm64_mem_map[entry].size = sdram_size;
return 0;
}
int dram_init_banksize(void)
{
int bank = 0;
int ret;
phys_size_t sdram_size;
ret = board_phys_sdram_size(&sdram_size);
if (ret)
return ret;
gd->bd->bi_dram[bank].start = PHYS_SDRAM;
if (rom_pointer[1]) {
phys_addr_t optee_start = (phys_addr_t)rom_pointer[0];
phys_size_t optee_size = (size_t)rom_pointer[1];
gd->bd->bi_dram[bank].size = optee_start - gd->bd->bi_dram[bank].start;
if ((optee_start + optee_size) < (PHYS_SDRAM + sdram_size)) {
if (++bank >= CONFIG_NR_DRAM_BANKS) {
puts("CONFIG_NR_DRAM_BANKS is not enough\n");
return -1;
}
gd->bd->bi_dram[bank].start = optee_start + optee_size;
gd->bd->bi_dram[bank].size = PHYS_SDRAM +
sdram_size - gd->bd->bi_dram[bank].start;
}
} else {
gd->bd->bi_dram[bank].size = sdram_size;
}
return 0;
}
phys_size_t get_effective_memsize(void)
{
/* return the first bank as effective memory */
if (rom_pointer[1])
return ((phys_addr_t)rom_pointer[0] - PHYS_SDRAM);
return gd->ram_size;
}
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
void get_board_serial(struct tag_serialnr *serialnr)
{
@ -491,10 +624,10 @@ static int trdc_set_access(void)
return 0;
}
void lpav_configure(void)
void lpav_configure(bool lpav_to_m33)
{
/* LPAV to APD */
setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7));
if (!lpav_to_m33)
setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); /* LPAV to APD */
/* PXP/GPU 2D/3D/DCNANO/MIPI_DSI/EPDC/HIFI4 to APD */
setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, 0x7F);
@ -538,6 +671,19 @@ int arch_cpu_init(void)
int ret;
bool rdc_en = true; /* Default assume DBD_EN is set */
/* Enable System Reset Interrupt using WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x8C, BIT(13));
/* Clear AD_PERIPH Power switch domain out of reset interrupt flag */
setbits_le32(CMC1_BASE_ADDR + 0x70, BIT(4));
if (readl(CMC1_BASE_ADDR + 0x90) & BIT(13)) {
/* Clear System Reset Interrupt Flag Register of WDOG_AD */
setbits_le32(CMC1_BASE_ADDR + 0x90, BIT(13));
/* Reset WDOG to clear reset request */
pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, true);
pcc_reset_peripheral(3, WDOG3_PCC3_SLOT, false);
}
/* Disable wdog */
init_wdog();
@ -551,8 +697,9 @@ int arch_cpu_init(void)
release_rdc(RDC_TRDC);
trdc_set_access();
lpav_configure();
lpav_configure(false);
} else {
lpav_configure(true);
}
/* Release xrdc, then allow A35 to write SRAM2 */
@ -561,7 +708,7 @@ int arch_cpu_init(void)
xrdc_mrc_region_set_access(2, CONFIG_SPL_TEXT_BASE, 0xE00);
clock_init();
clock_init_early();
} else {
/* reconfigure core0 reset vector to ROM */
set_core0_reset_vector(0x1000);
@ -642,3 +789,37 @@ u32 spl_arch_boot_image_offset(u32 image_offset, u32 rom_bt_dev)
return image_offset;
}
enum env_location env_get_location(enum env_operation op, int prio)
{
enum boot_device dev = get_boot_device();
enum env_location env_loc = ENVL_UNKNOWN;
if (prio)
return env_loc;
switch (dev) {
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
case QSPI_BOOT:
env_loc = ENVL_SPI_FLASH;
break;
#endif
#ifdef CONFIG_ENV_IS_IN_MMC
case SD1_BOOT:
case SD2_BOOT:
case SD3_BOOT:
case MMC1_BOOT:
case MMC2_BOOT:
case MMC3_BOOT:
env_loc = ENVL_MMC;
break;
#endif
default:
#if defined(CONFIG_ENV_IS_NOWHERE)
env_loc = ENVL_NOWHERE;
#endif
break;
}
return env_loc;
}

10
arch/arm/mach-imx/mx6/Kconfig
View File

@ -354,6 +354,8 @@ config TARGET_MX6SABREAUTO
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
select FSL_CAAM
select ARCH_MISC_INIT
config TARGET_MX6SABRESD
bool "mx6sabresd"
@ -364,6 +366,8 @@ config TARGET_MX6SABRESD
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
select FSL_CAAM
select ARCH_MISC_INIT
config TARGET_MX6SLEVK
bool "mx6slevk"
@ -386,6 +390,8 @@ config TARGET_MX6SXSABRESD
select DM
select DM_THERMAL
select SUPPORT_SPL
select FSL_CAAM
select ARCH_MISC_INIT
config TARGET_MX6SXSABREAUTO
bool "mx6sxsabreauto"
@ -404,6 +410,8 @@ config TARGET_MX6UL_9X9_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
select FSL_CAAM
select ARCH_MISC_INIT
config TARGET_MX6UL_14X14_EVK
bool "mx6ul_14x14_evk"
@ -413,6 +421,8 @@ config TARGET_MX6UL_14X14_EVK
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
select FSL_CAAM
select ARCH_MISC_INIT
config TARGET_MX6UL_ENGICAM
bool "Support Engicam GEAM6UL/Is.IoT"

13
arch/arm/mach-imx/mx6/ddr.c
View File

@ -108,7 +108,7 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
{
struct mmdc_p_regs *mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
struct mmdc_p_regs *mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
u32 esdmisc_val, zq_val;
u32 esdmisc_val, zq_val, mdmisc_val;
u32 errors = 0;
u32 ldectrl[4] = {0};
u32 ddr_mr1 = 0x4;
@ -131,6 +131,9 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
/* disable Adopt power down timer */
setbits_le32(&mmdc0->mapsr, 0x1);
/* Save old RALAT and WALAT values */
mdmisc_val = readl(&mmdc0->mdmisc);
debug("Starting write leveling calibration.\n");
/*
@ -217,6 +220,9 @@ int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo)
writel(esdmisc_val, &mmdc0->mdref);
writel(zq_val, &mmdc0->mpzqhwctrl);
/* restore WALAT/RALAT */
writel(mdmisc_val, &mmdc0->mdmisc);
debug("\tMMDC_MPWLDECTRL0 after write level cal: 0x%08x\n",
readl(&mmdc0->mpwldectrl0));
debug("\tMMDC_MPWLDECTRL1 after write level cal: 0x%08x\n",
@ -1520,6 +1526,11 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
/* Step 8: Write Mode Registers to Init DDR3 devices */
mdelay(1); /* Wait before issuing the first MRS command.
* Minimum wait time is (tXPR + 500us),
* with max tXPR value 360ns, and 500us wait required after
* RESET_n is de-asserted.
*/
for (cs = 0; cs < sysinfo->ncs; cs++) {
/* MR2 */
val = (sysinfo->rtt_wr & 3) << 9 | (ddr3_cfg->SRT & 1) << 7 |

13
arch/arm/mach-imx/mx6/soc.c
View File

@ -4,6 +4,7 @@
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2009 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -23,7 +24,6 @@
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <dm.h>
#include <fsl_sec.h>
#include <imx_thermal.h>
#include <mmc.h>
@ -738,9 +738,14 @@ static void setup_serial_number(void)
int arch_misc_init(void)
{
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
setup_serial_number();
return 0;
}

1
arch/arm/mach-imx/mx7/Kconfig
View File

@ -68,6 +68,7 @@ config TARGET_MX7DSABRESD
select DM_THERMAL
select MX7D
imply CMD_DM
select FSL_CAAM
config TARGET_PICO_IMX7D
bool "pico-imx7d"

12
arch/arm/mach-imx/mx7/soc.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -20,7 +21,6 @@
#include <dm.h>
#include <env.h>
#include <imx_thermal.h>
#include <fsl_sec.h>
#include <asm/setup.h>
#include <linux/delay.h>
@ -356,9 +356,13 @@ int arch_misc_init(void)
env_set("serial#", serial_string);
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#endif
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}

2
arch/arm/mach-imx/mx7ulp/Kconfig
View File

@ -40,6 +40,8 @@ config TARGET_MX7ULP_EVK
bool "Support mx7ulp EVK board"
select MX7ULP
select SYS_ARCH_TIMER
select FSL_CAAM
select ARCH_MISC_INIT
endchoice

18
arch/arm/mach-imx/mx7ulp/soc.c
View File

@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2021 NXP
*/
#include <common.h>
@ -16,6 +17,7 @@
#include <asm/mach-imx/sys_proto.h>
#include <asm/setup.h>
#include <linux/bitops.h>
#include <dm.h>
#define PMC0_BASE_ADDR 0x410a1000
#define PMC0_CTRL 0x28
@ -82,6 +84,22 @@ int arch_cpu_init(void)
return 0;
}
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
#endif
#ifdef CONFIG_BOARD_POSTCLK_INIT
int board_postclk_init(void)
{

4
arch/arm/mach-imx/parse-container.c
View File

@ -142,12 +142,12 @@ static int read_auth_container(struct spl_image_info *spl_image,
return -EIO;
if (container->tag != 0x87 && container->version != 0x0) {
printf("Wrong container header");
printf("Wrong container header\n");
return -ENOENT;
}
if (!container->num_images) {
printf("Wrong container, no image found");
printf("Wrong container, no image found\n");
return -ENOENT;
}

10
arch/arm/mach-imx/spl_imx_romapi.c
View File

@ -38,14 +38,8 @@ ulong spl_romapi_raw_seekable_read(u32 offset, u32 size, void *buf)
ulong __weak spl_romapi_get_uboot_base(u32 image_offset, u32 rom_bt_dev)
{
u32 offset;
if (((rom_bt_dev >> 16) & 0xff) == BT_DEV_TYPE_FLEXSPINOR)
offset = CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512;
else
offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;
return offset;
return image_offset +
(CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000);
}
static int is_boot_from_stream_device(u32 boot)

20
arch/arm/mach-socfpga/reset_manager_s10.c
View File

@ -80,9 +80,9 @@ void socfpga_bridges_reset(int enable)
~0);
/* Poll until all idleack to 0 */
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK, reg, !reg, 1000,
300000);
read_poll_timeout(readl, reg, !reg, 1000, 300000,
socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK);
} else {
/* set idle request to all bridges */
writel(~0,
@ -93,18 +93,20 @@ void socfpga_bridges_reset(int enable)
writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK, reg,
read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
1000, 300000);
1000, 300000,
socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLEACK);
/* Poll until all idlestatus to 1 */
read_poll_timeout(readl, socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLESTATUS, reg,
read_poll_timeout(readl, reg,
reg == (SYSMGR_NOC_H2F_MSK |
SYSMGR_NOC_LWH2F_MSK),
1000, 300000);
1000, 300000,
socfpga_get_sysmgr_addr() +
SYSMGR_SOC64_NOC_IDLESTATUS);
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,

19
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -56,6 +56,7 @@
#ifdef CONFIG_U_QE
#include <fsl_qe.h>
#endif
#include <dm.h>
#ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
/*
@ -902,8 +903,6 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FSL_CAAM
sec_init();
#if defined(CONFIG_ARCH_C29X)
if ((SVR_SOC_VER(svr) == SVR_C292) ||
(SVR_SOC_VER(svr) == SVR_C293))
@ -942,6 +941,22 @@ int cpu_init_r(void)
return 0;
}
#ifdef CONFIG_ARCH_MISC_INIT
int arch_misc_init(void)
{
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
struct udevice *dev;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
if (ret)
printf("Failed to initialize %s: %d\n", dev->name, ret);
}
return 0;
}
#endif
void arch_preboot_os(void)
{
u32 msr;

1
arch/powerpc/dts/p2041si-post.dtsi
View File

@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"

1
arch/powerpc/dts/p3041si-post.dtsi
View File

@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-sec4.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"

1
arch/powerpc/dts/p4080si-post.dtsi
View File

@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-sec4.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"

1
arch/powerpc/dts/p5040si-post.dtsi
View File

@ -11,6 +11,7 @@
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-sec5.2-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"

74
arch/powerpc/dts/qoriq-sec4.0-0.dtsi Normal file
View File

@ -0,0 +1,74 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* QorIQ Sec/Crypto 4.0 device tree stub [ controller @ offset 0x300000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
crypto: crypto@300000 {
compatible = "fsl,sec-v4.0";
fsl,sec-era = <1>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupts = <93 2 0 0>;
};

83
arch/powerpc/dts/qoriq-sec4.2-0.dtsi Normal file
View File

@ -0,0 +1,83 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* QorIQ Sec/Crypto 4.2 device tree stub [ controller @ offset 0x300000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
*/
crypto: crypto@300000 {
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
fsl,sec-era = <3>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v4.2-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v4.2-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v4.2-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v4.2-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v4.2-rtic",
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v4.2-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v4.2-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v4.2-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v4.2-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v4.2-mon", "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupts = <93 2 0 0>;
};

92
arch/powerpc/dts/qoriq-sec5.2-0.dtsi Normal file
View File

@ -0,0 +1,92 @@
// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
* QorIQ Sec/Crypto 5.2 device tree stub [ controller @ offset 0x300000 ]
*
* Copyright 2011-2012 Freescale Semiconductor Inc.
*/
crypto: crypto@300000 {
compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
fsl,sec-era = <5>;
#address-cells = <1>;
#size-cells = <1>;
reg = <0x300000 0x10000>;
ranges = <0 0x300000 0x10000>;
interrupts = <92 2 0 0>;
sec_jr0: jr@1000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x1000 0x1000>;
interrupts = <88 2 0 0>;
};
sec_jr1: jr@2000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x2000 0x1000>;
interrupts = <89 2 0 0>;
};
sec_jr2: jr@3000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x3000 0x1000>;
interrupts = <90 2 0 0>;
};
sec_jr3: jr@4000 {
compatible = "fsl,sec-v5.2-job-ring",
"fsl,sec-v5.0-job-ring",
"fsl,sec-v4.0-job-ring";
reg = <0x4000 0x1000>;
interrupts = <91 2 0 0>;
};
rtic@6000 {
compatible = "fsl,sec-v5.2-rtic",
"fsl,sec-v5.0-rtic",
"fsl,sec-v4.0-rtic";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x6000 0x100>;
ranges = <0x0 0x6100 0xe00>;
rtic_a: rtic-a@0 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x00 0x20 0x100 0x80>;
};
rtic_b: rtic-b@20 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x20 0x20 0x200 0x80>;
};
rtic_c: rtic-c@40 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x40 0x20 0x300 0x80>;
};
rtic_d: rtic-d@60 {
compatible = "fsl,sec-v5.2-rtic-memory",
"fsl,sec-v5.0-rtic-memory",
"fsl,sec-v4.0-rtic-memory";
reg = <0x60 0x20 0x500 0x80>;
};
};
};
sec_mon: sec_mon@314000 {
compatible = "fsl,sec-v5.2-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
reg = <0x314000 0x1000>;
interrupts = <93 2 0 0>;
};

1
arch/powerpc/dts/t1023si-post.dtsi
View File

@ -14,6 +14,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-sec5.0-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"

1
arch/powerpc/dts/t1042si-post.dtsi
View File

@ -12,6 +12,7 @@
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/include/ "qoriq-sec5.0-0.dtsi"
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-1g-0.dtsi"

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