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Program EPLD to force full duplex mode for PHY.

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EPLD forces modes of PHY operation. By default full duplex is turned off.
This fix turns it on.

Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
This commit is contained in:
Grzegorz Bernacki 2007-10-01 09:51:50 +02:00 committed by Stefan Roese
parent 636538c520
commit 2db6478406
2 changed files with 20 additions and 9 deletions
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17
board/amcc/luan/luan.c
View File

@ -39,8 +39,6 @@ extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
************************************************************************/ ************************************************************************/
int board_early_init_f(void) int board_early_init_f(void)
{ {
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
mtebc( pb0ap, 0x03800000 ); /* set chip selects */ mtebc( pb0ap, 0x03800000 ); /* set chip selects */
mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
mtebc( pb1ap, 0x03800000 ); mtebc( pb1ap, 0x03800000 );
@ -66,8 +64,6 @@ int board_early_init_f(void)
mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */ mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
mtdcr( uic0sr, 0xffffffff ); mtdcr( uic0sr, 0xffffffff );
x->ethuart &= ~EPLD2_RESET_ETH_N; /* put Ethernet+PHY in reset */
return 0; return 0;
} }
@ -79,7 +75,18 @@ int board_early_init_f(void)
int misc_init_r(void) int misc_init_r(void)
{ {
volatile epld_t *x = (epld_t *) CFG_EPLD_BASE; volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
x->ethuart |= EPLD2_RESET_ETH_N; /* take Ethernet+PHY out of reset */
/* set modes of operation */
x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
/* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
/* put Ethernet+PHY in reset */
x->ethuart &= ~EPLD2_RESET_ETH_N;
udelay(10000);
/* take Ethernet+PHY out of reset */
x->ethuart |= EPLD2_RESET_ETH_N;
return 0; return 0;
} }

12
cpu/ppc4xx/4xx_enet.c
View File

@ -138,7 +138,8 @@
#define BI_PHYMODE_MII 7 #define BI_PHYMODE_MII 7
#endif #endif
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || \
defined(CONFIG_440GRX) || defined(CONFIG_440SP)
#define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
#endif #endif
@ -408,7 +409,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
int ethgroup = -1; int ethgroup = -1;
#endif #endif
#endif #endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SPE) || defined(CONFIG_440SP)
unsigned long mfr; unsigned long mfr;
#endif #endif
@ -500,7 +502,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
__asm__ volatile ("eieio"); __asm__ volatile ("eieio");
/* reset emac so we have access to the phy */ /* reset emac so we have access to the phy */
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP)
/* provide clocks for EMAC internal loopback */ /* provide clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr); mfsdr (sdr_mfr, mfr);
mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum); mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
@ -518,7 +521,8 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
if (failsafe <= 0) if (failsafe <= 0)
printf("\nProblem resetting EMAC!\n"); printf("\nProblem resetting EMAC!\n");
#if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
defined(CONFIG_440SP)
/* remove clocks for EMAC internal loopback */ /* remove clocks for EMAC internal loopback */
mfsdr (sdr_mfr, mfr); mfsdr (sdr_mfr, mfr);
mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum); mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);