leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch '2022-09-01-assorted-Kconfig-migrations' into next

Browse Source 
- Assorted Kconfig migrations
This commit is contained in:
Tom Rini 2022-09-02 08:59:15 -04:00
commit 2d7069126d
81 changed files with 106 additions and 138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README
View File

@ -415,8 +415,6 @@ The following options need to be configured:
the defaults discussed just above. the defaults discussed just above.
- Cache Configuration for ARM: - Cache Configuration for ARM:
CONFIG_SYS_L2_PL310 - Enable support for ARM PL310 L2 cache
controller
CONFIG_SYS_PL310_BASE - Physical base address of PL310 CONFIG_SYS_PL310_BASE - Physical base address of PL310
controller register space controller register space

10
arch/arm/Kconfig
View File

@ -488,6 +488,15 @@ config TPL_SYS_THUMB_BUILD
density. For ARM architectures that support Thumb2 this flag will density. For ARM architectures that support Thumb2 this flag will
result in Thumb2 code generated by GCC. result in Thumb2 code generated by GCC.
config SYS_L2_PL310
bool "ARM PL310 L2 cache controller"
help
Enable support for ARM PL310 L2 cache controller in U-Boot
config SPL_SYS_L2_PL310
bool "ARM PL310 L2 cache controller in SPL"
help
Enable support for ARM PL310 L2 cache controller in SPL
config SYS_L2CACHE_OFF config SYS_L2CACHE_OFF
bool "L2cache off" bool "L2cache off"
@ -989,6 +998,7 @@ config ARCH_MX6
select SYS_FSL_HAS_SEC select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_4 select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE select SYS_FSL_SEC_LE
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
imply MXC_GPIO imply MXC_GPIO
imply SYS_THUMB_BUILD imply SYS_THUMB_BUILD
imply SPL_SEPARATE_BSS imply SPL_SEPARATE_BSS

2
arch/arm/lib/Makefile
View File

@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o
obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o
obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
else else
obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o
obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o
@ -46,6 +45,7 @@ else
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
endif endif
obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),) ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),)

1
arch/arm/mach-mvebu/Kconfig
View File

@ -14,6 +14,7 @@ config ARMADA_32BIT
select SPL_SKIP_LOWLEVEL_INIT if SPL select SPL_SKIP_LOWLEVEL_INIT if SPL
select SPL_SIMPLE_BUS if SPL select SPL_SIMPLE_BUS if SPL
select SUPPORT_SPL select SUPPORT_SPL
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
select TRANSLATION_OFFSET select TRANSLATION_OFFSET
select SPL_SYS_NO_VECTOR_TABLE if SPL select SPL_SYS_NO_VECTOR_TABLE if SPL
select ARCH_VERY_EARLY_INIT select ARCH_VERY_EARLY_INIT

2
arch/arm/mach-mvebu/include/mach/config.h
View File

@ -25,8 +25,6 @@
#define MV88F78X60 /* for the DDR training bin_hdr code */ #define MV88F78X60 /* for the DDR training bin_hdr code */
#endif #endif
#define CONFIG_SYS_L2_PL310
#define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE #define MV_UART_CONSOLE_BASE MVEBU_UART0_BASE
/* Needed for SPI NOR booting in SPL */ /* Needed for SPI NOR booting in SPL */

1
arch/arm/mach-omap2/Kconfig
View File

@ -96,6 +96,7 @@ config TI816X
config AM43XX config AM43XX
bool "AM43XX SoC" bool "AM43XX SoC"
select SPECIFY_CONSOLE_INDEX select SPECIFY_CONSOLE_INDEX
select SYS_L2_PL310 if !SYS_L2CACHE_OFF
imply NAND_OMAP_ELM imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC imply NAND_OMAP_GPMC
imply SPL_DM imply SPL_DM

41
board/dhelectronics/dh_imx6/dh_imx6_spl.c
View File

@ -6,6 +6,7 @@
*/ */
#include <common.h> #include <common.h>
#include <cpu_func.h>
#include <init.h> #include <init.h>
#include <asm/arch/clock.h> #include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h> #include <asm/arch/crm_regs.h>
@ -14,11 +15,13 @@
#include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h> #include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h> #include <asm/arch/sys_proto.h>
#include <asm/cache.h>
#include <asm/gpio.h> #include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/system.h>
#include <errno.h> #include <errno.h>
#include <fuse.h> #include <fuse.h>
#include <fsl_esdhc_imx.h> #include <fsl_esdhc_imx.h>
@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void)
} }
} }
void dram_bank_mmu_setup(int bank)
{
int i;
set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +
(SZ_1G >> MMU_SECTION_SHIFT));
i++)
set_section_dcache(i, DCACHE_DEFAULT_OPTION);
}
void board_init_f(ulong dummy) void board_init_f(ulong dummy)
{ {
/* setup AIPS and disable watchdog */ /* setup AIPS and disable watchdog */
@ -636,9 +653,33 @@ void board_init_f(ulong dummy)
/* DDR3 initialization */ /* DDR3 initialization */
dhcom_spl_dram_init(); dhcom_spl_dram_init();
/* Set up early MMU tables at the beginning of DRAM and start d-cache */
gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
gd->arch.tlb_size = PGTABLE_SIZE;
enable_caches();
/* Clear the BSS. */ /* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start); memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */ /* load/boot image from boot device */
board_init_r(NULL, 0); board_init_r(NULL, 0);
} }
void spl_board_prepare_for_boot(void)
{
/*
* Flush and disable dcache. Without it, the following bootstage might fail randomly because
* dirty cache lines may not have been written back to DRAM.
*
* If dcache_disable() would be omitted, the following scenario may occur:
*
* The SPL enables dcache and cachelines get populated with data. Then dcache gets disabled
* in U-Boot proper, but still contains dirty data, i.e. the corresponding DRAM locations
* have not yet been updated. When U-Boot reads these locations, it sees an (incorrect) old
* state of the content.
*
* Furthermore, the DRAM contents have likely been modified by U-Boot while dcache was
* disabled. Thus, U-Boot flushing dcache would corrupt DRAM with stale data.
*/
dcache_disable(); /* implies flush_dcache_all() */
}

21
common/Kconfig
View File

@ -671,6 +671,27 @@ config ID_EEPROM
A number of different systems and vendors enable a vendor-specified A number of different systems and vendors enable a vendor-specified
EEPROM that contains various identifying features. EEPROM that contains various identifying features.
config SYS_EEPROM_BUS_NUM
int "I2C bus number of the system identifier EEPROM"
depends on ID_EEPROM
default 0
choice
prompt "EEPROM starts with 'CCID' or 'NXID'"
depends on ID_EEPROM && (PPC || ARCH_LS1021A || FSL_LAYERSCAPE)
default SYS_I2C_EEPROM_NXID
help
Specify if the Freescale / NXP ID EEPROM starts with 'CCID' or 'NXID'
ASCII literal string.
config SYS_I2C_EEPROM_CCID
bool "EEPROM starts with 'CCID'"
config SYS_I2C_EEPROM_NXID
bool "EEPROM starts with 'NXID'"
endchoice
config PCI_INIT_R config PCI_INIT_R
bool "Enumerate PCI buses during init" bool "Enumerate PCI buses during init"
depends on PCI depends on PCI

1
configs/MPC8548CDS_36BIT_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set # CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/MPC8548CDS_defconfig
View File

@ -20,6 +20,7 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set # CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/MPC8548CDS_legacy_defconfig
View File

@ -21,6 +21,7 @@ CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr" CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
# CONFIG_MISC_INIT_R is not set # CONFIG_MISC_INIT_R is not set
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_I2C_EEPROM_CCID=y
CONFIG_HUSH_PARSER=y CONFIG_HUSH_PARSER=y
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_CMD_IMLS=y CONFIG_CMD_IMLS=y

1
configs/dh_imx6_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SPL_SYS_L2_PL310=y
CONFIG_ARCH_MX6=y CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_SYS_TEXT_BASE=0x17800000
CONFIG_SYS_MALLOC_F_LEN=0x1000 CONFIG_SYS_MALLOC_F_LEN=0x1000

1
configs/ls1021atwr_nor_SECURE_BOOT_defconfig
View File

@ -33,6 +33,7 @@ CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_BOOTM_LEN=0x4000000

1
configs/ls1021atwr_nor_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_BOOTM_LEN=0x4000000

1
configs/ls1021atwr_nor_lpuart_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_BOOTM_LEN=0x4000000

1
configs/ls1021atwr_qspi_defconfig
View File

@ -35,6 +35,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SYS_CBSIZE=256 CONFIG_SYS_CBSIZE=256
CONFIG_SYS_PBSIZE=276 CONFIG_SYS_PBSIZE=276
CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_SYS_BOOTM_LEN=0x4000000

1
configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig
View File

@ -43,6 +43,7 @@ CONFIG_SILENT_CONSOLE=y
CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000 CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/ls1021atwr_sdcard_ifc_defconfig
View File

@ -44,6 +44,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000 CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/ls1021atwr_sdcard_qspi_defconfig
View File

@ -45,6 +45,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_ARCH_MISC_INIT=y CONFIG_ARCH_MISC_INIT=y
CONFIG_MISC_INIT_R=y CONFIG_MISC_INIT_R=y
CONFIG_ID_EEPROM=y CONFIG_ID_EEPROM=y
CONFIG_SYS_EEPROM_BUS_NUM=1
CONFIG_SPL_MAX_SIZE=0x1a000 CONFIG_SPL_MAX_SIZE=0x1a000
CONFIG_SPL_PAD_TO=0x1c000 CONFIG_SPL_PAD_TO=0x1c000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y

1
configs/omap4_panda_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_OMAP2PLUS=y CONFIG_ARCH_OMAP2PLUS=y
CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_DEFAULT_DEVICE_TREE="omap4-panda" CONFIG_DEFAULT_DEVICE_TREE="omap4-panda"

1
configs/omap4_sdp4430_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
# CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMCPY is not set
# CONFIG_SPL_USE_ARCH_MEMSET is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set
CONFIG_ARCH_OMAP2PLUS=y CONFIG_ARCH_OMAP2PLUS=y

1
configs/poleg_evb_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_ARCH_CPU_INIT=y CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_NPCM=y CONFIG_ARCH_NPCM=y
CONFIG_SYS_TEXT_BASE=0x8200 CONFIG_SYS_TEXT_BASE=0x8200
CONFIG_SYS_MALLOC_LEN=0x240000 CONFIG_SYS_MALLOC_LEN=0x240000

1
configs/socfpga_arria10_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_arria5_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_chameleonv3_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x4400 CONFIG_ENV_OFFSET=0x4400

1
configs/socfpga_cyclone5_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_dbm_soc1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de0_nano_soc_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de10_nano_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de10_standard_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_de1_soc_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_is1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_mcvevk_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_secu1_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_SYS_MALLOC_F_LEN=0x800

1
configs/socfpga_sockit_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_socrates_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_SIZE=0x2000

1
configs/socfpga_sr1500_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/socfpga_vining_fpga_defconfig
View File

@ -1,4 +1,5 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_SOCFPGA=y CONFIG_ARCH_SOCFPGA=y
CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_ENV_SIZE=0x4000 CONFIG_ENV_SIZE=0x4000

1
configs/stemmy_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_L2_PL310=y
CONFIG_ARCH_U8500=y CONFIG_ARCH_U8500=y
CONFIG_SUPPORT_PASSING_ATAGS=y CONFIG_SUPPORT_PASSING_ATAGS=y
# CONFIG_SETUP_MEMORY_TAGS is not set # CONFIG_SETUP_MEMORY_TAGS is not set

3
include/configs/MPC8548CDS.h
View File

@ -255,9 +255,6 @@
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_CCID
/* /*
* General PCI * General PCI
* Memory space is mapped 1-1, but I/O space must start from 0. * Memory space is mapped 1-1, but I/O space must start from 0.

4
include/configs/P1010RDB.h
View File

@ -351,10 +351,6 @@ extern unsigned long get_sdram_size(void);
/* I2C EEPROM */ /* I2C EEPROM */
#if defined(CONFIG_TARGET_P1010RDB_PB) #if defined(CONFIG_TARGET_P1010RDB_PB)
#ifdef CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#endif
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */
#endif #endif
/* enable read and write access to EEPROM */ /* enable read and write access to EEPROM */

4
include/configs/P2041RDB.h
View File

@ -67,10 +67,6 @@
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* DDR Setup * DDR Setup
*/ */

4
include/configs/T102xRDB.h
View File

@ -112,10 +112,6 @@
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* DDR Setup * DDR Setup
*/ */

5
include/configs/T104xRDB.h
View File

@ -292,11 +292,6 @@
#if defined(CONFIG_TARGET_T1042RDB_PI) || \ #if defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_TARGET_T1040D4RDB) || \ defined(CONFIG_TARGET_T1040D4RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) defined(CONFIG_TARGET_T1042D4RDB)
/* LDI/DVI Encoder for display */
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
/* /*
* RTC configuration * RTC configuration
*/ */

4
include/configs/T208xQDS.h
View File

@ -82,10 +82,6 @@
#define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* DDR Setup * DDR Setup
*/ */

4
include/configs/T208xRDB.h
View File

@ -77,10 +77,6 @@
#define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR 0xf0000000
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* DDR Setup * DDR Setup
*/ */

1
include/configs/am43xx_evm.h
View File

@ -29,7 +29,6 @@
/* SPL defines. */ /* SPL defines. */
/* Enabling L2 Cache */ /* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
/* /*

1
include/configs/brppt2.h
View File

@ -13,7 +13,6 @@
/* -- i.mx6 specifica -- */ /* -- i.mx6 specifica -- */
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif /* !CONFIG_SYS_L2CACHE_OFF */ #endif /* !CONFIG_SYS_L2CACHE_OFF */

1
include/configs/cm_t43.h
View File

@ -36,7 +36,6 @@
#define CONFIG_POWER_TPS65218 #define CONFIG_POWER_TPS65218
/* Enabling L2 Cache */ /* Enabling L2 Cache */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
/* /*

4
include/configs/corenet_ds.h
View File

@ -62,10 +62,6 @@
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* DDR Setup * DDR Setup
*/ */

4
include/configs/ls1012aqds.h
View File

@ -49,10 +49,6 @@
#define RTC #define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Voltage monitor on channel 2*/ /* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x40 #define I2C_VOL_MONITOR_ADDR 0x40

4
include/configs/ls1021aiot.h
View File

@ -59,10 +59,6 @@
* I2C * I2C
*/ */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* MMC * MMC
*/ */

4
include/configs/ls1021aqds.h
View File

@ -246,10 +246,6 @@
/* GPIO */ /* GPIO */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* I2C bus multiplexer * I2C bus multiplexer
*/ */

4
include/configs/ls1021atsn.h
View File

@ -71,10 +71,6 @@
/* I2C */ /* I2C */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* PCIe */ /* PCIe */
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"

4
include/configs/ls1021atwr.h
View File

@ -161,10 +161,6 @@
/* GPIO */ /* GPIO */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 1
#define CONFIG_PEN_ADDR_BIG_ENDIAN #define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_SMP_PEN_ADDR 0x01ee0200

4
include/configs/ls1028a_common.h
View File

@ -63,10 +63,6 @@
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
#define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH_DEFAULT 0x8
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* DisplayPort */ /* DisplayPort */
#define DP_PWD_EN_DEFAULT_MASK 0x8 #define DP_PWD_EN_DEFAULT_MASK 0x8

4
include/configs/ls1043aqds.h
View File

@ -37,10 +37,6 @@
/* SATA */ /* SATA */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_SATA AHCI_BASE_ADDR #define CONFIG_SYS_SATA AHCI_BASE_ADDR
/* /*

6
include/configs/ls1043ardb.h
View File

@ -184,12 +184,6 @@
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_CPLD_FTIM2
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
/* EEPROM */
#ifndef SPL_NO_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#endif
/* /*
* Environment * Environment
*/ */

2
include/configs/ls1046afrwy.h
View File

@ -59,8 +59,6 @@
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
/* EEPROM */ /* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define I2C_RETIMER_ADDR 0x18 #define I2C_RETIMER_ADDR 0x18
/* I2C bus multiplexer */ /* I2C bus multiplexer */

4
include/configs/ls1046aqds.h
View File

@ -54,10 +54,6 @@
#define CFG_LPUART_EN 0x2 #define CFG_LPUART_EN 0x2
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* /*
* IFC Definitions * IFC Definitions
*/ */

2
include/configs/ls1046ardb.h
View File

@ -98,8 +98,6 @@
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_CPLD_FTIM3
/* EEPROM */ /* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define I2C_RETIMER_ADDR 0x18 #define I2C_RETIMER_ADDR 0x18
/* PMIC */ /* PMIC */

4
include/configs/ls1088aqds.h
View File

@ -287,10 +287,6 @@
#define RTC #define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#ifdef CONFIG_FSL_DSPI #ifdef CONFIG_FSL_DSPI
#if !defined(CONFIG_TFABOOT) && \ #if !defined(CONFIG_TFABOOT) && \
!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)

4
include/configs/ls1088ardb.h
View File

@ -198,10 +198,6 @@
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#ifndef SPL_NO_ENV #ifndef SPL_NO_ENV
/* Initial environment variables */ /* Initial environment variables */
#ifdef CONFIG_TFABOOT #ifdef CONFIG_TFABOOT

4
include/configs/ls2080aqds.h
View File

@ -235,10 +235,6 @@
#define CONFIG_RTC_DS3231 1 #define CONFIG_RTC_DS3231 1
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Initial environment variables */ /* Initial environment variables */
#undef CONFIG_EXTRA_ENV_SETTINGS #undef CONFIG_EXTRA_ENV_SETTINGS
#ifdef CONFIG_NXP_ESBC #ifdef CONFIG_NXP_ESBC

4
include/configs/ls2080ardb.h
View File

@ -222,10 +222,6 @@
#define CONFIG_SYS_I2C_RTC_ADDR 0x68 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
#endif #endif
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define BOOT_TARGET_DEVICES(func) \ #define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \ func(USB, usb, 0) \
func(MMC, mmc, 0) \ func(MMC, mmc, 0) \

4
include/configs/lx2160a_common.h
View File

@ -78,10 +78,6 @@
#define RTC #define RTC
#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Qixis */ /* Qixis */
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66

4
include/configs/lx2160aqds.h
View File

@ -13,10 +13,6 @@
/* MAC/PHY configuration */ /* MAC/PHY configuration */
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Initial environment variables */ /* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \

4
include/configs/lx2160ardb.h
View File

@ -17,10 +17,6 @@
#define I2C_EMC2305_CMD 0x40 #define I2C_EMC2305_CMD 0x40
#define I2C_EMC2305_PWM 0x80 #define I2C_EMC2305_PWM 0x80
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Initial environment variables */ /* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \

4
include/configs/lx2162aqds.h
View File

@ -13,10 +13,6 @@
/* RTC */ /* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 0 #define CONFIG_SYS_RTC_BUS_NUM 0
/* EEPROM */
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
/* Initial environment variables */ /* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \ #define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \ EXTRA_ENV_SETTINGS \

1
include/configs/mx6_common.h
View File

@ -12,7 +12,6 @@
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */ #define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#else #else
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE L2_PL310_BASE #define CONFIG_SYS_PL310_BASE L2_PL310_BASE
#endif #endif

1
include/configs/odroid.h
View File

@ -14,7 +14,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/poleg.h
View File

@ -7,7 +7,6 @@
#define __CONFIG_POLEG_H #define __CONFIG_POLEG_H
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/ #define CONFIG_SYS_PL310_BASE 0xF03FC000 /* L2 - Cache Regs Base (4k Space)*/
#endif #endif

2
include/configs/sifive-unmatched.h
View File

@ -51,6 +51,4 @@
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
BOOTENV BOOTENV
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#endif /* __SIFIVE_UNMATCHED_H */ #endif /* __SIFIVE_UNMATCHED_H */

1
include/configs/socfpga_common.h
View File

@ -48,7 +48,6 @@
/* /*
* Cache * Cache
*/ */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
/* /*

1
include/configs/stemmy.h
View File

@ -15,7 +15,6 @@
*/ */
/* FIXME: This should be loaded from device tree... */ /* FIXME: This should be loaded from device tree... */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0xa0412000 #define CONFIG_SYS_PL310_BASE 0xa0412000
/* Linux does not boot if FDT / initrd is loaded to end of RAM */ /* Linux does not boot if FDT / initrd is loaded to end of RAM */

1
include/configs/ti_omap4_common.h
View File

@ -12,7 +12,6 @@
#define __CONFIG_TI_OMAP4_COMMON_H #define __CONFIG_TI_OMAP4_COMMON_H
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310 1
#define CONFIG_SYS_PL310_BASE 0x48242000 #define CONFIG_SYS_PL310_BASE 0x48242000
#endif #endif

4
include/configs/tqma6.h
View File

@ -37,10 +37,6 @@
/* I2C Configs */ /* I2C Configs */
#define CONFIG_I2C_MULTI_BUS #define CONFIG_I2C_MULTI_BUS
/* I2C EEPROM (M24C64) */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS 5 /* 32 Bytes */
#define CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS 20
#if !defined(CONFIG_DM_PMIC) #if !defined(CONFIG_DM_PMIC)
#define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100
#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08

1
include/configs/trats.h
View File

@ -12,7 +12,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/trats2.h
View File

@ -13,7 +13,6 @@
#include <configs/exynos4-common.h> #include <configs/exynos4-common.h>
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE 0x10502000 #define CONFIG_SYS_PL310_BASE 0x10502000
#endif #endif

1
include/configs/zynq-common.h
View File

@ -11,7 +11,6 @@
/* Cache options */ /* Cache options */
#ifndef CONFIG_SYS_L2CACHE_OFF #ifndef CONFIG_SYS_L2CACHE_OFF
# define CONFIG_SYS_L2_PL310
# define CONFIG_SYS_PL310_BASE 0xf8f02000 # define CONFIG_SYS_PL310_BASE 0xf8f02000
#endif #endif

9
scripts/config_whitelist.txt
View File

@ -622,7 +622,6 @@ CONFIG_SYS_DPAA_PME
CONFIG_SYS_DPAA_RMAN CONFIG_SYS_DPAA_RMAN
CONFIG_SYS_DRAM_TEST CONFIG_SYS_DRAM_TEST
CONFIG_SYS_DV_NOR_BOOT_CFG CONFIG_SYS_DV_NOR_BOOT_CFG
CONFIG_SYS_EEPROM_BUS_NUM
CONFIG_SYS_EEPROM_WREN CONFIG_SYS_EEPROM_WREN
CONFIG_SYS_ENV_SECT_SIZE CONFIG_SYS_ENV_SECT_SIZE
CONFIG_SYS_ETHOC_BASE CONFIG_SYS_ETHOC_BASE
@ -791,18 +790,11 @@ CONFIG_SYS_GPIO_OUT
CONFIG_SYS_GPR1 CONFIG_SYS_GPR1
CONFIG_SYS_HZ_CLOCK CONFIG_SYS_HZ_CLOCK
CONFIG_SYS_I2C_BUSES CONFIG_SYS_I2C_BUSES
CONFIG_SYS_I2C_DVI_ADDR
CONFIG_SYS_I2C_DVI_BUS_NUM
CONFIG_SYS_I2C_EEPROM_CCID
CONFIG_SYS_I2C_EEPROM_NXID
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_BITS
CONFIG_SYS_I2C_EEPROM_PAGE_WRITE_DELAY_MS
CONFIG_SYS_I2C_EXPANDER_ADDR CONFIG_SYS_I2C_EXPANDER_ADDR
CONFIG_SYS_I2C_FPGA_ADDR CONFIG_SYS_I2C_FPGA_ADDR
CONFIG_SYS_I2C_G762_ADDR CONFIG_SYS_I2C_G762_ADDR
CONFIG_SYS_I2C_IFDR_DIV CONFIG_SYS_I2C_IFDR_DIV
CONFIG_SYS_I2C_INIT_BOARD CONFIG_SYS_I2C_INIT_BOARD
CONFIG_SYS_I2C_LDI_ADDR
CONFIG_SYS_I2C_MAX_HOPS CONFIG_SYS_I2C_MAX_HOPS
CONFIG_SYS_I2C_NOPROBES CONFIG_SYS_I2C_NOPROBES
CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR
@ -845,7 +837,6 @@ CONFIG_SYS_JFFS2_FIRST_SECTOR
CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_JFFS2_NUM_BANKS
CONFIG_SYS_KMBEC_FPGA_BASE CONFIG_SYS_KMBEC_FPGA_BASE
CONFIG_SYS_KMBEC_FPGA_SIZE CONFIG_SYS_KMBEC_FPGA_SIZE
CONFIG_SYS_L2_PL310
CONFIG_SYS_L2_SIZE CONFIG_SYS_L2_SIZE
CONFIG_SYS_L3_SIZE CONFIG_SYS_L3_SIZE
CONFIG_SYS_LATCH_ADDR CONFIG_SYS_LATCH_ADDR