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ARM: socfpga: Configure PL310 latencies

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Configure the PL310 tag and data latency registers, which slightly
improves performance and aligns the behavior with Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dalon Westergreen <dwesterg@gmail.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Marek Vasut 2019-02-19 01:11:24 +01:00
parent b275c9aba6
commit 2c0b300bc3
1 changed files with 3 additions and 0 deletions
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3
arch/arm/mach-socfpga/misc.c
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@ -62,6 +62,9 @@ void v7_outer_cache_enable(void)
/* Disable the L2 cache */
clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
writel(0x111, &pl310->pl310_tag_latency_ctrl);
writel(0x121, &pl310->pl310_data_latency_ctrl);
/* enable BRESP, instruction and data prefetch, full line of zeroes */
setbits_le32(&pl310->pl310_aux_ctrl,
L310_AUX_CTRL_DATA_PREFETCH_MASK |