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powerpc: e6500: Lock/unlock L2 cache instead of L1 as init_ram

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MPC85xx has been using locked L1 cache as init_ram. L1 cache is a write
through cache on E6500. L2 cache is enabled to to hold the data. This
patch locks/unlocks L2 cache to ensure no data cast out from L2 cache.

Signed-off-by: York Sun <yorksun@freescale.com>
Reported-by: Jeffery Zhu <Jefferry.Zhu@freescale.com>
This commit is contained in:
York Sun 2015-08-17 13:31:52 -07:00
parent b3142e2cf8
commit 2becdc6f9d
1 changed files with 9 additions and 1 deletions
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10
arch/powerpc/cpu/mpc85xx/start.S
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@ -1116,7 +1116,11 @@ switch_as:
li r0,0
1:
dcbz r0,r3
dcbtls 0,r0,r3
#ifdef CONFIG_E6500 /* Lock/unlock L2 cache instead of L1 */
dcbtls 2, r0, r3
#else
dcbtls 0, r0, r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
@ -1727,7 +1731,11 @@ unlock_ram_in_cache:
slwi r4,r4,(10 - 1 - L1_CACHE_SHIFT)
mtctr r4
1: dcbi r0,r3
#ifdef CONFIG_E6500 /* lock/unlock L2 cache instead of L1 */
dcblc 2, r0, r3
#else
dcblc r0,r3
#endif
addi r3,r3,CONFIG_SYS_CACHELINE_SIZE
bdnz 1b
sync