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x86: tnc: Use DM PCI API in disable_igd()

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Once we get udevice of IGD and SDVO, we can use its udevice to
access PCI configuration space with dm_pci_write_config32().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng
2016-02-01 01:40:54 -08:00
parent 9e36c53dd0
commit 2b94d9fca2
1 changed files with 19 additions and 3 deletions
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22
arch/x86/cpu/queensbay/tnc.c
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@@ -5,9 +5,10 @@
*/ */
#include <common.h> #include <common.h>
#include <dm.h>
#include <pci.h>
#include <asm/io.h> #include <asm/io.h>
#include <asm/irq.h> #include <asm/irq.h>
#include <asm/pci.h>
#include <asm/post.h> #include <asm/post.h>
#include <asm/arch/device.h> #include <asm/arch/device.h>
#include <asm/arch/tnc.h> #include <asm/arch/tnc.h>
@@ -16,6 +17,21 @@
static int __maybe_unused disable_igd(void) static int __maybe_unused disable_igd(void)
{ {
struct udevice *igd, *sdvo;
int ret;
ret = dm_pci_bus_find_bdf(TNC_IGD, &igd);
if (ret)
return ret;
if (!igd)
return 0;
ret = dm_pci_bus_find_bdf(TNC_SDVO, &sdvo);
if (ret)
return ret;
if (!sdvo)
return 0;
/* /*
* According to Atom E6xx datasheet, setting VGA Disable (bit17) * According to Atom E6xx datasheet, setting VGA Disable (bit17)
* of Graphics Controller register (offset 0x50) prevents IGD * of Graphics Controller register (offset 0x50) prevents IGD
@@ -34,8 +50,8 @@ static int __maybe_unused disable_igd(void)
* two devices will be completely disabled (invisible in the PCI * two devices will be completely disabled (invisible in the PCI
* configuration space) unless a system reset is performed. * configuration space) unless a system reset is performed.
*/ */
x86_pci_write_config32(TNC_IGD, IGD_FD, FUNC_DISABLE); dm_pci_write_config32(igd, IGD_FD, FUNC_DISABLE);
x86_pci_write_config32(TNC_SDVO, IGD_FD, FUNC_DISABLE); dm_pci_write_config32(sdvo, IGD_FD, FUNC_DISABLE);
return 0; return 0;
} }