MIPS: avoid .set ISA for cache operations
As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Paul Burton
Daniel Schwierzeck
parent
ab92da9f47
commit
2b8bcc5a2f
@ -22,14 +22,6 @@
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#define INDEX_BASE CKSEG0
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.macro cache_op op addr
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.set push
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.set noreorder
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.set mips3
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cache \op, 0(\addr)
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.set pop
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.endm
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.macro f_fill64 dst, offset, val
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LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
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LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
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@ -60,17 +52,17 @@ LEAF(mips_init_icache)
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/* clear tag to invalidate */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_I t0
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1: cache INDEX_STORE_TAG_I, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* fill once, so data field parity is correct */
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PTR_LI t0, INDEX_BASE
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2: cache_op FILL t0
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2: cache FILL, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 2b
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/* invalidate again - prudent but not strictly neccessary */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_I t0
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1: cache INDEX_STORE_TAG_I, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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@ -85,7 +77,7 @@ LEAF(mips_init_dcache)
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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PTR_ADDU t1, t0, a1
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1: cache_op INDEX_STORE_TAG_D t0
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1: cache INDEX_STORE_TAG_D, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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/* load from each line (in cached space) */
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@ -95,7 +87,7 @@ LEAF(mips_init_dcache)
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bne t0, t1, 2b
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/* clear all tags */
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PTR_LI t0, INDEX_BASE
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1: cache_op INDEX_STORE_TAG_D t0
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1: cache INDEX_STORE_TAG_D, 0(t0)
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PTR_ADDU t0, a2
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bne t0, t1, 1b
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9: jr ra
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@ -12,16 +12,6 @@
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#include <asm/cacheops.h>
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#include <asm/reboot.h>
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips3\n\t \n" \
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" cache %0, %1 \n" \
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" .set pop \n" \
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: \
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: "i" (op), "R" (*(unsigned char *)(addr)))
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void __attribute__((weak)) _machine_restart(void)
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{
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}
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@ -74,20 +64,20 @@ void flush_cache(ulong start_addr, ulong size)
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{
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unsigned long ilsize = icache_line_size();
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unsigned long dlsize = dcache_line_size();
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unsigned long addr, aend;
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const void *addr, *aend;
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/* aend will be miscalculated when size is zero, so we return here */
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if (size == 0)
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return;
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addr = start_addr & ~(dlsize - 1);
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aend = (start_addr + size - 1) & ~(dlsize - 1);
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addr = (const void *)(start_addr & ~(dlsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
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if (ilsize == dlsize) {
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/* flush I-cache & D-cache simultaneously */
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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cache_op(HIT_INVALIDATE_I, addr);
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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@ -97,17 +87,17 @@ void flush_cache(ulong start_addr, ulong size)
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/* flush D-cache */
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += dlsize;
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}
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/* flush I-cache */
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addr = start_addr & ~(ilsize - 1);
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aend = (start_addr + size - 1) & ~(ilsize - 1);
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addr = (const void *)(start_addr & ~(ilsize - 1));
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aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
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while (1) {
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cache_op(HIT_INVALIDATE_I, addr);
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mips_cache(HIT_INVALIDATE_I, addr);
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if (addr == aend)
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break;
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addr += ilsize;
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@ -117,11 +107,11 @@ void flush_cache(ulong start_addr, ulong size)
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void flush_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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while (1) {
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cache_op(HIT_WRITEBACK_INV_D, addr);
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mips_cache(HIT_WRITEBACK_INV_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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@ -131,11 +121,11 @@ void flush_dcache_range(ulong start_addr, ulong stop)
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void invalidate_dcache_range(ulong start_addr, ulong stop)
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{
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unsigned long lsize = dcache_line_size();
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unsigned long addr = start_addr & ~(lsize - 1);
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unsigned long aend = (stop - 1) & ~(lsize - 1);
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const void *addr = (const void *)(start_addr & ~(lsize - 1));
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const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
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while (1) {
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cache_op(HIT_INVALIDATE_D, addr);
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mips_cache(HIT_INVALIDATE_D, addr);
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if (addr == aend)
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break;
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addr += lsize;
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@ -11,6 +11,19 @@
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#ifndef __ASM_CACHEOPS_H
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#define __ASM_CACHEOPS_H
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#ifndef __ASSEMBLY__
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static inline void mips_cache(int op, const volatile void *addr)
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{
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#ifdef __GCC_HAVE_BUILTIN_MIPS_CACHE
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__builtin_mips_cache(op, addr);
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#else
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__asm__ __volatile__("cache %0, %1" : : "i"(op), "R"(addr))
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#endif
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}
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#endif /* !__ASSEMBLY__ */
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/*
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* Cache Operations available on all MIPS processors with R4000-style caches
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*/
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