phy: atheros: move delay config to common function
Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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@ -94,19 +94,32 @@ static int ar8021_config(struct phy_device *phydev)
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return 0;
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}
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static int ar8031_config(struct phy_device *phydev)
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static int ar803x_delay_config(struct phy_device *phydev)
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{
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int ret;
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ar803x_enable_tx_delay(phydev, true);
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ret = ar803x_enable_tx_delay(phydev, true);
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else
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ar803x_enable_tx_delay(phydev, false);
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ret = ar803x_enable_tx_delay(phydev, false);
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if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID ||
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phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
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ar803x_enable_rx_delay(phydev, true);
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ret = ar803x_enable_rx_delay(phydev, true);
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else
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ar803x_enable_rx_delay(phydev, false);
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ret = ar803x_enable_rx_delay(phydev, false);
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return ret;
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}
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static int ar8031_config(struct phy_device *phydev)
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{
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int ret;
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ret = ar803x_delay_config(phydev);
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if (ret < 0)
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return ret;
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phydev->supported = phydev->drv->features;
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@ -118,6 +131,7 @@ static int ar8031_config(struct phy_device *phydev)
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static int ar8035_config(struct phy_device *phydev)
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{
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int ret;
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int regval;
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/* Configure CLK_25M output clock at 125 MHz */
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@ -126,17 +140,9 @@ static int ar8035_config(struct phy_device *phydev)
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regval |= AR8035_CLK_25M_FREQ_125M;
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phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
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ar803x_enable_tx_delay(phydev, true);
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else
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ar803x_enable_tx_delay(phydev, false);
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if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
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(phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
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ar803x_enable_rx_delay(phydev, true);
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else
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ar803x_enable_rx_delay(phydev, false);
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ret = ar803x_delay_config(phydev);
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if (ret < 0)
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return ret;
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phydev->supported = phydev->drv->features;
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