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powerpc/mpc8548: Add workaround for erratum NMG_LBC103

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The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document.
Any local bus transaction may fail during LBIU resynchronization
process when the clock divider [CLKDIV] is changing. Ensure there
is no transaction on the local bus for at least 100 microseconds
after changing clock divider LCRR[CLKDIV].

Refer to the erratum LBIU3 of mpc8548.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2011-10-03 08:37:57 -05:00
parent 5ace2992b5
commit 2b3a1cdd9e
3 changed files with 7 additions and 0 deletions
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3
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -99,6 +99,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG DDR120 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
puts("Work-around for Erratum NMG_LBC103 enabled\n");
#endif
return 0;
}

3
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -463,6 +463,9 @@ skip_l2:
clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
__raw_readl(&lbc->lcrr);
isync();
#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
udelay(100);
#endif
#endif
#ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE

1
arch/powerpc/include/asm/config_mpc85xx.h
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@ -63,6 +63,7 @@
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
#elif defined(CONFIG_MPC8555)
#define CONFIG_MAX_CPUS 1