leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch '2022-12-07-Kconfig-migrations' into next

Browse Source 
- Import another batch of Kconfig migrations and in this case, also
  legacy code removal.
This commit is contained in:
Tom Rini 2022-12-07 18:08:01 -05:00
commit 2b2e9127cc
108 changed files with 35 additions and 9976 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/Kconfig
View File

@ -113,7 +113,6 @@ config RISCV
select DM
select SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
imply DM_ETH
imply DM_EVENT
imply DM_MMC
imply DM_SPI
@ -241,7 +240,6 @@ config X86
imply CMD_SF
imply CMD_SF_TEST
imply CMD_ZBOOT
imply DM_ETH
imply DM_EVENT
imply DM_GPIO
imply DM_KEYBOARD

13
arch/arm/Kconfig
View File

@ -632,7 +632,6 @@ config ARCH_KIRKWOOD
config ARCH_MVEBU
bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
select DM
select DM_ETH
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
@ -736,7 +735,6 @@ config ARCH_EXYNOS
select DM
select DM_GPIO
select DM_I2C
select DM_ETH
select DM_KEYBOARD
select DM_SERIAL
select DM_SPI
@ -767,7 +765,6 @@ config ARCH_HIGHBANK
select CLK
select CLK_CCF
select AHCI
select DM_ETH
select PHYS_64BIT
select TIMER
select SP804_TIMER
@ -1041,7 +1038,6 @@ config ARCH_APPLE
config ARCH_OWL
bool "Actions Semi OWL SoCs"
select DM
select DM_ETH
select DM_SERIAL
select GPIO_EXTRA_HEADER
select OWL_SERIAL
@ -1141,7 +1137,6 @@ config ARCH_SUNXI
select CMD_USB if DISTRO_DEFAULTS && USB_HOST
select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_I2C if I2C
select DM_SPI if SPI
@ -1220,7 +1215,6 @@ config ARCH_VERSAL
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select GICV3
@ -1234,7 +1228,6 @@ config ARCH_VERSAL_NET
select ARM64
select CLK
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
@ -1259,7 +1252,6 @@ config ARCH_ZYNQ
select CPU_V7A
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select DM_SPI
@ -1289,7 +1281,6 @@ config ARCH_ZYNQMP_R5
select CLK
select CPU_V7R
select DM
select DM_ETH if NET
select DM_MMC if MMC
select DM_SERIAL
select OF_CONTROL
@ -1302,7 +1293,6 @@ config ARCH_ZYNQMP
select CLK
select DM
select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
select DM_ETH if NET
imply DM_MAILBOX
select DM_MMC if MMC
select DM_SERIAL
@ -1849,7 +1839,6 @@ config TARGET_SL28
select DM_I2C
select DM_MMC
select DM_SPI_FLASH
select DM_ETH
select DM_MDIO
select PCI
select DM_RNG
@ -1886,7 +1875,6 @@ config ARCH_UNIPHIER
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -2072,7 +2060,6 @@ config TARGET_POMELO
select SCSI
select DM_SCSI
select DM_SERIAL
select DM_ETH if NET
imply CMD_PCI
help
Support for pomelo platform.

5
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -36,11 +36,6 @@
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CFG_SYS_TSEC1_OFFSET 0x01d10000
#define CFG_SYS_MDIO1_OFFSET 0x01d24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#define SCTR_BASE_ADDR (CONFIG_SYS_IMMR + 0x01b00000)

4
arch/arm/mach-at91/Kconfig
View File

@ -85,7 +85,6 @@ config TARGET_GURNARD
select AT91_WANTS_COMMON_PHY
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_SERIAL
select DM_SPI
@ -253,7 +252,6 @@ config TARGET_CORVUS
select AT91SAM9M10G45
select AT91_WANTS_COMMON_PHY
select DM
select DM_ETH
select DM_GPIO
select DM_SERIAL
select SUPPORT_SPL
@ -271,7 +269,6 @@ config TARGET_TAURUS
select AT91SAM9G20
select AT91_WANTS_COMMON_PHY
select DM
select DM_ETH
select DM_GPIO
select DM_SERIAL
select DM_SPI
@ -284,7 +281,6 @@ config TARGET_SMARTWEB
select AT91SAM9260
select AT91_WANTS_COMMON_PHY
select DM
select DM_ETH
select DM_GPIO
select DM_SERIAL
select SUPPORT_SPL

1
arch/arm/mach-imx/mx5/Kconfig
View File

@ -22,7 +22,6 @@ config TARGET_KP_IMX53
bool "Support K+P imx53 board"
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_PMIC

16
arch/arm/mach-imx/mx6/Kconfig
View File

@ -174,7 +174,6 @@ config TARGET_DART_6UL
bool "Variscite imx6ULL dart(DART-SOM-6ULL)"
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -197,7 +196,6 @@ config TARGET_DISPLAY5
bool "LWN DISPLAY5 board"
depends on MX6Q
select DM
select DM_ETH
select DM_I2C
select DM_MMC
select DM_SPI
@ -245,7 +243,6 @@ config TARGET_KONTRON_MX6UL
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
select DM_ETH
select DM_GPIO
select DM_MMC
select PCI
@ -261,7 +258,6 @@ config TARGET_MCCMON6
select SUPPORT_SPL
select DM
select DM_GPIO
select DM_ETH
select DM_SERIAL
select DM_I2C
select DM_SPI
@ -280,7 +276,6 @@ config TARGET_MX6LOGICPD
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -301,7 +296,6 @@ config TARGET_MX6DL_MAMOJ
bool "Support BTicino Mamoj"
depends on MX6QDL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -334,7 +328,6 @@ config TARGET_MX6Q_ENGICAM
depends on MX6QDL
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -355,7 +348,6 @@ config TARGET_MX6Q_ACC
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -447,7 +439,6 @@ config TARGET_MX6UL_ENGICAM
depends on MX6UL
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -484,7 +475,6 @@ config TARGET_MYS_6ULX
bool "MYiR MYS-6ULX"
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -504,7 +494,6 @@ config TARGET_NPI_IMX6ULL
bool "Seeed NPI-IMX6ULL"
depends on MX6ULL
select DM
select DM_ETH
select DM_MMC
select DM_GPIO
select DM_SERIAL
@ -552,7 +541,6 @@ config TARGET_PCL063
bool "PHYTEC PCL063 (phyCORE-i.MX6UL)"
depends on MX6UL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -564,7 +552,6 @@ config TARGET_PCL063_ULL
bool "PHYTEC PCL063 (phyCORE-i.MX6ULL)"
depends on MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
@ -577,7 +564,6 @@ config TARGET_SOMLABS_VISIONSOM_6ULL
depends on MX6ULL
select BOARD_LATE_INIT
select DM
select DM_ETH
select DM_GPIO
select DM_MMC
select DM_SERIAL
@ -597,7 +583,6 @@ config TARGET_KP_IMX6Q_TPC
select SPL_DM if SPL
select DM_THERMAL
select DM_MMC
select DM_ETH
select DM_REGULATOR
select SPL_DM_REGULATOR if SPL
select DM_SERIAL
@ -661,7 +646,6 @@ config TARGET_BRPPT2
select OF_CONTROL
select SPL_OF_LIBFDT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC

1
arch/arm/mach-omap2/am33xx/Kconfig
View File

@ -230,7 +230,6 @@ config TARGET_AM43XX_EVM
bool "Support am43xx_evm"
select BOARD_LATE_INIT
select TI_I2C_BOARD_DETECT
imply DM_ETH
imply DM_I2C
imply DM_SPI
imply DM_SPI_FLASH

2
arch/arm/mach-snapdragon/Kconfig
View File

@ -55,7 +55,6 @@ config TARGET_DRAGONBOARD845C
- 64GiB UFS drive
select MISC_INIT_R
select SDM845
select DM_ETH if NET
config TARGET_STARQLTECHN
bool "Samsung S9 SM-G9600(starqltechn)"
@ -67,7 +66,6 @@ config TARGET_STARQLTECHN
- 64GiB UFS drive
select MISC_INIT_R
select SDM845
select DM_ETH if NET
config TARGET_QCS404EVB
bool "Qualcomm Technologies, Inc. QCS404 EVB"

1
arch/arm/mach-tegra/Kconfig
View File

@ -44,7 +44,6 @@ config TEGRA_COMMON
select BOARD_EARLY_INIT_F
select CLK
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_KEYBOARD

4
arch/mips/Kconfig
View File

@ -19,7 +19,6 @@ config TARGET_MALTA
select DM
select DM_SERIAL
select PCI
select DM_ETH
select DYNAMIC_IO_PORT_BASE
select MIPS_CM
select MIPS_INSERT_BOOT_CONFIG
@ -71,7 +70,6 @@ config ARCH_MTMIPS
imply CMD_DM
select DISPLAY_CPUINFO
select DM
imply DM_ETH
imply DM_GPIO
select DM_RESET
select DM_SERIAL
@ -104,7 +102,6 @@ config ARCH_OCTEON
select DISPLAY_CPUINFO
select DMA_ADDR_T_64BIT
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_SERIAL
@ -153,7 +150,6 @@ config TARGET_XILFPGA
bool "Support Imagination Xilfpga"
select HAS_FIXED_TIMER_FREQUENCY
select DM
select DM_ETH
select DM_GPIO
select DM_SERIAL
select SYS_CACHE_SHIFT_4

17
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -24,18 +24,9 @@
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
/* P1011 is single core version of P1020 */
#elif defined(CONFIG_ARCH_P1011)
#define CONFIG_TSECV2
#elif defined(CONFIG_ARCH_P1020)
#define CONFIG_TSECV2
#elif defined(CONFIG_ARCH_P1021)
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@ -47,13 +38,8 @@
#define CFG_SYS_BMAN_NUM_PORTALS 3
#define CFG_SYS_FM_MURAM_SIZE 0x10000
/* P1024 is lower end variant of P1020 */
#elif defined(CONFIG_ARCH_P1024)
#define CONFIG_TSECV2
/* P1025 is lower end variant of P1021 */
#elif defined(CONFIG_ARCH_P1025)
#define CONFIG_TSECV2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
@ -108,12 +94,10 @@
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_BSC9132)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
#elif defined(CONFIG_ARCH_T4240)
@ -221,7 +205,6 @@
#elif defined(CONFIG_ARCH_C29X)
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000

5
arch/powerpc/include/asm/immap_83xx.h
View File

@ -873,9 +873,4 @@ struct ccsr_gpio {
#define CFG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
#define CFG_SYS_TSEC1_OFFSET 0x24000
#define CFG_SYS_MDIO1_OFFSET 0x24000
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#endif /* __IMMAP_83xx__ */

8
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2541,13 +2541,6 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000
#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100
#ifdef CONFIG_TSECV2
#define CFG_SYS_TSEC1_OFFSET 0xB0000
#elif defined(CONFIG_TSECV2_1)
#define CFG_SYS_TSEC1_OFFSET 0x10000
#else
#define CFG_SYS_TSEC1_OFFSET 0x24000
#endif
#define CFG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
@ -2673,7 +2666,6 @@ struct ccsr_pman {
#define CFG_SYS_SEC_MON_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_SEC_MON_OFFSET)
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MDIO1_OFFSET)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2

1
board/armltd/vexpress64/Kconfig
View File

@ -14,7 +14,6 @@ config VEXPRESS64_BASE_MODEL
select SEMIHOSTING
select VIRTIO_BLK if VIRTIO_MMIO
select VIRTIO_NET if VIRTIO_MMIO
select DM_ETH if VIRTIO_NET
select LINUX_KERNEL_IMAGE_HEADER
select POSITION_INDEPENDENT

73
board/freescale/common/pixis.c
View File

@ -281,79 +281,6 @@ U_BOOT_CMD(
""
);
#ifdef CONFIG_PIXIS_SGMII_CMD
/* Enable or disable SGMII mode for a TSEC
*/
static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
int which_tsec = -1;
unsigned char mask;
unsigned char switch_mask;
if ((argc > 2) && (strcmp(argv[1], "all") != 0))
which_tsec = simple_strtoul(argv[1], NULL, 0);
switch (which_tsec) {
#ifdef CONFIG_TSEC1
case 1:
mask = PIXIS_VSPEED2_TSEC1SER;
switch_mask = PIXIS_VCFGEN1_TSEC1SER;
break;
#endif
#ifdef CONFIG_TSEC2
case 2:
mask = PIXIS_VSPEED2_TSEC2SER;
switch_mask = PIXIS_VCFGEN1_TSEC2SER;
break;
#endif
#ifdef CONFIG_TSEC3
case 3:
mask = PIXIS_VSPEED2_TSEC3SER;
switch_mask = PIXIS_VCFGEN1_TSEC3SER;
break;
#endif
#ifdef CONFIG_TSEC4
case 4:
mask = PIXIS_VSPEED2_TSEC4SER;
switch_mask = PIXIS_VCFGEN1_TSEC4SER;
break;
#endif
default:
mask = PIXIS_VSPEED2_MASK;
switch_mask = PIXIS_VCFGEN1_MASK;
break;
}
/* Toggle whether the switches or FPGA control the settings */
if (!strcmp(argv[argc - 1], "switch"))
clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
else
setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
/* If it's not the switches, enable or disable SGMII, as specified */
if (!strcmp(argv[argc - 1], "on"))
clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
else if (!strcmp(argv[argc - 1], "off"))
setbits_8(pixis_base + PIXIS_VSPEED2, mask);
return 0;
}
U_BOOT_CMD(
pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
"pixis_set_sgmii"
" - Enable or disable SGMII mode for a given TSEC \n",
"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
" TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
" on - enables SGMII\n"
" off - disables SGMII\n"
" switch - use switch settings"
);
#endif
/*
* This function takes the non-integral cpu:mpx pll ratio
* and converts it to an integer that can be used to assign

82
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -168,85 +168,3 @@ void lbc_sdram_init(void)
#endif /* enable SDRAM init */
}
#ifndef CONFIG_DM_ETH
static void configure_rgmii(void)
{
unsigned short temp;
/* Change the resistors for the PHY */
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 18);
miiphy_read(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, temp);
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 29, 3);
miiphy_write(DEFAULT_MII_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}
return;
}
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
#ifdef CONFIG_TSEC4
/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
if (get_board_version() >= 0x13) {
SET_STD_TSEC_INFO(tsec_info[num], 4);
tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
num++;
}
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
configure_rgmii();
#endif
return pci_eth_init(bis);
}
#endif

43
board/freescale/p1010rdb/p1010rdb.c
View File

@ -478,49 +478,6 @@ int checkboard(void)
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
#ifdef CONFIG_TSEC_ENET
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
struct cpu_type *cpu;
int num = 0;
cpu = gd->arch.cpu;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
num++;
#endif
#ifdef CONFIG_TSEC3
/* P1014 and it's derivatives do not support eTSEC3 */
if (cpu->soc_ver != SVR_P1014) {
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
}
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#endif
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_del_flexcan(void *blob)
{

50
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
View File

@ -364,56 +364,6 @@ int board_early_init_r(void)
return 0;
}
#ifndef CONFIG_DM_ETH
int board_eth_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info mdio_info;
struct tsec_info_struct tsec_info[4];
ccsr_gur_t *gur __attribute__((unused)) =
(void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
int num = 0;
#ifdef CONFIG_TSEC1
SET_STD_TSEC_INFO(tsec_info[num], 1);
num++;
#endif
#ifdef CONFIG_TSEC2
SET_STD_TSEC_INFO(tsec_info[num], 2);
if (is_serdes_configured(SGMII_TSEC2)) {
printf("eTSEC2 is in sgmii mode.\n");
tsec_info[num].flags |= TSEC_SGMII;
}
num++;
#endif
#ifdef CONFIG_TSEC3
SET_STD_TSEC_INFO(tsec_info[num], 3);
num++;
#endif
if (!num) {
printf("No TSECs initialized\n");
return 0;
}
mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
mdio_info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &mdio_info);
tsec_eth_init(bis, tsec_info, num);
#if defined(CONFIG_UEC_ETH)
/* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3);
uec_standard_init(bis);
#endif
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP) || defined(CONFIG_OF_BOARD_FIXUP)
static void fix_max6370_watchdog(void *blob)
{

1
board/keymile/km83xx/Kconfig
View File

@ -6,7 +6,6 @@ config KM_ENABLE_FULL_DM_DTS_SUPPORT
default y
select CMD_DM
select DM
select DM_ETH
select DM_MDIO
select DM_SERIAL
select OF_CONTROL

1
board/tq/tqma6/Kconfig
View File

@ -63,7 +63,6 @@ choice
config MBA6
bool "TQMa6 on MBa6 Starterkit"
select DM_ETH
select USB
select CMD_USB
select USB_STORAGE

3
boot/bootm.c
View File

@ -475,9 +475,6 @@ ulong bootm_disable_interrupts(void)
#ifdef CONFIG_NETCONSOLE
/* Stop the ethernet stack if NetConsole could have left it up */
eth_halt();
# ifndef CONFIG_DM_ETH
eth_unregister(eth_get_dev());
# endif
#endif
#if defined(CONFIG_CMD_USB)

2
cmd/net.c
View File

@ -597,7 +597,6 @@ U_BOOT_CMD(
#endif /* CONFIG_CMD_LINK_LOCAL */
#ifdef CONFIG_DM_ETH
static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
const struct udevice *current = eth_get_dev();
@ -640,7 +639,6 @@ U_BOOT_CMD(
"NET sub-system",
"list - list available devices\n"
);
#endif // CONFIG_DM_ETH
#if defined(CONFIG_CMD_NCSI)
static int do_ncsi(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[])

10
cmd/usb.c
View File

@ -591,16 +591,6 @@ static void do_usb_start(void)
drv_usb_kbd_init();
# endif
#endif /* !CONFIG_DM_USB */
#ifdef CONFIG_USB_HOST_ETHER
# ifdef CONFIG_DM_ETH
# ifndef CONFIG_DM_USB
# error "You must use CONFIG_DM_USB if you want to use CONFIG_USB_HOST_ETHER with CONFIG_DM_ETH"
# endif
# else
/* try to recognize ethernet devices immediately */
usb_ether_curr_dev = usb_host_eth_scan(1);
# endif
#endif
}
#ifdef CONFIG_DM_USB

2
configs/LicheePi_Zero_defconfig
View File

@ -6,4 +6,4 @@ CONFIG_MACH_SUN8I_V3S=y
CONFIG_DRAM_CLK=360
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SYS_MONITOR_LEN=786432
# CONFIG_NETDEVICES is not set
# CONFIG_NET is not set

1
configs/chromebook_samus_tpl_defconfig
View File

@ -39,7 +39,6 @@ CONFIG_SPL_NO_BSS_LIMIT=y
CONFIG_HANDOFF=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NET=y
CONFIG_SPL_PCI=y
CONFIG_SPL_PCH=y
CONFIG_TPL_PCI=y

2
configs/pinecube_defconfig
View File

@ -10,12 +10,12 @@ CONFIG_I2C0_ENABLE=y
# CONFIG_HAS_ARMV7_SECURE_BASE is not set
CONFIG_SYS_MONITOR_LEN=786432
CONFIG_SPL_I2C=y
# CONFIG_NET is not set
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MVTWSI=y
CONFIG_SYS_I2C_SLAVE=0x7f
CONFIG_SYS_I2C_SPEED=400000
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_NETDEVICES is not set
CONFIG_AXP209_POWER=y
CONFIG_AXP_DCDC2_VOLT=1250
CONFIG_AXP_DCDC3_VOLT=3300

2
configs/topic_miami_defconfig
View File

@ -46,11 +46,11 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000

2
configs/topic_miamilite_defconfig
View File

@ -46,11 +46,11 @@ CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000

2
configs/topic_miamiplus_defconfig
View File

@ -50,6 +50,7 @@ CONFIG_CMD_CACHE=y
CONFIG_OF_EMBED=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_DFU_RAM=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x600000
@ -62,7 +63,6 @@ CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_SF_DEFAULT_SPEED=108000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
# CONFIG_NETDEVICES is not set
CONFIG_DEBUG_UART_ZYNQ=y
CONFIG_ARM_DCC=y
CONFIG_ZYNQ_SERIAL=y

2
configs/xenguest_arm64_defconfig
View File

@ -35,10 +35,10 @@ CONFIG_CMD_PVBLOCK=y
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_SLEEP is not set
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
# CONFIG_NET is not set
# CONFIG_MMC is not set
# CONFIG_REQUIRE_SERIAL_CONSOLE is not set
CONFIG_DM_SERIAL=y

8
drivers/net/Kconfig
View File

@ -1,7 +1,6 @@
source "drivers/net/phy/Kconfig"
source "drivers/net/pfe_eth/Kconfig"
source "drivers/net/fsl-mc/Kconfig"
source "drivers/net/bnxt/Kconfig"
config ETH
def_bool y
@ -16,6 +15,10 @@ config DM_ETH
This is currently implemented in net/eth-uclass.c
Look in include/net.h for details.
config SPL_DM_ETH
depends on SPL_NET
def_bool y
config DM_MDIO
bool "Enable Driver Model for MDIO devices"
depends on PHYLIB
@ -175,6 +178,8 @@ config BCMGENET
help
This driver supports the BCMGENET Ethernet MAC.
source "drivers/net/bnxt/Kconfig"
config CORTINA_NI_ENET
bool "Cortina-Access Ethernet driver"
depends on CORTINA_PLATFORM
@ -721,7 +726,6 @@ config RENESAS_RAVB
config MPC8XX_FEC
bool "Fast Ethernet Controller on MPC8XX"
depends on MPC8xx
depends on DM_ETH
select MII
select SYS_DISCOVER_PHY
help

1
drivers/net/bnxt/Kconfig
View File

@ -1,6 +1,5 @@
config BNXT_ETH
bool "BNXT PCI support"
depends on DM_ETH
select PCI_INIT_R
help
This driver implements support for bnxt pci controller

156
drivers/net/dc2114x.c
View File

@ -73,13 +73,7 @@
#define POLL_DEMAND 1
#if defined(CONFIG_DM_ETH)
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
#elif defined(CONFIG_E500)
#define phys_to_bus(dev, a) (a)
#else
#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
#endif
#define NUM_RX_DESC PKTBUFSRX
#define NUM_TX_DESC 1 /* Number of TX descriptors */
@ -103,12 +97,7 @@ struct dc2114x_priv {
int tx_new; /* TX descriptor ring pointer */
char rx_ring_size;
char tx_ring_size;
#ifdef CONFIG_DM_ETH
struct udevice *devno;
#else
struct eth_device dev;
pci_dev_t devno;
#endif
char *name;
void __iomem *iobase;
u8 *enetaddr;
@ -479,150 +468,6 @@ static struct pci_device_id supported[] = {
{ }
};
#ifndef CONFIG_DM_ETH
static int dc21x4x_init(struct eth_device *dev, struct bd_info *bis)
{
struct dc2114x_priv *priv =
container_of(dev, struct dc2114x_priv, dev);
/* Ensure we're not sleeping. */
pci_write_config_byte(priv->devno, PCI_CFDA_PSM, WAKEUP);
return dc21x4x_init_common(priv);
}
static void dc21x4x_halt(struct eth_device *dev)
{
struct dc2114x_priv *priv =
container_of(dev, struct dc2114x_priv, dev);
dc21x4x_halt_common(priv);
pci_write_config_byte(priv->devno, PCI_CFDA_PSM, SLEEP);
}
static int dc21x4x_send(struct eth_device *dev, void *packet, int length)
{
struct dc2114x_priv *priv =
container_of(dev, struct dc2114x_priv, dev);
return dc21x4x_send_common(priv, packet, length);
}
static int dc21x4x_recv(struct eth_device *dev)
{
struct dc2114x_priv *priv =
container_of(dev, struct dc2114x_priv, dev);
int length = 0;
int ret;
while (true) {
ret = dc21x4x_recv_check(priv);
if (!ret)
break;
if (ret > 0) {
length = ret;
/* Pass the packet up to the protocol layers */
net_process_received_packet
(net_rx_packets[priv->rx_new], length - 4);
}
/*
* Change buffer ownership for this frame,
* back to the adapter.
*/
if (ret != -EAGAIN)
priv->rx_ring[priv->rx_new].status = cpu_to_le32(R_OWN);
/* Update entry information. */
priv->rx_new = (priv->rx_new + 1) % priv->rx_ring_size;
}
return length;
}
int dc21x4x_initialize(struct bd_info *bis)
{
struct dc2114x_priv *priv;
struct eth_device *dev;
unsigned short status;
unsigned char timer;
unsigned int iobase;
int card_number = 0;
pci_dev_t devbusfn;
int idx = 0;
while (1) {
devbusfn = pci_find_devices(supported, idx++);
if (devbusfn == -1)
break;
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, status);
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEMORY access.\n");
continue;
}
if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
/* Check the latency timer for values >= 0x60. */
pci_read_config_byte(devbusfn, PCI_LATENCY_TIMER, &timer);
if (timer < 0x60) {
pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER,
0x60);
}
/* read BAR for memory space access */
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
debug("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
priv = memalign(32, sizeof(*priv));
if (!priv) {
printf("Can not allocalte memory of dc21x4x\n");
break;
}
memset(priv, 0, sizeof(*priv));
dev = &priv->dev;
sprintf(dev->name, "dc21x4x#%d", card_number);
priv->devno = devbusfn;
priv->name = dev->name;
priv->enetaddr = dev->enetaddr;
dev->iobase = pci_mem_to_phys(devbusfn, iobase);
dev->priv = (void *)devbusfn;
dev->init = dc21x4x_init;
dev->halt = dc21x4x_halt;
dev->send = dc21x4x_send;
dev->recv = dc21x4x_recv;
/* Ensure we're not sleeping. */
pci_write_config_byte(devbusfn, PCI_CFDA_PSM, WAKEUP);
udelay(10 * 1000);
read_hw_addr(priv);
eth_register(dev);
card_number++;
}
return card_number;
}
#else /* DM_ETH */
static int dc2114x_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -756,4 +601,3 @@ U_BOOT_DRIVER(eth_dc2114x) = {
};
U_BOOT_PCI_DEVICE(eth_dc2114x, supported);
#endif

112
drivers/net/designware.c
View File

@ -34,12 +34,8 @@
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
#ifdef CONFIG_DM_ETH
struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
struct eth_mac_regs *mac_p = priv->mac_regs_p;
#else
struct eth_mac_regs *mac_p = bus->priv;
#endif
ulong start;
u16 miiaddr;
int timeout = CONFIG_MDIO_TIMEOUT;
@ -62,12 +58,8 @@ static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
u16 val)
{
#ifdef CONFIG_DM_ETH
struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
struct eth_mac_regs *mac_p = priv->mac_regs_p;
#else
struct eth_mac_regs *mac_p = bus->priv;
#endif
ulong start;
u16 miiaddr;
int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
@ -90,7 +82,7 @@ static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
return ret;
}
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
#if CONFIG_IS_ENABLED(DM_GPIO)
static int __dw_mdio_reset(struct udevice *dev)
{
struct dw_eth_dev *priv = dev_get_priv(dev);
@ -192,7 +184,7 @@ static int dw_mdio_init(const char *name, void *priv)
bus->read = dw_mdio_read;
bus->write = dw_mdio_write;
snprintf(bus->name, sizeof(bus->name), "%s", name);
#if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
#if CONFIG_IS_ENABLED(DM_GPIO)
bus->reset = dw_mdio_reset;
#endif
@ -575,7 +567,7 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
struct phy_device *phydev;
int ret;
#if IS_ENABLED(CONFIG_DM_MDIO) && IS_ENABLED(CONFIG_DM_ETH)
#if IS_ENABLED(CONFIG_DM_MDIO)
phydev = dm_eth_phy_connect(dev);
if (!phydev)
return -ENODEV;
@ -605,103 +597,6 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
return 0;
}
#ifndef CONFIG_DM_ETH
static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
{
int ret;
ret = designware_eth_init(dev->priv, dev->enetaddr);
if (!ret)
ret = designware_eth_enable(dev->priv);
return ret;
}
static int dw_eth_send(struct eth_device *dev, void *packet, int length)
{
return _dw_eth_send(dev->priv, packet, length);
}
static int dw_eth_recv(struct eth_device *dev)
{
uchar *packet;
int length;
length = _dw_eth_recv(dev->priv, &packet);
if (length == -EAGAIN)
return 0;
net_process_received_packet(packet, length);
_dw_free_pkt(dev->priv);
return 0;
}
static void dw_eth_halt(struct eth_device *dev)
{
return _dw_eth_halt(dev->priv);
}
static int dw_write_hwaddr(struct eth_device *dev)
{
return _dw_write_hwaddr(dev->priv, dev->enetaddr);
}
int designware_initialize(ulong base_addr, u32 interface)
{
struct eth_device *dev;
struct dw_eth_dev *priv;
dev = (struct eth_device *) malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
/*
* Since the priv structure contains the descriptors which need a strict
* buswidth alignment, memalign is used to allocate memory
*/
priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
sizeof(struct dw_eth_dev));
if (!priv) {
free(dev);
return -ENOMEM;
}
if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
printf("designware: buffers are outside DMA memory\n");
return -EINVAL;
}
memset(dev, 0, sizeof(struct eth_device));
memset(priv, 0, sizeof(struct dw_eth_dev));
sprintf(dev->name, "dwmac.%lx", base_addr);
dev->iobase = (int)base_addr;
dev->priv = priv;
priv->dev = dev;
priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
DW_DMA_BASE_OFFSET);
dev->init = dw_eth_init;
dev->send = dw_eth_send;
dev->recv = dw_eth_recv;
dev->halt = dw_eth_halt;
dev->write_hwaddr = dw_write_hwaddr;
eth_register(dev);
priv->interface = interface;
dw_mdio_init(dev->name, priv->mac_regs_p);
priv->bus = miiphy_get_dev_by_name(dev->name);
return dw_phy_init(priv, dev);
}
#endif
#ifdef CONFIG_DM_ETH
static int designware_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@ -971,4 +866,3 @@ static struct pci_device_id supported[] = {
};
U_BOOT_PCI_DEVICE(eth_designware, supported);
#endif

5
drivers/net/designware.h
View File

@ -233,9 +233,6 @@ struct dw_eth_dev {
struct eth_mac_regs *mac_regs_p;
struct eth_dma_regs *dma_regs_p;
#ifndef CONFIG_DM_ETH
struct eth_device *dev;
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
struct gpio_desc reset_gpio;
#endif
@ -248,7 +245,6 @@ struct dw_eth_dev {
struct mii_dev *bus;
};
#ifdef CONFIG_DM_ETH
int designware_eth_of_to_plat(struct udevice *dev);
int designware_eth_probe(struct udevice *dev);
extern const struct eth_ops designware_eth_ops;
@ -266,6 +262,5 @@ int designware_eth_free_pkt(struct udevice *dev, uchar *packet,
int length);
void designware_eth_stop(struct udevice *dev);
int designware_eth_write_hwaddr(struct udevice *dev);
#endif
#endif

66
drivers/net/dm9000x.c
View File

@ -75,9 +75,6 @@ struct dm9000_priv {
void (*outblk)(struct dm9000_priv *db, void *data_ptr, int count);
void (*inblk)(struct dm9000_priv *db, void *data_ptr, int count);
void (*rx_status)(struct dm9000_priv *db, u16 *rxstatus, u16 *rxlen);
#ifndef CONFIG_DM_ETH
struct eth_device dev;
#endif
void __iomem *base_io;
void __iomem *base_data;
};
@ -572,68 +569,6 @@ static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr)
static void dm9000_get_enetaddr(struct dm9000_priv *db, u8 *enetaddr) {}
#endif
#ifndef CONFIG_DM_ETH
static int dm9000_init(struct eth_device *dev, struct bd_info *bd)
{
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
return dm9000_init_common(db, dev->enetaddr);
}
static void dm9000_halt(struct eth_device *dev)
{
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
dm9000_halt_common(db);
}
static int dm9000_send(struct eth_device *dev, void *packet, int length)
{
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
return dm9000_send_common(db, packet, length);
}
static int dm9000_recv(struct eth_device *dev)
{
struct dm9000_priv *db = container_of(dev, struct dm9000_priv, dev);
int ret;
ret = dm9000_recv_common(db, net_rx_packets[0]);
if (ret > 0)
net_process_received_packet(net_rx_packets[0], ret);
return ret;
}
int dm9000_initialize(struct bd_info *bis)
{
struct dm9000_priv *priv;
struct eth_device *dev;
priv = calloc(1, sizeof(*priv));
if (!priv)
return -ENOMEM;
dev = &priv->dev;
priv->base_io = (void __iomem *)DM9000_IO;
priv->base_data = (void __iomem *)DM9000_DATA;
/* Load MAC address from EEPROM */
dm9000_get_enetaddr(priv, dev->enetaddr);
dev->init = dm9000_init;
dev->halt = dm9000_halt;
dev->send = dm9000_send;
dev->recv = dm9000_recv;
strcpy(dev->name, "dm9000");
eth_register(&priv->dev);
return 0;
}
#else /* ifdef CONFIG_DM_ETH */
static int dm9000_start(struct udevice *dev)
{
struct dm9000_priv *db = dev_get_priv(dev);
@ -746,4 +681,3 @@ U_BOOT_DRIVER(dm9000) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif

216
drivers/net/e1000.c
View File

@ -65,9 +65,7 @@ DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);
static int tx_tail;
static int rx_tail, rx_last;
#ifdef CONFIG_DM_ETH
static int num_cards; /* Number of E1000 devices seen so far */
#endif
static struct pci_device_id e1000_supported[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
@ -1611,13 +1609,8 @@ e1000_reset_hw(struct e1000_hw *hw)
/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND,
hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#else
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#endif
}
/* Clear interrupt mask to stop board from generating interrupts */
@ -1695,11 +1688,7 @@ e1000_reset_hw(struct e1000_hw *hw)
/* If MWI was previously enabled, reenable it. */
if (hw->mac_type == e1000_82542_rev2_0) {
#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#else
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#endif
}
if (hw->mac_type != e1000_igb)
E1000_WRITE_REG(hw, PBA, pba);
@ -1884,15 +1873,9 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
if (hw->mac_type == e1000_82542_rev2_0) {
DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND,
hw->
pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#else
pci_write_config_word(hw->pdev, PCI_COMMAND,
hw->
pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#endif
E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
E1000_WRITE_FLUSH(hw);
mdelay(5);
@ -1908,11 +1891,7 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
E1000_WRITE_REG(hw, RCTL, 0);
E1000_WRITE_FLUSH(hw);
mdelay(1);
#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#else
pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#endif
}
/* Zero out the Multicast HASH table */
@ -1935,17 +1914,10 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
default:
/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
if (hw->bus_type == e1000_bus_type_pcix) {
#ifdef CONFIG_DM_ETH
dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI,
&pcix_stat_hi_word);
#else
pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
&pcix_cmd_word);
pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI,
&pcix_stat_hi_word);
#endif
cmd_mmrbc =
(pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
PCIX_COMMAND_MMRBC_SHIFT;
@ -1957,13 +1929,8 @@ e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
if (cmd_mmrbc > stat_mmrbc) {
pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
#ifdef CONFIG_DM_ETH
dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER,
pcix_cmd_word);
#else
pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER,
pcix_cmd_word);
#endif
}
}
break;
@ -5060,7 +5027,6 @@ e1000_sw_init(struct e1000_hw *hw)
int result;
/* PCI config space info */
#ifdef CONFIG_DM_ETH
dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
@ -5069,16 +5035,6 @@ e1000_sw_init(struct e1000_hw *hw)
dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
#else
pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id);
pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID,
&hw->subsystem_vendor_id);
pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id);
pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word);
#endif
/* identify the MAC */
result = e1000_set_mac_type(hw);
@ -5485,51 +5441,25 @@ void e1000_get_bus_type(struct e1000_hw *hw)
}
}
#ifndef CONFIG_DM_ETH
/* A list of all registered e1000 devices */
static LIST_HEAD(e1000_hw_list);
#endif
#ifdef CONFIG_DM_ETH
static int e1000_init_one(struct e1000_hw *hw, int cardnum,
struct udevice *devno, unsigned char enetaddr[6])
#else
static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
unsigned char enetaddr[6])
#endif
{
u32 val;
/* Assign the passed-in values */
#ifdef CONFIG_DM_ETH
hw->pdev = devno;
#else
hw->pdev = devno;
#endif
hw->cardnum = cardnum;
/* Print a debug message with the IO base address */
#ifdef CONFIG_DM_ETH
dm_pci_read_config32(devno, PCI_BASE_ADDRESS_0, &val);
#else
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &val);
#endif
E1000_DBG(hw, "iobase 0x%08x\n", val & 0xfffffff0);
/* Try to enable I/O accesses and bus-mastering */
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
#ifdef CONFIG_DM_ETH
dm_pci_write_config32(devno, PCI_COMMAND, val);
#else
pci_write_config_dword(devno, PCI_COMMAND, val);
#endif
/* Make sure it worked */
#ifdef CONFIG_DM_ETH
dm_pci_read_config32(devno, PCI_COMMAND, &val);
#else
pci_read_config_dword(devno, PCI_COMMAND, &val);
#endif
if (!(val & PCI_COMMAND_MEMORY)) {
E1000_ERR(hw, "Can't enable I/O memory\n");
return -ENOSPC;
@ -5548,13 +5478,8 @@ static int e1000_init_one(struct e1000_hw *hw, int cardnum, pci_dev_t devno,
#ifndef CONFIG_E1000_NO_NVM
hw->eeprom_semaphore_present = true;
#endif
#ifdef CONFIG_DM_ETH
hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, 0, 0,
PCI_REGION_TYPE, PCI_REGION_MEM);
#else
hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
PCI_REGION_MEM);
#endif
hw->mac_type = e1000_undefined;
/* MAC and Phy settings */
@ -5599,71 +5524,13 @@ static void e1000_name(char *str, int cardnum)
sprintf(str, "e1000#%u", cardnum);
}
#ifndef CONFIG_DM_ETH
/**************************************************************************
TRANSMIT - Transmit a frame
***************************************************************************/
static int e1000_transmit(struct eth_device *nic, void *txpacket, int length)
{
struct e1000_hw *hw = nic->priv;
return _e1000_transmit(hw, txpacket, length);
}
/**************************************************************************
DISABLE - Turn off ethernet interface
***************************************************************************/
static void
e1000_disable(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
_e1000_disable(hw);
}
/**************************************************************************
INIT - set up ethernet interface(s)
***************************************************************************/
static int
e1000_init(struct eth_device *nic, struct bd_info *bis)
{
struct e1000_hw *hw = nic->priv;
return _e1000_init(hw, nic->enetaddr);
}
static int
e1000_poll(struct eth_device *nic)
{
struct e1000_hw *hw = nic->priv;
int len;
len = _e1000_poll(hw);
if (len) {
net_process_received_packet((uchar *)packet, len);
fill_rx(hw);
}
return len ? 1 : 0;
}
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_DM_ETH
static int e1000_write_hwaddr(struct udevice *dev)
#else
static int e1000_write_hwaddr(struct eth_device *dev)
#endif
{
#ifndef CONFIG_E1000_NO_NVM
unsigned char current_mac[6];
#ifdef CONFIG_DM_ETH
struct eth_pdata *plat = dev_get_plat(dev);
struct e1000_hw *hw = dev_get_priv(dev);
u8 *mac = plat->enetaddr;
#else
struct e1000_hw *hw = dev->priv;
u8 *mac = dev->enetaddr;
#endif
uint16_t data[3];
int ret_val, i;
@ -5701,87 +5568,16 @@ static int e1000_write_hwaddr(struct eth_device *dev)
#endif
}
#ifndef CONFIG_DM_ETH
/**************************************************************************
PROBE - Look for an adapter, this routine's visible to the outside
You should omit the last argument struct pci_device * for a non-PCI NIC
***************************************************************************/
int
e1000_initialize(struct bd_info * bis)
{
unsigned int i;
pci_dev_t devno;
int ret;
DEBUGFUNC();
/* Find and probe all the matching PCI devices */
for (i = 0; (devno = pci_find_devices(e1000_supported, i)) >= 0; i++) {
/*
* These will never get freed due to errors, this allows us to
* perform SPI EEPROM programming from U-Boot, for example.
*/
struct eth_device *nic = malloc(sizeof(*nic));
struct e1000_hw *hw = malloc(sizeof(*hw));
if (!nic || !hw) {
printf("e1000#%u: Out of Memory!\n", i);
free(nic);
free(hw);
continue;
}
/* Make sure all of the fields are initially zeroed */
memset(nic, 0, sizeof(*nic));
memset(hw, 0, sizeof(*hw));
nic->priv = hw;
/* Generate a card name */
e1000_name(nic->name, i);
hw->name = nic->name;
ret = e1000_init_one(hw, i, devno, nic->enetaddr);
if (ret)
continue;
list_add_tail(&hw->list_node, &e1000_hw_list);
hw->nic = nic;
/* Set up the function pointers and register the device */
nic->init = e1000_init;
nic->recv = e1000_poll;
nic->send = e1000_transmit;
nic->halt = e1000_disable;
nic->write_hwaddr = e1000_write_hwaddr;
eth_register(nic);
}
return i;
}
struct e1000_hw *e1000_find_card(unsigned int cardnum)
{
struct e1000_hw *hw;
list_for_each_entry(hw, &e1000_hw_list, list_node)
if (hw->cardnum == cardnum)
return hw;
return NULL;
}
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_CMD_E1000
static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
unsigned char *mac = NULL;
#ifdef CONFIG_DM_ETH
struct eth_pdata *plat;
struct udevice *dev;
char name[30];
int ret;
#endif
#if !defined(CONFIG_DM_ETH) || defined(CONFIG_E1000_SPI)
#if defined(CONFIG_E1000_SPI)
struct e1000_hw *hw;
#endif
int cardnum;
@ -5793,18 +5589,12 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
/* Make sure we can find the requested e1000 card */
cardnum = dectoul(argv[1], NULL);
#ifdef CONFIG_DM_ETH
e1000_name(name, cardnum);
ret = uclass_get_device_by_name(UCLASS_ETH, name, &dev);
if (!ret) {
plat = dev_get_plat(dev);
mac = plat->enetaddr;
}
#else
hw = e1000_find_card(cardnum);
if (hw)
mac = hw->nic->enetaddr;
#endif
if (!mac) {
printf("e1000: ERROR: No such device: e1000#%s\n", argv[1]);
return 1;
@ -5817,9 +5607,7 @@ static int do_e1000(struct cmd_tbl *cmdtp, int flag, int argc,
}
#ifdef CONFIG_E1000_SPI
#ifdef CONFIG_DM_ETH
hw = dev_get_priv(dev);
#endif
/* Handle the "SPI" subcommand */
if (!strcmp(argv[2], "spi"))
return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3);
@ -5843,7 +5631,6 @@ U_BOOT_CMD(
);
#endif /* not CONFIG_CMD_E1000 */
#ifdef CONFIG_DM_ETH
static int e1000_eth_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -5948,4 +5735,3 @@ U_BOOT_DRIVER(eth_e1000) = {
};
U_BOOT_PCI_DEVICE(eth_e1000, e1000_supported);
#endif

11
drivers/net/e1000.h
View File

@ -21,10 +21,6 @@
#include <linux/list.h>
#include <malloc.h>
#include <net.h>
/* Avoids a compile error since struct eth_device is not defined */
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif
#include <asm/io.h>
#include <pci.h>
@ -1077,19 +1073,12 @@ typedef enum {
struct e1000_hw {
const char *name;
struct list_head list_node;
#ifndef CONFIG_DM_ETH
struct eth_device *nic;
#endif
#ifdef CONFIG_E1000_SPI
struct spi_slave spi;
#endif
unsigned int cardnum;
#ifdef CONFIG_DM_ETH
struct udevice *pdev;
#else
pci_dev_t pdev;
#endif
uint8_t *hw_addr;
e1000_mac_type mac_type;
e1000_phy_type phy_type;

134
drivers/net/eepro100.c
View File

@ -206,27 +206,14 @@ struct eepro100_priv {
/* TX descriptor ring pointer */
int tx_next;
int tx_threshold;
#ifdef CONFIG_DM_ETH
struct udevice *devno;
#else
struct eth_device dev;
pci_dev_t devno;
#endif
char *name;
void __iomem *iobase;
u8 *enetaddr;
};
#if defined(CONFIG_DM_ETH)
#define bus_to_phys(dev, a) dm_pci_mem_to_phys((dev), (a))
#define phys_to_bus(dev, a) dm_pci_phys_to_mem((dev), (a))
#elif defined(CONFIG_E500)
#define bus_to_phys(dev, a) (a)
#define phys_to_bus(dev, a) (a)
#else
#define bus_to_phys(dev, a) pci_mem_to_phys((dev), (a))
#define phys_to_bus(dev, a) pci_phys_to_mem((dev), (a))
#endif
static int INW(struct eepro100_priv *priv, u_long addr)
{
@ -778,126 +765,6 @@ done:
return;
}
#ifndef CONFIG_DM_ETH
static int eepro100_init(struct eth_device *dev, struct bd_info *bis)
{
struct eepro100_priv *priv =
container_of(dev, struct eepro100_priv, dev);
return eepro100_init_common(priv);
}
static void eepro100_halt(struct eth_device *dev)
{
struct eepro100_priv *priv =
container_of(dev, struct eepro100_priv, dev);
eepro100_halt_common(priv);
}
static int eepro100_send(struct eth_device *dev, void *packet, int length)
{
struct eepro100_priv *priv =
container_of(dev, struct eepro100_priv, dev);
return eepro100_send_common(priv, packet, length);
}
static int eepro100_recv(struct eth_device *dev)
{
struct eepro100_priv *priv =
container_of(dev, struct eepro100_priv, dev);
uchar *packet;
int ret;
ret = eepro100_recv_common(priv, &packet);
if (ret > 0)
net_process_received_packet(packet, ret);
if (ret)
eepro100_free_pkt_common(priv);
return ret;
}
int eepro100_initialize(struct bd_info *bis)
{
struct eepro100_priv *priv;
struct eth_device *dev;
int card_number = 0;
u32 iobase, status;
pci_dev_t devno;
int idx = 0;
int ret;
while (1) {
/* Find PCI device */
devno = pci_find_devices(supported, idx++);
if (devno < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
iobase &= ~0xf;
debug("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
iobase);
pci_write_config_dword(devno, PCI_COMMAND,
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
/* Check if I/O accesses and Bus Mastering are enabled. */
pci_read_config_dword(devno, PCI_COMMAND, &status);
if (!(status & PCI_COMMAND_MEMORY)) {
printf("Error: Can not enable MEM access.\n");
continue;
}
if (!(status & PCI_COMMAND_MASTER)) {
printf("Error: Can not enable Bus Mastering.\n");
continue;
}
priv = calloc(1, sizeof(*priv));
if (!priv) {
printf("eepro100: Can not allocate memory\n");
break;
}
dev = &priv->dev;
sprintf(dev->name, "i82559#%d", card_number);
priv->name = dev->name;
/* this have to come before bus_to_phys() */
priv->devno = devno;
priv->iobase = (void __iomem *)bus_to_phys(devno, iobase);
priv->enetaddr = dev->enetaddr;
dev->init = eepro100_init;
dev->halt = eepro100_halt;
dev->send = eepro100_send;
dev->recv = eepro100_recv;
eth_register(dev);
ret = eepro100_initialize_mii(priv);
if (ret) {
eth_unregister(dev);
free(priv);
return ret;
}
card_number++;
/* Set the latency timer for value. */
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
udelay(10 * 1000);
eepro100_get_hwaddr(priv);
}
return card_number;
}
#else /* DM_ETH */
static int eepro100_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -1014,4 +881,3 @@ U_BOOT_DRIVER(eth_eepro100) = {
};
U_BOOT_PCI_DEVICE(eth_eepro100, supported);
#endif

85
drivers/net/ethoc.c
View File

@ -643,8 +643,6 @@ static inline int ethoc_phy_init(struct ethoc *priv, void *dev)
#endif
#ifdef CONFIG_DM_ETH
static int ethoc_write_hwaddr(struct udevice *dev)
{
struct ethoc_eth_pdata *pdata = dev_get_plat(dev);
@ -753,86 +751,3 @@ U_BOOT_DRIVER(ethoc) = {
.priv_auto = sizeof(struct ethoc),
.plat_auto = sizeof(struct ethoc_eth_pdata),
};
#else
static int ethoc_init(struct eth_device *dev, struct bd_info *bd)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
return ethoc_init_common(priv);
}
static int ethoc_write_hwaddr(struct eth_device *dev)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
u8 *mac = dev->enetaddr;
return ethoc_write_hwaddr_common(priv, mac);
}
static int ethoc_send(struct eth_device *dev, void *packet, int length)
{
return ethoc_send_common(dev->priv, packet, length);
}
static void ethoc_halt(struct eth_device *dev)
{
ethoc_disable_rx_and_tx(dev->priv);
}
static int ethoc_recv(struct eth_device *dev)
{
struct ethoc *priv = (struct ethoc *)dev->priv;
int count;
if (!ethoc_is_new_packet_received(priv))
return 0;
for (count = 0; count < PKTBUFSRX; ++count) {
uchar *packetp;
int size = ethoc_rx_common(priv, &packetp);
if (size < 0)
break;
if (size > 0)
net_process_received_packet(packetp, size);
ethoc_free_pkt_common(priv);
}
return 0;
}
int ethoc_initialize(u8 dev_num, int base_addr)
{
struct ethoc *priv;
struct eth_device *dev;
priv = malloc(sizeof(*priv));
if (!priv)
return 0;
dev = malloc(sizeof(*dev));
if (!dev) {
free(priv);
return 0;
}
memset(dev, 0, sizeof(*dev));
dev->priv = priv;
dev->iobase = base_addr;
dev->init = ethoc_init;
dev->halt = ethoc_halt;
dev->send = ethoc_send;
dev->recv = ethoc_recv;
dev->write_hwaddr = ethoc_write_hwaddr;
sprintf(dev->name, "%s-%hu", "ETHOC", dev_num);
priv->iobase = ioremap(dev->iobase, ETHOC_IOSIZE);
eth_register(dev);
ethoc_mdio_init(dev->name, priv);
ethoc_phy_init(priv, dev);
return 1;
}
#endif

2
drivers/net/fec_mxc.h
View File

@ -263,9 +263,7 @@ struct fec_priv {
uint32_t reset_delay;
uint32_t reset_post_delay;
#endif
#ifdef CONFIG_DM_ETH
u32 interface;
#endif
struct clk ipg_clk;
struct clk ahb_clk;
struct clk clk_enet_out;

1
drivers/net/fm/Makefile
View File

@ -6,7 +6,6 @@ obj-y += dtsec.o
obj-y += eth.o
obj-y += fdt.o
obj-y += fm.o
obj-y += init.o
obj-y += tgec.o
obj-y += tgec_phy.o

238
drivers/net/fm/eth.c
View File

@ -8,12 +8,10 @@
#include <log.h>
#include <part.h>
#include <asm/io.h>
#ifdef CONFIG_DM_ETH
#include <dm.h>
#include <dm/ofnode.h>
#include <linux/compat.h>
#include <phy_interface.h>
#endif
#include <malloc.h>
#include <net.h>
#include <hwconfig.h>
@ -28,11 +26,6 @@
#include "fm.h"
#ifndef CONFIG_DM_ETH
static struct eth_device *devlist[NUM_FM_PORTS];
static int num_controllers;
#endif
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
@ -53,14 +46,10 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
PHY_INTERFACE_MODE_2500BASEX) ? true : false;
int i = 0, j;
#ifndef CONFIG_DM_ETH
bus.priv = priv->mac->phyregs;
#else
bus.priv = priv->pcs_mdio;
bus.read = memac_mdio_read;
bus.write = memac_mdio_write;
bus.reset = memac_mdio_reset;
#endif
qsgmii_loop:
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
@ -136,19 +125,6 @@ static void dtsec_init_phy(struct fm_eth *fm_eth)
fm_eth->enet_if == PHY_INTERFACE_MODE_2500BASEX)
dtsec_configure_serdes(fm_eth);
}
#ifndef CONFIG_DM_ETH
#ifdef CONFIG_PHYLIB
static int tgec_is_fibre(struct fm_eth *fm)
{
char phyopt[20];
sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
return hwconfig_arg_cmp(phyopt, "xfi");
}
#endif
#endif /* CONFIG_DM_ETH */
#endif
static u16 muram_readw(u16 *addr)
@ -465,18 +441,10 @@ static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
sync();
}
#ifndef CONFIG_DM_ETH
static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
#else
static int fm_eth_open(struct udevice *dev)
#endif
{
#ifndef CONFIG_DM_ETH
struct fm_eth *fm_eth = dev->priv;
#else
struct eth_pdata *pdata = dev_get_plat(dev);
struct fm_eth *fm_eth = dev_get_priv(dev);
#endif
unsigned char *enetaddr;
struct fsl_enet_mac *mac;
#ifdef CONFIG_PHYLIB
@ -485,11 +453,7 @@ static int fm_eth_open(struct udevice *dev)
mac = fm_eth->mac;
#ifndef CONFIG_DM_ETH
enetaddr = &dev->enetaddr[0];
#else
enetaddr = pdata->enetaddr;
#endif
/* setup the MAC address */
if (enetaddr[0] & 0x01) {
@ -512,12 +476,7 @@ static int fm_eth_open(struct udevice *dev)
if (fm_eth->phydev) {
ret = phy_startup(fm_eth->phydev);
if (ret) {
#ifndef CONFIG_DM_ETH
printf("%s: Could not initialize\n",
fm_eth->phydev->dev->name);
#else
printf("%s: Could not initialize\n", dev->name);
#endif
return ret;
}
} else {
@ -540,20 +499,12 @@ static int fm_eth_open(struct udevice *dev)
return fm_eth->phydev->link ? 0 : -1;
}
#ifndef CONFIG_DM_ETH
static void fm_eth_halt(struct eth_device *dev)
#else
static void fm_eth_halt(struct udevice *dev)
#endif
{
struct fm_eth *fm_eth;
struct fsl_enet_mac *mac;
#ifndef CONFIG_DM_ETH
fm_eth = (struct fm_eth *)dev->priv;
#else
fm_eth = dev_get_priv(dev);
#endif
mac = fm_eth->mac;
/* graceful stop the transmission of frames */
@ -571,11 +522,7 @@ static void fm_eth_halt(struct udevice *dev)
#endif
}
#ifndef CONFIG_DM_ETH
static int fm_eth_send(struct eth_device *dev, void *buf, int len)
#else
static int fm_eth_send(struct udevice *dev, void *buf, int len)
#endif
{
struct fm_eth *fm_eth;
struct fm_port_global_pram *pram;
@ -583,11 +530,7 @@ static int fm_eth_send(struct udevice *dev, void *buf, int len)
u16 offset_in;
int i;
#ifndef CONFIG_DM_ETH
fm_eth = (struct fm_eth *)dev->priv;
#else
fm_eth = dev_get_priv(dev);
#endif
pram = fm_eth->tx_pram;
txbd = fm_eth->cur_txbd;
@ -668,11 +611,7 @@ static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
return rxbd;
}
#ifndef CONFIG_DM_ETH
static int fm_eth_recv(struct eth_device *dev)
#else
static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
#endif
{
struct fm_eth *fm_eth;
struct fm_port_bd *rxbd;
@ -681,11 +620,7 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
int ret = -1;
u8 *data;
#ifndef CONFIG_DM_ETH
fm_eth = (struct fm_eth *)dev->priv;
#else
fm_eth = dev_get_priv(dev);
#endif
rxbd = fm_eth->cur_rxbd;
status = muram_readw(&rxbd->status);
@ -695,12 +630,8 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
buf_lo = in_be32(&rxbd->buf_ptr_lo);
data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
len = muram_readw(&rxbd->len);
#ifndef CONFIG_DM_ETH
net_process_received_packet(data, len);
#else
*packetp = data;
return len;
#endif
} else {
printf("%s: Rx error\n", dev->name);
ret = 0;
@ -717,7 +648,6 @@ static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
return ret;
}
#ifdef CONFIG_DM_ETH
static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct fm_eth *fm_eth = (struct fm_eth *)dev_get_priv(dev);
@ -726,65 +656,7 @@ static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
return 0;
}
#endif /* CONFIG_DM_ETH */
#ifndef CONFIG_DM_ETH
static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
{
struct fsl_enet_mac *mac;
int num;
void *base, *phyregs = NULL;
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
if (fm_eth->type == FM_ETH_10G_E) {
/* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
* 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
* 10GEC1 uses mEMAC1 on T1024.
* so it needs to change the num.
*/
if (fm_eth->num >= 2)
num -= 2;
else
num += 8;
}
#endif
base = &reg->memac[num].fm_memac;
phyregs = &reg->memac[num].fm_memac_mdio;
#else
/* Get the mac registers base address */
if (fm_eth->type == FM_ETH_1G_E) {
base = &reg->mac_1g[num].fm_dtesc;
phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
} else {
base = &reg->mac_10g[num].fm_10gec;
phyregs = &reg->mac_10g[num].fm_10gec_mdio;
}
#endif
/* alloc mac controller */
mac = malloc(sizeof(struct fsl_enet_mac));
if (!mac)
return -ENOMEM;
memset(mac, 0, sizeof(struct fsl_enet_mac));
/* save the mac to fm_eth struct */
fm_eth->mac = mac;
#ifdef CONFIG_SYS_FMAN_V3
init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
#else
if (fm_eth->type == FM_ETH_1G_E)
init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
else
init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
#endif
return 0;
}
#else /* CONFIG_DM_ETH */
static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
{
#ifndef CONFIG_SYS_FMAN_V3
@ -817,15 +689,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
return 0;
}
#endif /* CONFIG_DM_ETH */
static int init_phy(struct fm_eth *fm_eth)
{
#ifdef CONFIG_PHYLIB
u32 supported = PHY_GBIT_FEATURES;
#ifndef CONFIG_DM_ETH
struct phy_device *phydev = NULL;
#endif
if (fm_eth->type == FM_ETH_10G_E)
supported = PHY_10G_FEATURES;
@ -836,7 +704,6 @@ static int init_phy(struct fm_eth *fm_eth)
if (fm_eth->type == FM_ETH_1G_E)
dtsec_init_phy(fm_eth);
#ifdef CONFIG_DM_ETH
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_MDIO
fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
@ -848,113 +715,9 @@ static int init_phy(struct fm_eth *fm_eth)
phy_config(fm_eth->phydev);
#endif
#else /* CONFIG_DM_ETH */
#ifdef CONFIG_PHYLIB
if (fm_eth->bus) {
phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
fm_eth->enet_if);
if (!phydev) {
printf("Failed to connect\n");
return -1;
}
} else {
return 0;
}
if (fm_eth->type == FM_ETH_1G_E) {
supported = (SUPPORTED_10baseT_Half |
SUPPORTED_10baseT_Full |
SUPPORTED_100baseT_Half |
SUPPORTED_100baseT_Full |
SUPPORTED_1000baseT_Full);
} else {
supported = SUPPORTED_10000baseT_Full;
if (tgec_is_fibre(fm_eth))
phydev->port = PORT_FIBRE;
}
phydev->supported &= supported;
phydev->advertising = phydev->supported;
fm_eth->phydev = phydev;
phy_config(phydev);
#endif
#endif /* CONFIG_DM_ETH */
return 0;
}
#ifndef CONFIG_DM_ETH
int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
{
struct eth_device *dev;
struct fm_eth *fm_eth;
int i, num = info->num;
int ret;
/* alloc eth device */
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev)
return -ENOMEM;
memset(dev, 0, sizeof(struct eth_device));
/* alloc the FMan ethernet private struct */
fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
if (!fm_eth)
return -ENOMEM;
memset(fm_eth, 0, sizeof(struct fm_eth));
/* save off some things we need from the info struct */
fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
fm_eth->num = num;
fm_eth->type = info->type;
fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
/* set the ethernet max receive length */
fm_eth->max_rx_len = MAX_RXBUF_LEN;
/* init global mac structure */
ret = fm_eth_init_mac(fm_eth, reg);
if (ret)
return ret;
/* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
if (fm_eth->type == FM_ETH_1G_E)
sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
else
sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
devlist[num_controllers++] = dev;
dev->iobase = 0;
dev->priv = (void *)fm_eth;
dev->init = fm_eth_open;
dev->halt = fm_eth_halt;
dev->send = fm_eth_send;
dev->recv = fm_eth_recv;
fm_eth->dev = dev;
fm_eth->bus = info->bus;
fm_eth->phyaddr = info->phy_addr;
fm_eth->enet_if = info->enet_if;
/* startup the FM im */
ret = fm_eth_startup(fm_eth);
if (ret)
return ret;
init_phy(fm_eth);
/* clear the ethernet address */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
return 0;
}
#else /* CONFIG_DM_ETH */
static int fm_eth_bind(struct udevice *dev)
{
char mac_name[11];
@ -1139,4 +902,3 @@ U_BOOT_DRIVER(eth_fman) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */

4
drivers/net/fm/fm.c
View File

@ -10,9 +10,7 @@
#include <asm/io.h>
#include <linux/errno.h>
#include <u-boot/crc.h>
#ifdef CONFIG_DM_ETH
#include <dm.h>
#endif
#include "fm.h"
#include <fsl_qe.h> /* For struct qe_firmware */
@ -551,7 +549,6 @@ int fm_init_common(int index, struct ccsr_fman *reg)
}
#endif
#ifdef CONFIG_DM_ETH
struct fman_priv {
struct ccsr_fman *reg;
unsigned int fman_id;
@ -626,4 +623,3 @@ U_BOOT_DRIVER(fman) = {
.priv_auto = sizeof(struct fman_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */

8
drivers/net/fm/fm.h
View File

@ -57,7 +57,6 @@ struct fm_port_bd {
#define TxBD_READY 0x8000
#define TxBD_LAST BD_LAST
#ifdef CONFIG_DM_ETH
enum fm_mac_type {
#ifdef CONFIG_SYS_FMAN_V3
FM_MEMAC,
@ -66,7 +65,6 @@ enum fm_mac_type {
FM_TGEC,
#endif
};
#endif
/* Fman ethernet private struct */
/* Rx/Tx queue descriptor */
@ -115,9 +113,7 @@ void fman_disable_port(enum fm_port port);
void fman_enable_port(enum fm_port port);
int fman_id(struct udevice *dev);
void *fman_port(struct udevice *dev, int num);
#ifdef CONFIG_DM_ETH
void *fman_mdio(struct udevice *dev, enum fm_mac_type type, int num);
#endif
struct fsl_enet_mac {
void *base; /* MAC controller registers base address */
@ -143,13 +139,9 @@ struct fm_eth {
struct mii_dev *bus;
struct phy_device *phydev;
int phyaddr;
#ifndef CONFIG_DM_ETH
struct eth_device *dev;
#else
enum fm_mac_type mac_type;
struct udevice *dev;
struct udevice *pcs_mdio;
#endif
int max_rx_len;
struct fm_port_global_pram *rx_pram; /* Rx parameter table */
struct fm_port_global_pram *tx_pram; /* Tx parameter table */

386
drivers/net/fm/init.c
View File

@ -1,386 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2015 Freescale Semiconductor, Inc.
*/
#include <errno.h>
#include <common.h>
#include <net.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <fsl_mdio.h>
#ifdef CONFIG_FSL_LAYERSCAPE
#include <asm/arch/fsl_serdes.h>
#include <linux/libfdt.h>
#else
#include <asm/fsl_serdes.h>
#endif
#include "fm.h"
#ifndef CONFIG_DM_ETH
struct fm_eth_info fm_info[] = {
#if (CFG_SYS_NUM_FM1_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(1, 1),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(1, 2),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(1, 3),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(1, 4),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(1, 5),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(1, 6),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(1, 9),
#endif
#if (CFG_SYS_NUM_FM1_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(1, 10),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 1)
FM_DTSEC_INFO_INITIALIZER(2, 1),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 2)
FM_DTSEC_INFO_INITIALIZER(2, 2),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 3)
FM_DTSEC_INFO_INITIALIZER(2, 3),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 4)
FM_DTSEC_INFO_INITIALIZER(2, 4),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 5)
FM_DTSEC_INFO_INITIALIZER(2, 5),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 6)
FM_DTSEC_INFO_INITIALIZER(2, 6),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 7)
FM_DTSEC_INFO_INITIALIZER(2, 9),
#endif
#if (CFG_SYS_NUM_FM2_DTSEC >= 8)
FM_DTSEC_INFO_INITIALIZER(2, 10),
#endif
#if (CFG_SYS_NUM_FM1_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(1, 1),
#endif
#if (CFG_SYS_NUM_FM1_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(1, 2),
#endif
#if (CFG_SYS_NUM_FM1_10GEC >= 3)
FM_TGEC_INFO_INITIALIZER2(1, 3),
#endif
#if (CFG_SYS_NUM_FM1_10GEC >= 4)
FM_TGEC_INFO_INITIALIZER2(1, 4),
#endif
#if (CFG_SYS_NUM_FM2_10GEC >= 1)
FM_TGEC_INFO_INITIALIZER(2, 1),
#endif
#if (CFG_SYS_NUM_FM2_10GEC >= 2)
FM_TGEC_INFO_INITIALIZER(2, 2),
#endif
};
int fm_standard_init(struct bd_info *bis)
{
int i;
struct ccsr_fman *reg;
reg = (void *)CFG_SYS_FSL_FM1_ADDR;
if (fm_init_common(0, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 1))
fm_eth_initialize(reg, &fm_info[i]);
}
#if (CFG_SYS_NUM_FMAN == 2)
reg = (void *)CFG_SYS_FSL_FM2_ADDR;
if (fm_init_common(1, reg))
return 0;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if ((fm_info[i].enabled) && (fm_info[i].index == 2))
fm_eth_initialize(reg, &fm_info[i]);
}
#endif
return 1;
}
/* simple linear search to map from port to array index */
static int fm_port_to_index(enum fm_port port)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
if (fm_info[i].port == port)
return i;
}
return -1;
}
/*
* Determine if an interface is actually active based on HW config
* we expect fman_port_enet_if() to report PHY_INTERFACE_MODE_NA if
* the interface is not active based on HW cfg of the SoC
*/
void fman_enet_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
phy_interface_t enet_if;
enet_if = fman_port_enet_if(fm_info[i].port);
if (enet_if != PHY_INTERFACE_MODE_NA) {
fm_info[i].enabled = 1;
fm_info[i].enet_if = enet_if;
} else {
fm_info[i].enabled = 0;
}
}
return;
}
void fm_disable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 0;
#ifndef CONFIG_SYS_FMAN_V3
fman_disable_port(port);
#endif
}
void fm_enable_port(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].enabled = 1;
fman_enable_port(port);
}
void fm_info_set_mdio(enum fm_port port, struct mii_dev *bus)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].bus = bus;
}
void fm_info_set_phy_address(enum fm_port port, int address)
{
int i = fm_port_to_index(port);
if (i == -1)
return;
fm_info[i].phy_addr = address;
}
/*
* Returns the PHY address for a given Fman port
*
* The port must be set via a prior call to fm_info_set_phy_address().
* A negative error code is returned if the port is invalid.
*/
int fm_info_get_phy_address(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return -1;
return fm_info[i].phy_addr;
}
/*
* Returns the type of the data interface between the given MAC and its PHY.
* This is typically determined by the RCW.
*/
phy_interface_t fm_info_get_enet_if(enum fm_port port)
{
int i = fm_port_to_index(port);
if (i == -1)
return PHY_INTERFACE_MODE_NA;
if (fm_info[i].enabled)
return fm_info[i].enet_if;
return PHY_INTERFACE_MODE_NA;
}
static void
__def_board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
{
return;
}
void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa,
enum fm_port port, int offset)
__attribute__((weak, alias("__def_board_ft_fman_fixup_port")));
int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
{
int off;
uint32_t ph;
phys_addr_t paddr = CFG_SYS_CCSRBAR_PHYS + info->compat_offset;
#ifndef CONFIG_SYS_FMAN_V3
u64 dtsec1_addr = (u64)CFG_SYS_CCSRBAR_PHYS +
CFG_SYS_FSL_FM1_DTSEC1_OFFSET;
#endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
if (off == -FDT_ERR_NOTFOUND)
return -EINVAL;
if (info->enabled) {
fdt_fixup_phy_connection(blob, off, info->enet_if);
board_ft_fman_fixup_port(blob, prop, paddr, info->port, off);
return 0;
}
#ifdef CONFIG_SYS_FMAN_V3
#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
/*
* On T2/T4 SoCs, physically FM1_DTSEC9 and FM1_10GEC1 use the same
* dual-role MAC, when FM1_10GEC1 is enabled and FM1_DTSEC9
* is disabled, ensure that the dual-role MAC is not disabled,
* ditto for other dual-role MACs.
*/
if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC2)))
#if (CFG_SYS_NUM_FMAN == 2)
||
((info->port == FM2_DTSEC9) && (PORT_IS_ENABLED(FM2_10GEC1))) ||
((info->port == FM2_DTSEC10) && (PORT_IS_ENABLED(FM2_10GEC2))) ||
((info->port == FM2_10GEC1) && (PORT_IS_ENABLED(FM2_DTSEC9))) ||
((info->port == FM2_10GEC2) && (PORT_IS_ENABLED(FM2_DTSEC10)))
#endif
#else
/* FM1_DTSECx and FM1_10GECx use the same dual-role MAC */
if (((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
((info->port == FM1_DTSEC3) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC4) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC2))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC3))) ||
((info->port == FM1_10GEC4) && (PORT_IS_ENABLED(FM1_DTSEC4)))
#endif
)
return 0;
#endif
/* board code might have caused offset to change */
off = fdt_node_offset_by_compat_reg(blob, prop, paddr);
#ifndef CONFIG_SYS_FMAN_V3
/* Don't disable FM1-DTSEC1 MAC as its used for MDIO */
if (paddr != dtsec1_addr)
#endif
fdt_status_disabled(blob, off); /* disable the MAC node */
/* disable the fsl,dpa-ethernet node that points to the MAC */
ph = fdt_get_phandle(blob, off);
do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph),
"status", "disabled", strlen("disabled") + 1, 1);
return 0;
}
void fdt_fixup_fman_ethernet(void *blob)
{
int i;
#ifdef CONFIG_SYS_FMAN_V3
for (i = 0; i < ARRAY_SIZE(fm_info); i++)
ft_fixup_port(blob, &fm_info[i], "fsl,fman-memac");
#else
for (i = 0; i < ARRAY_SIZE(fm_info); i++) {
/* Try the new compatible first.
* If the node is missing, try the old.
*/
if (fm_info[i].type == FM_ETH_1G_E) {
if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-dtsec"))
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-1g-mac");
} else {
if (ft_fixup_port(blob, &fm_info[i], "fsl,fman-xgec") &&
ft_fixup_port(blob, &fm_info[i], "fsl,fman-tgec"))
ft_fixup_port(blob, &fm_info[i],
"fsl,fman-10g-mac");
}
}
#endif
}
/*QSGMII Riser Card can work in SGMII mode, but the PHY address is different.
*This function scans which Riser Card being used(QSGMII or SGMII Riser Card),
*then set the correct PHY address
*/
void set_sgmii_phy(struct mii_dev *bus, enum fm_port base_port,
unsigned int port_num, int phy_base_addr)
{
unsigned int regnum = 0;
int qsgmii;
int i;
int phy_real_addr;
qsgmii = is_qsgmii_riser_card(bus, phy_base_addr, port_num, regnum);
if (!qsgmii)
return;
for (i = base_port; i < base_port + port_num; i++) {
if (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_SGMII) {
phy_real_addr = phy_base_addr + i - base_port;
fm_info_set_phy_address(i, phy_real_addr);
}
}
}
/*to check whether qsgmii riser card is used*/
int is_qsgmii_riser_card(struct mii_dev *bus, int phy_base_addr,
unsigned int port_num, unsigned regnum)
{
int i;
int val;
if (!bus)
return 0;
for (i = phy_base_addr; i < phy_base_addr + port_num; i++) {
val = bus->read(bus, i, MDIO_DEVAD_NONE, regnum);
if (val != MIIM_TIMEOUT)
return 1;
}
return 0;
}
#endif /* CONFIG_DM_ETH */

52
drivers/net/fm/memac_phy.c
View File

@ -22,11 +22,9 @@
#define memac_setbits_32(a, v) setbits_be32(a, v)
#endif
#ifdef CONFIG_DM_ETH
struct fm_mdio_priv {
struct memac_mdio_controller *regs;
};
#endif
#define MAX_NUM_RETRIES 1000
@ -88,9 +86,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
u32 c45 = 1; /* Default to 10G interface */
int err;
#ifndef CONFIG_DM_ETH
regs = bus->priv;
#else
struct fm_mdio_priv *priv;
if (!bus->priv)
@ -99,7 +94,6 @@ int memac_mdio_write(struct mii_dev *bus, int port_addr, int dev_addr,
regs = priv->regs;
debug("memac_mdio_write(regs %p, port %d, dev %d, reg %d, val %#x)\n",
regs, port_addr, dev_addr, regnum, value);
#endif
if (dev_addr == MDIO_DEVAD_NONE) {
c45 = 0; /* clause 22 */
@ -147,22 +141,14 @@ int memac_mdio_read(struct mii_dev *bus, int port_addr, int dev_addr,
u32 c45 = 1;
int err;
#ifndef CONFIG_DM_ETH
regs = bus->priv;
#else
struct fm_mdio_priv *priv;
if (!bus->priv)
return -EINVAL;
priv = dev_get_priv(bus->priv);
regs = priv->regs;
#endif
if (dev_addr == MDIO_DEVAD_NONE) {
#ifndef CONFIG_DM_ETH
if (!strcmp(bus->name, DEFAULT_FM_TGEC_MDIO_NAME))
return 0xffff;
#endif
c45 = 0; /* clause 22 */
dev_addr = regnum & 0x1f;
memac_clrbits_32(&regs->mdio_stat, MDIO_STAT_ENC);
@ -205,43 +191,6 @@ int memac_mdio_reset(struct mii_dev *bus)
return 0;
}
#ifndef CONFIG_DM_ETH
int fm_memac_mdio_init(struct bd_info *bis, struct memac_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate FM TGEC MDIO bus\n");
return -1;
}
bus->read = memac_mdio_read;
bus->write = memac_mdio_write;
bus->reset = memac_mdio_reset;
strcpy(bus->name, info->name);
bus->priv = info->regs;
/*
* On some platforms like B4860, default value of MDIO_CLK_DIV bits
* in mdio_stat(mdio_cfg) register generates MDIO clock too high
* (much higher than 2.5MHz), violating the IEEE specs.
* On other platforms like T1040, default value of MDIO_CLK_DIV bits
* is zero, so MDIO clock is disabled.
* So, for proper functioning of MDIO, MDIO_CLK_DIV bits needs to
* be properly initialized.
* NEG bit default should be '1' as per FMAN-v3 RM, but on platform
* like T2080QDS, this bit default is '0', which leads to MDIO failure
* on XAUI PHY, so set this bit definitely.
*/
memac_setbits_32(
&((struct memac_mdio_controller *)info->regs)->mdio_stat,
MDIO_STAT_CLKDIV(258) | MDIO_STAT_NEG);
return mdio_register(bus);
}
#else /* CONFIG_DM_ETH */
#if defined(CONFIG_PHYLIB) && defined(CONFIG_DM_MDIO)
static int fm_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
@ -341,4 +290,3 @@ U_BOOT_DRIVER(fman_mdio) = {
.plat_auto = sizeof(struct mdio_perdev_priv),
};
#endif /* CONFIG_PHYLIB && CONFIG_DM_MDIO */
#endif /* CONFIG_DM_ETH */

21
drivers/net/fsl-mc/mc.c
View File

@ -165,21 +165,12 @@ enum mc_fixup_type {
};
static int mc_fixup_mac_addr(void *blob, int nodeoffset,
#ifdef CONFIG_DM_ETH
const char *propname, struct udevice *eth_dev,
#else
const char *propname, struct eth_device *eth_dev,
#endif
enum mc_fixup_type type)
{
#ifdef CONFIG_DM_ETH
struct eth_pdata *plat = dev_get_plat(eth_dev);
unsigned char *enetaddr = plat->enetaddr;
int eth_index = dev_seq(eth_dev);
#else
unsigned char *enetaddr = eth_dev->enetaddr;
int eth_index = eth_dev->index;
#endif
int err = 0, len = 0, size, i;
unsigned char env_enetaddr[ARP_HLEN];
unsigned int enetaddr_32[ARP_HLEN];
@ -252,11 +243,7 @@ const char *dpl_get_connection_endpoint(void *blob, char *endpoint)
}
static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id,
#ifdef CONFIG_DM_ETH
struct udevice *eth_dev)
#else
struct eth_device *eth_dev)
#endif
{
int objoff = fdt_path_offset(blob, "/objects");
int dpmacoff = -1, dpnioff = -1;
@ -355,11 +342,7 @@ void fdt_fsl_mc_fixup_iommu_map_entry(void *blob)
}
static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
#ifdef CONFIG_DM_ETH
struct udevice *eth_dev)
#else
struct eth_device *eth_dev)
#endif
{
int nodeoffset = fdt_path_offset(blob, "/board_info/ports"), noff;
int err = 0;
@ -402,12 +385,8 @@ static int mc_fixup_dpc_mac_addr(void *blob, int dpmac_id,
static int mc_fixup_mac_addrs(void *blob, enum mc_fixup_type type)
{
int i, err = 0, ret = 0;
#ifdef CONFIG_DM_ETH
#define ETH_NAME_LEN 20
struct udevice *eth_dev;
#else
struct eth_device *eth_dev;
#endif
char ethname[ETH_NAME_LEN];
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {

198
drivers/net/ldpaa_eth/ldpaa_eth.c
View File

@ -24,7 +24,6 @@
#include "ldpaa_eth.h"
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_ETH
static void init_phy(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
@ -36,51 +35,6 @@ static void init_phy(struct udevice *dev)
phy_config(priv->phy);
}
#else
static int init_phy(struct eth_device *dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
struct phy_device *phydev = NULL;
struct mii_dev *bus;
int phy_addr, phy_num;
int ret = 0;
bus = wriop_get_mdio(priv->dpmac_id);
if (bus == NULL)
return 0;
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
phy_addr = wriop_get_phy_address(priv->dpmac_id, phy_num);
if (phy_addr < 0)
continue;
phydev = phy_connect(bus, phy_addr, dev,
wriop_get_enet_if(priv->dpmac_id));
if (!phydev) {
printf("Failed to connect\n");
ret = -ENODEV;
break;
}
wriop_set_phy_dev(priv->dpmac_id, phy_num, phydev);
ret = phy_config(phydev);
if (ret)
break;
}
if (ret) {
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
if (!phydev)
continue;
free(phydev);
wriop_set_phy_dev(priv->dpmac_id, phy_num, NULL);
}
}
return ret;
}
#endif
#endif
#ifdef DEBUG
@ -147,15 +101,9 @@ static void ldpaa_eth_get_dpni_counter(void)
}
}
#ifdef CONFIG_DM_ETH
static void ldpaa_eth_get_dpmac_counter(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static void ldpaa_eth_get_dpmac_counter(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
#endif
int err = 0;
u64 value;
@ -288,16 +236,10 @@ error:
return;
}
#ifdef CONFIG_DM_ETH
static int ldpaa_eth_pull_dequeue_rx(struct udevice *dev,
int flags, uchar **packetp)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)dev->priv;
#endif
const struct ldpaa_dq *dq;
const struct dpaa_fd *fd;
int i = 5, err = 0, status;
@ -354,15 +296,9 @@ static int ldpaa_eth_pull_dequeue_rx(struct eth_device *dev)
return err;
}
#ifdef CONFIG_DM_ETH
static int ldpaa_eth_tx(struct udevice *dev, void *buf, int len)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static int ldpaa_eth_tx(struct eth_device *net_dev, void *buf, int len)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
#endif
struct dpaa_fd fd;
u64 buffer_start;
int data_offset, err;
@ -438,27 +374,6 @@ error:
return err;
}
static struct phy_device *ldpaa_get_phydev(struct ldpaa_eth_priv *priv)
{
#ifdef CONFIG_DM_ETH
return priv->phy;
#else
#ifdef CONFIG_PHYLIB
struct phy_device *phydev = NULL;
int phy_num;
/* start the phy devices one by one and update the dpmac state */
for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
phydev = wriop_get_phy_dev(priv->dpmac_id, phy_num);
if (phydev)
return phydev;
}
return NULL;
#endif
return NULL;
#endif
}
static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
struct dpmac_link_state *state)
{
@ -479,7 +394,7 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
state->up = 1;
state->options |= DPMAC_LINK_OPT_AUTONEG;
phydev = ldpaa_get_phydev(priv);
phydev = priv->phy;
if (phydev) {
err = phy_startup(phydev);
@ -509,16 +424,10 @@ static int ldpaa_get_dpmac_state(struct ldpaa_eth_priv *priv,
return 0;
}
#ifdef CONFIG_DM_ETH
static int ldpaa_eth_open(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
#endif
struct dpmac_link_state dpmac_link_state = { 0 };
#ifdef DEBUG
struct dpni_link_state link_state;
@ -526,13 +435,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
int err = 0;
struct dpni_queue d_queue;
#ifdef CONFIG_DM_ETH
if (eth_is_active(dev))
return 0;
#else
if (net_dev->state == ETH_STATE_ACTIVE)
return 0;
#endif
if (get_mc_boot_status() != 0) {
printf("ERROR (MC is not booted)\n");
@ -572,13 +476,8 @@ static int ldpaa_eth_open(struct eth_device *net_dev, struct bd_info *bd)
if (err)
goto err_dpni_bind;
#ifdef CONFIG_DM_ETH
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, plat->enetaddr);
#else
err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS,
dflt_dpni->dpni_handle, net_dev->enetaddr);
#endif
if (err) {
printf("dpni_add_mac_addr() failed\n");
return err;
@ -651,34 +550,18 @@ err_dpmac_setup:
return err;
}
#ifdef CONFIG_DM_ETH
static void ldpaa_eth_stop(struct udevice *dev)
{
struct ldpaa_eth_priv *priv = dev_get_priv(dev);
#else
static void ldpaa_eth_stop(struct eth_device *net_dev)
{
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
#endif
struct phy_device *phydev = NULL;
int err = 0;
#ifdef CONFIG_DM_ETH
if (!eth_is_active(dev))
return;
#else
if ((net_dev->state == ETH_STATE_PASSIVE) ||
(net_dev->state == ETH_STATE_INIT))
return;
#endif
#ifdef DEBUG
ldpaa_eth_get_dpni_counter();
#ifdef CONFIG_DM_ETH
ldpaa_eth_get_dpmac_counter(dev);
#else
ldpaa_eth_get_dpmac_counter(net_dev);
#endif
#endif
err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS,
@ -702,7 +585,7 @@ static void ldpaa_eth_stop(struct eth_device *net_dev)
if (err < 0)
printf("dpni_disable() failed\n");
phydev = ldpaa_get_phydev(priv);
phydev = priv->phy;
if (phydev)
phy_shutdown(phydev);
@ -1097,7 +980,6 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv)
return 0;
}
#ifdef CONFIG_DM_ETH
static int ldpaa_eth_probe(struct udevice *dev)
{
struct ofnode_phandle_args phandle;
@ -1177,79 +1059,3 @@ U_BOOT_DRIVER(ldpaa_eth) = {
.priv_auto = sizeof(struct ldpaa_eth_priv),
.plat_auto = sizeof(struct eth_pdata),
};
#else
static int ldpaa_eth_netdev_init(struct eth_device *net_dev,
phy_interface_t enet_if)
{
int err;
struct ldpaa_eth_priv *priv = (struct ldpaa_eth_priv *)net_dev->priv;
snprintf(net_dev->name, ETH_NAME_LEN, "DPMAC%d@%s", priv->dpmac_id,
phy_interface_strings[enet_if]);
net_dev->iobase = 0;
net_dev->init = ldpaa_eth_open;
net_dev->halt = ldpaa_eth_stop;
net_dev->send = ldpaa_eth_tx;
net_dev->recv = ldpaa_eth_pull_dequeue_rx;
#ifdef CONFIG_PHYLIB
err = init_phy(net_dev);
if (err < 0)
return err;
#endif
err = eth_register(net_dev);
if (err < 0) {
printf("eth_register() = %d\n", err);
return err;
}
return 0;
}
int ldpaa_eth_init(int dpmac_id, phy_interface_t enet_if)
{
struct eth_device *net_dev = NULL;
struct ldpaa_eth_priv *priv = NULL;
int err = 0;
/* Net device */
net_dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!net_dev) {
printf("eth_device malloc() failed\n");
return -ENOMEM;
}
memset(net_dev, 0, sizeof(struct eth_device));
/* alloc the ldpaa ethernet private struct */
priv = (struct ldpaa_eth_priv *)malloc(sizeof(struct ldpaa_eth_priv));
if (!priv) {
printf("ldpaa_eth_priv malloc() failed\n");
free(net_dev);
return -ENOMEM;
}
memset(priv, 0, sizeof(struct ldpaa_eth_priv));
net_dev->priv = (void *)priv;
priv->net_dev = (struct eth_device *)net_dev;
priv->dpmac_id = dpmac_id;
debug("%s dpmac_id=%d\n", __func__, dpmac_id);
err = ldpaa_eth_netdev_init(net_dev, enet_if);
if (err)
goto err_netdev_init;
debug("ldpaa ethernet: Probed interface %s\n", net_dev->name);
return 0;
err_netdev_init:
free(priv);
net_dev->priv = NULL;
free(net_dev);
return err;
}
#endif

4
drivers/net/ldpaa_eth/ldpaa_eth.h
View File

@ -116,13 +116,9 @@ struct ldpaa_fas {
LDPAA_ETH_FAS_TIDE)
struct ldpaa_eth_priv {
#ifdef CONFIG_DM_ETH
struct phy_device *phy;
int phy_mode;
bool started;
#else
struct eth_device *net_dev;
#endif
uint32_t dpmac_id;
uint16_t dpmac_handle;

194
drivers/net/macb.c
View File

@ -33,9 +33,6 @@
*/
#include <net.h>
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif
#include <malloc.h>
#include <miiphy.h>
@ -131,21 +128,16 @@ struct macb_device {
unsigned long dummy_desc_dma;
const struct device *dev;
#ifndef CONFIG_DM_ETH
struct eth_device netdev;
#endif
unsigned short phy_addr;
struct mii_dev *bus;
#ifdef CONFIG_PHYLIB
struct phy_device *phydev;
#endif
#ifdef CONFIG_DM_ETH
#ifdef CONFIG_CLK
unsigned long pclk_rate;
#endif
phy_interface_t phy_interface;
#endif
};
struct macb_usrio_cfg {
@ -164,10 +156,6 @@ struct macb_config {
const struct macb_usrio_cfg *usrio;
};
#ifndef CONFIG_DM_ETH
#define to_macb(_nd) container_of(_nd, struct macb_device, netdev)
#endif
static int macb_is_gem(struct macb_device *macb)
{
return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) >= 0x2;
@ -258,13 +246,8 @@ void __weak arch_get_mdio_control(const char *name)
int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
{
u16 value = 0;
#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = to_macb(dev);
#endif
arch_get_mdio_control(bus->name);
value = macb_mdio_read(macb, phy_adr, reg);
@ -275,13 +258,8 @@ int macb_miiphy_read(struct mii_dev *bus, int phy_adr, int devad, int reg)
int macb_miiphy_write(struct mii_dev *bus, int phy_adr, int devad, int reg,
u16 value)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = dev_get_priv(dev);
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct macb_device *macb = to_macb(dev);
#endif
arch_get_mdio_control(bus->name);
macb_mdio_write(macb, phy_adr, reg, value);
@ -598,7 +576,6 @@ static int macb_phy_find(struct macb_device *macb, const char *name)
* Returns 0 when operation success and negative errno number
* when operation failed.
*/
#ifdef CONFIG_DM_ETH
static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
{
void *gemgxl_regs;
@ -678,22 +655,10 @@ int __weak macb_linkspd_cb(struct udevice *dev, unsigned int speed)
return 0;
}
#else
int __weak macb_linkspd_cb(void *regs, unsigned int speed)
{
return 0;
}
#endif
#ifdef CONFIG_DM_ETH
static int macb_phy_init(struct udevice *dev, const char *name)
#else
static int macb_phy_init(struct macb_device *macb, const char *name)
#endif
{
#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
#endif
u32 ncfgr;
u16 phy_id, status, adv, lpa;
int media, speed, duplex;
@ -714,14 +679,8 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
}
#ifdef CONFIG_PHYLIB
#ifdef CONFIG_DM_ETH
macb->phydev = phy_connect(macb->bus, macb->phy_addr, dev,
macb->phy_interface);
#else
/* need to consider other phy interface mode */
macb->phydev = phy_connect(macb->bus, macb->phy_addr, &macb->netdev,
PHY_INTERFACE_MODE_RGMII);
#endif
if (!macb->phydev) {
printf("phy_connect failed\n");
return -ENODEV;
@ -778,11 +737,7 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
macb_writel(macb, NCFGR, ncfgr);
#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _1000BASET);
#else
ret = macb_linkspd_cb(macb->regs, _1000BASET);
#endif
if (ret)
return ret;
@ -807,17 +762,9 @@ static int macb_phy_init(struct macb_device *macb, const char *name)
ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD) | GEM_BIT(GBE));
if (speed) {
ncfgr |= MACB_BIT(SPD);
#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _100BASET);
#else
ret = macb_linkspd_cb(macb->regs, _100BASET);
#endif
} else {
#ifdef CONFIG_DM_ETH
ret = macb_linkspd_cb(dev, _10BASET);
#else
ret = macb_linkspd_cb(macb->regs, _10BASET);
#endif
}
if (ret)
@ -891,16 +838,10 @@ static void gmac_configure_dma(struct macb_device *macb)
gem_writel(macb, DMACFG, dmacfg);
}
#ifdef CONFIG_DM_ETH
static int _macb_init(struct udevice *dev, const char *name)
#else
static int _macb_init(struct macb_device *macb, const char *name)
#endif
{
#ifdef CONFIG_DM_ETH
struct macb_device *macb = dev_get_priv(dev);
unsigned int val = 0;
#endif
unsigned long paddr;
int ret;
int i;
@ -969,7 +910,6 @@ static int _macb_init(struct macb_device *macb, const char *name)
* When the GMAC IP without GE feature, this bit is used
* to select interface between RMII and MII.
*/
#ifdef CONFIG_DM_ETH
if (macb->phy_interface == PHY_INTERFACE_MODE_RGMII ||
macb->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
macb->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID ||
@ -991,16 +931,8 @@ static int _macb_init(struct macb_device *macb, const char *name)
ncfgr |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
macb_writel(macb, NCFGR, ncfgr);
}
#else
#if defined(CONFIG_RGMII) || defined(CONFIG_RMII)
gem_writel(macb, USRIO, macb->config->usrio->rgmii);
#else
gem_writel(macb, USRIO, 0);
#endif
#endif
} else {
/* choose RMII or MII mode. This depends on the board */
#ifdef CONFIG_DM_ETH
#ifdef CONFIG_AT91FAMILY
if (macb->phy_interface == PHY_INTERFACE_MODE_RMII) {
macb_writel(macb, USRIO,
@ -1014,30 +946,10 @@ static int _macb_init(struct macb_device *macb, const char *name)
macb_writel(macb, USRIO, 0);
else
macb_writel(macb, USRIO, macb->config->usrio->mii);
#endif
#else
#ifdef CONFIG_RMII
#ifdef CONFIG_AT91FAMILY
macb_writel(macb, USRIO, macb->config->usrio->rmii |
macb->config->usrio->clken);
#else
macb_writel(macb, USRIO, 0);
#endif
#else
#ifdef CONFIG_AT91FAMILY
macb_writel(macb, USRIO, macb->config->usrio->clken);
#else
macb_writel(macb, USRIO, macb->config->usrio->mii);
#endif
#endif /* CONFIG_RMII */
#endif
}
#ifdef CONFIG_DM_ETH
ret = macb_phy_init(dev, name);
#else
ret = macb_phy_init(macb, name);
#endif
if (ret)
return ret;
@ -1081,7 +993,7 @@ static int _macb_write_hwaddr(struct macb_device *macb, unsigned char *enetaddr)
static u32 macb_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
#if defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
@ -1103,7 +1015,7 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb)
{
u32 config;
#if defined(CONFIG_DM_ETH) && defined(CONFIG_CLK)
#if defined(CONFIG_CLK)
unsigned long macb_hz = macb->pclk_rate;
#else
unsigned long macb_hz = get_macb_pclk_rate(id);
@ -1182,106 +1094,6 @@ static void _macb_eth_initialize(struct macb_device *macb)
macb_writel(macb, NCFGR, ncfgr);
}
#ifndef CONFIG_DM_ETH
static int macb_send(struct eth_device *netdev, void *packet, int length)
{
struct macb_device *macb = to_macb(netdev);
return _macb_send(macb, netdev->name, packet, length);
}
static int macb_recv(struct eth_device *netdev)
{
struct macb_device *macb = to_macb(netdev);
uchar *packet;
int length;
macb->wrapped = false;
for (;;) {
macb->next_rx_tail = macb->rx_tail;
length = _macb_recv(macb, &packet);
if (length >= 0) {
net_process_received_packet(packet, length);
reclaim_rx_buffers(macb, macb->next_rx_tail);
} else {
return length;
}
}
}
static int macb_init(struct eth_device *netdev, struct bd_info *bd)
{
struct macb_device *macb = to_macb(netdev);
return _macb_init(macb, netdev->name);
}
static void macb_halt(struct eth_device *netdev)
{
struct macb_device *macb = to_macb(netdev);
return _macb_halt(macb);
}
static int macb_write_hwaddr(struct eth_device *netdev)
{
struct macb_device *macb = to_macb(netdev);
return _macb_write_hwaddr(macb, netdev->enetaddr);
}
int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
{
struct macb_device *macb;
struct eth_device *netdev;
macb = malloc(sizeof(struct macb_device));
if (!macb) {
printf("Error: Failed to allocate memory for MACB%d\n", id);
return -1;
}
memset(macb, 0, sizeof(struct macb_device));
netdev = &macb->netdev;
macb->regs = regs;
macb->phy_addr = phy_addr;
if (macb_is_gem(macb))
sprintf(netdev->name, "gmac%d", id);
else
sprintf(netdev->name, "macb%d", id);
netdev->init = macb_init;
netdev->halt = macb_halt;
netdev->send = macb_send;
netdev->recv = macb_recv;
netdev->write_hwaddr = macb_write_hwaddr;
_macb_eth_initialize(macb);
eth_register(netdev);
#if defined(CONFIG_CMD_MII) || defined(CONFIG_PHYLIB)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strlcpy(mdiodev->name, netdev->name, MDIO_NAME_LEN);
mdiodev->read = macb_miiphy_read;
mdiodev->write = macb_miiphy_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
macb->bus = miiphy_get_dev_by_name(netdev->name);
#endif
return 0;
}
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_DM_ETH
static int macb_start(struct udevice *dev)
{
return _macb_init(dev, dev->name);
@ -1536,5 +1348,3 @@ U_BOOT_DRIVER(eth_macb) = {
.plat_auto = sizeof(struct eth_pdata),
};
#endif
#endif

16
drivers/net/mcfmii.c
View File

@ -85,11 +85,7 @@ void mii_reset(fec_info_t *info)
/* send command to phy using mii, wait for result */
uint mii_send(uint mii_cmd)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev;
#else
struct eth_device *dev;
#endif
fec_info_t *info;
volatile FEC_T *ep;
uint mii_reply;
@ -97,11 +93,7 @@ uint mii_send(uint mii_cmd)
/* retrieve from register structure */
dev = eth_get_dev();
#ifdef CONFIG_DM_ETH
info = dev_get_priv(dev);
#else
info = dev->priv;
#endif
ep = (FEC_T *) info->miibase;
@ -202,11 +194,7 @@ int mii_discover_phy(fec_info_t *info)
__weak void mii_init(void)
{
#ifdef CONFIG_DM_ETH
struct udevice *dev;
#else
struct eth_device *dev;
#endif
fec_info_t *info;
volatile FEC_T *fecp;
int miispd = 0, i = 0;
@ -215,11 +203,7 @@ __weak void mii_init(void)
/* retrieve from register structure */
dev = eth_get_dev();
#ifdef CONFIG_DM_ETH
info = dev_get_priv(dev);
#else
info = dev->priv;
#endif
fecp = (FEC_T *) info->miibase;

10
drivers/net/mscc_eswitch/Kconfig
View File

@ -4,35 +4,35 @@
config MSCC_OCELOT_SWITCH
bool "Ocelot switch driver"
depends on DM_ETH && ARCH_MSCC
depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Ocelot network switch device.
config MSCC_LUTON_SWITCH
bool "Luton switch driver"
depends on DM_ETH && ARCH_MSCC
depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Luton network switch device.
config MSCC_JR2_SWITCH
bool "Jaguar2 switch driver"
depends on DM_ETH && ARCH_MSCC
depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Jaguar2 network switch device.
config MSCC_SERVALT_SWITCH
bool "Servalt switch driver"
depends on DM_ETH && ARCH_MSCC
depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Servalt network switch device.
config MSCC_SERVAL_SWITCH
bool "Serval switch driver"
depends on DM_ETH && ARCH_MSCC
depends on ARCH_MSCC
select PHYLIB
help
This driver supports the Serval network switch device.

214
drivers/net/mvgbe.c
View File

@ -132,12 +132,7 @@ static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
int reg_ofs)
{
#ifdef CONFIG_DM_ETH
struct mvgbe_device *dmvgbe = bus->priv;
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
#endif
return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
}
@ -189,12 +184,7 @@ static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
int reg_ofs, u16 data)
{
#ifdef CONFIG_DM_ETH
struct mvgbe_device *dmvgbe = bus->priv;
#else
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
#endif
return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
}
@ -432,12 +422,6 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
const char *name)
{
struct mvgbe_registers *regs = dmvgbe->regs;
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
!defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
mvgbe_init_rx_desc_ring(dmvgbe);
@ -486,37 +470,9 @@ static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
/* Enable port Rx. */
MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
!defined(CONFIG_PHYLIB) && \
!defined(CONFIG_DM_ETH) && \
defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i < 5; i++) {
u16 phyadr;
miiphy_read(name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, &phyadr);
/* Return if we get link up */
if (miiphy_link(name, phyadr))
return 0;
udelay(1000000);
}
printf("No link on %s\n", name);
return -1;
#endif
return 0;
}
#ifndef CONFIG_DM_ETH
static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
}
#endif
static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
{
struct mvgbe_registers *regs = dmvgbe->regs;
@ -542,18 +498,6 @@ static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
MVGBE_REG_WR(regs->peim, 0);
}
#ifndef CONFIG_DM_ETH
static int mvgbe_halt(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
__mvgbe_halt(dmvgbe);
return 0;
}
#endif
#ifdef CONFIG_DM_ETH
static int mvgbe_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@ -562,16 +506,6 @@ static int mvgbe_write_hwaddr(struct udevice *dev)
return 0;
}
#else
static int mvgbe_write_hwaddr(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
/* Programs net device MAC address after initialization */
port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
return 0;
}
#endif
static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
int datasize)
@ -628,15 +562,6 @@ static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
return 0;
}
#ifndef CONFIG_DM_ETH
static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
return __mvgbe_send(dmvgbe, dataptr, datasize);
}
#endif
static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
{
struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
@ -710,35 +635,11 @@ static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
return rx_bytes;
}
#ifndef CONFIG_DM_ETH
static int mvgbe_recv(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
uchar *packet;
int ret;
ret = __mvgbe_recv(dmvgbe, &packet);
if (ret < 0)
return ret;
net_process_received_packet(packet, ret);
return 0;
}
#endif
#if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
#if defined(CONFIG_DM_ETH)
#if defined(CONFIG_PHYLIB)
static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
struct mii_dev *bus,
phy_interface_t phy_interface,
int phyid)
#else
static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
struct mii_dev *bus,
phy_interface_t phy_interface,
int phyid)
#endif
{
struct phy_device *phydev;
@ -760,38 +661,7 @@ static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
return phydev;
}
#endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
#if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
int mvgbe_phylib_init(struct eth_device *dev, int phyid)
{
struct mii_dev *bus;
struct phy_device *phydev;
int ret;
bus = mdio_alloc();
if (!bus) {
printf("mdio_alloc failed\n");
return -ENOMEM;
}
bus->read = smi_reg_read;
bus->write = smi_reg_write;
strcpy(bus->name, dev->name);
ret = mdio_register(bus);
if (ret) {
printf("mdio_register failed\n");
free(bus);
return -ENOMEM;
}
phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
if (!phydev)
return -ENODEV;
return 0;
}
#endif
#endif /* CONFIG_PHYLIB */
static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
{
@ -825,85 +695,6 @@ error1:
return -ENOMEM;
}
#ifndef CONFIG_DM_ETH
int mvgbe_initialize(struct bd_info *bis)
{
struct mvgbe_device *dmvgbe;
struct eth_device *dev;
int devnum;
int ret;
u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
/*skip if port is configured not to use */
if (used_ports[devnum] == 0)
continue;
dmvgbe = malloc(sizeof(struct mvgbe_device));
if (!dmvgbe)
return -ENOMEM;
memset(dmvgbe, 0, sizeof(struct mvgbe_device));
ret = mvgbe_alloc_buffers(dmvgbe);
if (ret) {
printf("Err.. %s Failed to allocate memory\n",
__func__);
free(dmvgbe);
return ret;
}
dev = &dmvgbe->dev;
/* must be less than sizeof(dev->name) */
sprintf(dev->name, "egiga%d", devnum);
switch (devnum) {
case 0:
dmvgbe->regs = (void *)MVGBE0_BASE;
break;
#if defined(MVGBE1_BASE)
case 1:
dmvgbe->regs = (void *)MVGBE1_BASE;
break;
#endif
default: /* this should never happen */
printf("Err..(%s) Invalid device number %d\n",
__func__, devnum);
return -1;
}
dev->init = (void *)mvgbe_init;
dev->halt = (void *)mvgbe_halt;
dev->send = (void *)mvgbe_send;
dev->recv = (void *)mvgbe_recv;
dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
eth_register(dev);
#if defined(CONFIG_PHYLIB)
mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
int retval;
struct mii_dev *mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = smi_reg_read;
mdiodev->write = smi_reg_write;
retval = mdio_register(mdiodev);
if (retval < 0)
return retval;
/* Set phy address of the port */
miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
#endif
}
return 0;
}
#endif
#ifdef CONFIG_DM_ETH
static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
{
return dmvgbe->phyaddr > PHY_MAX_ADDR;
@ -1046,4 +837,3 @@ U_BOOT_DRIVER(mvgbe) = {
.priv_auto = sizeof(struct mvgbe_device),
.plat_auto = sizeof(struct eth_pdata),
};
#endif /* CONFIG_DM_ETH */

8
drivers/net/mvgbe.h
View File

@ -30,9 +30,6 @@
#define RXUQ 0 /* Used Rx queue */
#define TXUQ 0 /* Used Rx queue */
#ifndef CONFIG_DM_ETH
#define to_mvgbe(_d) container_of(_d, struct mvgbe_device, dev)
#endif
#define MVGBE_REG_WR(adr, val) writel(val, &adr)
#define MVGBE_REG_RD(adr) readl(&adr)
#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
@ -481,9 +478,6 @@ struct mvgbe_txdesc {
/* port device data struct */
struct mvgbe_device {
#ifndef CONFIG_DM_ETH
struct eth_device dev;
#endif
struct mvgbe_registers *regs;
struct mvgbe_txdesc *p_txdesc;
struct mvgbe_rxdesc *p_rxdesc;
@ -491,7 +485,6 @@ struct mvgbe_device {
u8 *p_rxbuf;
u8 *p_aligned_txbuf;
#ifdef CONFIG_DM_ETH
phy_interface_t phy_interface;
unsigned int link;
unsigned int duplex;
@ -501,7 +494,6 @@ struct mvgbe_device {
int phyaddr;
struct phy_device *phydev;
struct mii_dev *bus;
#endif
};
#endif /* __MVGBE_H__ */

8
drivers/net/netconsole.c
View File

@ -172,11 +172,7 @@ int nc_input_packet(uchar *pkt, struct in_addr src_ip, unsigned dest_port,
static void nc_send_packet(const char *buf, int len)
{
#ifdef CONFIG_DM_ETH
struct udevice *eth;
#else
struct eth_device *eth;
#endif
int inited = 0;
uchar *pkt;
uchar *ether;
@ -298,11 +294,7 @@ static int nc_stdio_getc(struct stdio_dev *dev)
static int nc_stdio_tstc(struct stdio_dev *dev)
{
#ifdef CONFIG_DM_ETH
struct udevice *eth;
#else
struct eth_device *eth;
#endif
if (input_recursion)
return 0;

136
drivers/net/pcnet.c
View File

@ -83,13 +83,8 @@ struct pcnet_priv {
/* Receive Buffer space */
unsigned char rx_buf[RX_RING_SIZE][PKT_BUF_SZ + 4];
struct pcnet_uncached_priv *uc;
#ifdef CONFIG_DM_ETH
struct udevice *dev;
const char *name;
#else
pci_dev_t dev;
char *name;
#endif
void __iomem *iobase;
u8 *enetaddr;
u16 status;
@ -142,11 +137,7 @@ static inline pci_addr_t pcnet_virt_to_mem(struct pcnet_priv *lp, void *addr)
{
void *virt_addr = addr;
#ifdef CONFIG_DM_ETH
return dm_pci_virt_to_mem(lp->dev, virt_addr);
#else
return pci_virt_to_mem(lp->dev, virt_addr);
#endif
}
static struct pci_device_id supported[] = {
@ -457,132 +448,6 @@ static void pcnet_halt_common(struct pcnet_priv *lp)
printf("%s: TIMEOUT: controller reset failed\n", lp->name);
}
#ifndef CONFIG_DM_ETH
static int pcnet_init(struct eth_device *dev, struct bd_info *bis)
{
struct pcnet_priv *lp = dev->priv;
return pcnet_init_common(lp);
}
static int pcnet_send(struct eth_device *dev, void *packet, int pkt_len)
{
struct pcnet_priv *lp = dev->priv;
return pcnet_send_common(lp, packet, pkt_len);
}
static int pcnet_recv(struct eth_device *dev)
{
struct pcnet_priv *lp = dev->priv;
uchar *packet;
int ret;
ret = pcnet_recv_common(lp, &packet);
if (ret > 0)
net_process_received_packet(packet, ret);
if (ret)
pcnet_free_pkt_common(lp, ret);
return ret;
}
static void pcnet_halt(struct eth_device *dev)
{
struct pcnet_priv *lp = dev->priv;
pcnet_halt_common(lp);
}
int pcnet_initialize(struct bd_info *bis)
{
pci_dev_t devbusfn;
struct eth_device *dev;
struct pcnet_priv *lp;
u16 command, status;
int dev_nr = 0;
u32 bar;
PCNET_DEBUG1("\n%s...\n", __func__);
for (dev_nr = 0; ; dev_nr++) {
/*
* Find the PCnet PCI device(s).
*/
devbusfn = pci_find_devices(supported, dev_nr);
if (devbusfn < 0)
break;
/*
* Allocate and pre-fill the device structure.
*/
dev = calloc(1, sizeof(*dev));
if (!dev) {
printf("pcnet: Can not allocate memory\n");
break;
}
/*
* We only maintain one structure because the drivers will
* never be used concurrently. In 32bit mode the RX and TX
* ring entries must be aligned on 16-byte boundaries.
*/
lp = malloc_cache_aligned(sizeof(*lp));
lp->uc = map_physmem((phys_addr_t)&lp->ucp,
sizeof(lp->ucp), MAP_NOCACHE);
lp->dev = devbusfn;
flush_dcache_range((unsigned long)lp,
(unsigned long)lp + sizeof(*lp));
dev->priv = lp;
sprintf(dev->name, "pcnet#%d", dev_nr);
lp->name = dev->name;
lp->enetaddr = dev->enetaddr;
/*
* Setup the PCI device.
*/
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &bar);
lp->iobase = (void *)(pci_mem_to_phys(devbusfn, bar) & ~0xf);
PCNET_DEBUG1("%s: devbusfn=0x%x iobase=0x%p: ",
lp->name, devbusfn, lp->iobase);
command = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(devbusfn, PCI_COMMAND, command);
pci_read_config_word(devbusfn, PCI_COMMAND, &status);
if ((status & command) != command) {
printf("%s: Couldn't enable IO access or Bus Mastering\n",
lp->name);
free(dev);
continue;
}
pci_write_config_byte(devbusfn, PCI_LATENCY_TIMER, 0x40);
/*
* Probe the PCnet chip.
*/
if (pcnet_probe_common(lp) < 0) {
free(dev);
continue;
}
/*
* Setup device structure and register the driver.
*/
dev->init = pcnet_init;
dev->halt = pcnet_halt;
dev->send = pcnet_send;
dev->recv = pcnet_recv;
eth_register(dev);
}
udelay(10 * 1000);
return dev_nr;
}
#else /* DM_ETH */
static int pcnet_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -695,4 +560,3 @@ U_BOOT_DRIVER(eth_pcnet) = {
};
U_BOOT_PCI_DEVICE(eth_pcnet, supported);
#endif

3
drivers/net/phy/Kconfig
View File

@ -315,7 +315,6 @@ config PHY_XILINX
config PHY_XILINX_GMII2RGMII
bool "Xilinx GMII to RGMII Ethernet PHYs support"
depends on DM_ETH
help
This adds support for Xilinx GMII to RGMII IP core. This IP acts
as bridge between MAC connected over GMII and external phy that
@ -336,7 +335,6 @@ config PHY_ETHERNET_ID
config PHY_FIXED
bool "Fixed-Link PHY"
depends on DM_ETH
help
Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
connection (MII, RGMII, ...).
@ -346,7 +344,6 @@ config PHY_FIXED
config PHY_NCSI
bool "NC-SI based PHY"
depends on DM_ETH
endif #PHYLIB

2
drivers/net/phy/aquantia.c
View File

@ -338,7 +338,6 @@ static int aquantia_set_proto(struct phy_device *phydev,
static int aquantia_dts_config(struct phy_device *phydev)
{
#ifdef CONFIG_DM_ETH
ofnode node = phydev->node;
u32 prop;
u16 reg;
@ -374,7 +373,6 @@ static int aquantia_dts_config(struct phy_device *phydev)
(u16)(prop << 1));
}
#endif
return 0;
}

2
drivers/net/phy/atheros.c
View File

@ -191,7 +191,6 @@ static int ar803x_regs_config(struct phy_device *phydev)
static int ar803x_of_init(struct phy_device *phydev)
{
#if defined(CONFIG_DM_ETH)
struct ar803x_priv *priv;
ofnode node, vddio_reg_node;
u32 strength, freq, min_uV, max_uV;
@ -306,7 +305,6 @@ static int ar803x_of_init(struct phy_device *phydev)
debug("%s: flags=%x clk_25m_reg=%04x clk_25m_mask=%04x\n", __func__,
priv->flags, priv->clk_25m_reg, priv->clk_25m_mask);
#endif
return 0;
}

14
drivers/net/phy/dp83867.c
View File

@ -144,7 +144,6 @@ static int dp83867_config_port_mirroring(struct phy_device *phydev)
return 0;
}
#if defined(CONFIG_DM_ETH)
/**
* dp83867_data_init - Convenience function for setting PHY specific data
*
@ -249,19 +248,6 @@ static int dp83867_of_init(struct phy_device *phydev)
return 0;
}
#else
static int dp83867_of_init(struct phy_device *phydev)
{
struct dp83867_private *dp83867 = phydev->priv;
dp83867->rx_id_delay = DP83867_RGMIIDCTL_2_25_NS;
dp83867->tx_id_delay = DP83867_RGMIIDCTL_2_75_NS;
dp83867->fifo_depth = DEFAULT_FIFO_DEPTH;
dp83867->io_impedance = -EINVAL;
return 0;
}
#endif
static int dp83867_config(struct phy_device *phydev)
{

14
drivers/net/phy/dp83869.c
View File

@ -157,7 +157,6 @@ static int dp83869_config_port_mirroring(struct phy_device *phydev)
return 0;
}
#ifdef CONFIG_DM_ETH
static const int dp83869_internal_delay[] = {250, 500, 750, 1000, 1250, 1500,
1750, 2000, 2250, 2500, 2750, 3000,
3250, 3500, 3750, 4000};
@ -269,19 +268,6 @@ static int dp83869_of_init(struct phy_device *phydev)
return 0;
}
#else
static int dp83869_of_init(struct phy_device *phydev)
{
struct dp83869_private *dp83869 = phydev->priv;
dp83869->rx_int_delay = DP83869_RGMIIDCTL_2_25_NS;
dp83869->tx_int_delay = DP83869_RGMIIDCTL_2_75_NS;
dp83869->fifo_depth = DEFAULT_FIFO_DEPTH;
dp83869->io_impedance = -EINVAL;
return 0;
}
#endif /* CONFIG_OF_MDIO */
static int dp83869_configure_rgmii(struct phy_device *phydev,
struct dp83869_private *dp83869)

7
drivers/net/phy/marvell.c
View File

@ -104,7 +104,6 @@
#define MIIM_88E151x_MODE_SGMII 1
#define MIIM_88E151x_RESET_OFFS 15
#if IS_ENABLED(CONFIG_DM_ETH)
static int marvell_read_page(struct phy_device *phydev)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE);
@ -179,12 +178,6 @@ static int marvell_of_reg_init(struct phy_device *phydev)
err:
return marvell_write_page(phydev, saved_page);
}
#else
static int marvell_of_reg_init(struct phy_device *phydev)
{
return 0;
}
#endif /* CONFIG_DM_ETH */
static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr,
int devaddr, int regnum)

18
drivers/net/phy/micrel_ksz90x1.c
View File

@ -68,7 +68,6 @@ static int ksz90xx_startup(struct phy_device *phydev)
}
/* Common OF config bits for KSZ9021 and KSZ9031 */
#ifdef CONFIG_DM_ETH
struct ksz90x1_reg_field {
const char *name;
const u8 size; /* Size of the bitfield, in bits */
@ -211,23 +210,6 @@ static int ksz9031_center_flp_timing(struct phy_device *phydev)
return ret;
}
#else /* !CONFIG_DM_ETH */
static int ksz9021_of_config(struct phy_device *phydev)
{
return 0;
}
static int ksz9031_of_config(struct phy_device *phydev)
{
return 0;
}
static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
return 0;
}
#endif
/*
* KSZ9021
*/

13
drivers/net/phy/phy.c
View File

@ -689,9 +689,7 @@ struct phy_device *phy_device_create(struct mii_dev *bus, int addr,
dev->link = 0;
dev->interface = PHY_INTERFACE_MODE_NA;
#ifdef CONFIG_DM_ETH
dev->node = ofnode_null();
#endif
dev->autoneg = AUTONEG_ENABLE;
@ -922,13 +920,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask)
return get_phy_device_by_mask(bus, phy_mask);
}
#ifdef CONFIG_DM_ETH
void phy_connect_dev(struct phy_device *phydev, struct udevice *dev,
phy_interface_t interface)
#else
void phy_connect_dev(struct phy_device *phydev, struct eth_device *dev,
phy_interface_t interface)
#endif
{
/* Soft Reset the PHY */
phy_reset(phydev);
@ -1011,15 +1004,9 @@ static struct phy_device *phy_connect_fixed(struct mii_dev *bus,
}
#endif
#ifdef CONFIG_DM_ETH
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct udevice *dev,
phy_interface_t interface)
#else
struct phy_device *phy_connect(struct mii_dev *bus, int addr,
struct eth_device *dev,
phy_interface_t interface)
#endif
{
struct phy_device *phydev = NULL;
uint mask = (addr >= 0) ? (1 << addr) : 0xffffffff;

1
drivers/net/qe/Kconfig
View File

@ -4,6 +4,5 @@
config QE_UEC
bool "NXP QE UEC Ethernet controller"
depends on DM_ETH
help
This driver supports the NXP QE UEC ethernet controller

112
drivers/net/rtl8139.c
View File

@ -97,13 +97,8 @@
#define DEBUG_TX 0 /* set to 1 to enable debug code */
#define DEBUG_RX 0 /* set to 1 to enable debug code */
#ifdef CONFIG_DM_ETH
#define bus_to_phys(devno, a) dm_pci_mem_to_phys((devno), (a))
#define phys_to_bus(devno, a) dm_pci_phys_to_mem((devno), (a))
#else
#define bus_to_phys(devno, a) pci_mem_to_phys((pci_dev_t)(devno), (a))
#define phys_to_bus(devno, a) pci_phys_to_mem((pci_dev_t)(devno), (a))
#endif
/* Symbolic offsets to registers. */
/* Ethernet hardware address. */
@ -198,12 +193,7 @@
#define RTL_STS_RXSTATUSOK BIT(0)
struct rtl8139_priv {
#ifndef CONFIG_DM_ETH
struct eth_device dev;
pci_dev_t devno;
#else
struct udevice *devno;
#endif
unsigned int rxstatus;
unsigned int cur_rx;
unsigned int cur_tx;
@ -557,107 +547,6 @@ static struct pci_device_id supported[] = {
{ }
};
#ifndef CONFIG_DM_ETH
static int rtl8139_bcast_addr(struct eth_device *dev, const u8 *bcast_mac,
int join)
{
return 0;
}
static int rtl8139_init(struct eth_device *dev, struct bd_info *bis)
{
struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
return rtl8139_init_common(priv);
}
static void rtl8139_stop(struct eth_device *dev)
{
struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
return rtl8139_stop_common(priv);
}
static int rtl8139_send(struct eth_device *dev, void *packet, int length)
{
struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
return rtl8139_send_common(priv, packet, length);
}
static int rtl8139_recv(struct eth_device *dev)
{
struct rtl8139_priv *priv = container_of(dev, struct rtl8139_priv, dev);
unsigned char rxdata[RX_BUF_LEN];
uchar *packet;
int ret;
ret = rtl8139_recv_common(priv, rxdata, &packet);
if (ret) {
net_process_received_packet(packet, ret);
rtl8139_free_pkt_common(priv, ret);
}
return ret;
}
int rtl8139_initialize(struct bd_info *bis)
{
struct rtl8139_priv *priv;
struct eth_device *dev;
int card_number = 0;
pci_dev_t devno;
int idx = 0;
u32 iobase;
while (1) {
/* Find RTL8139 */
devno = pci_find_devices(supported, idx++);
if (devno < 0)
break;
pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
iobase &= ~0xf;
debug("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
priv = calloc(1, sizeof(*priv));
if (!priv) {
printf("Can not allocate memory of rtl8139\n");
break;
}
priv->devno = devno;
priv->ioaddr = (unsigned long)bus_to_phys(devno, iobase);
dev = &priv->dev;
rtl8139_name(dev->name, card_number);
dev->iobase = priv->ioaddr; /* Non-DM compatibility */
dev->init = rtl8139_init;
dev->halt = rtl8139_stop;
dev->send = rtl8139_send;
dev->recv = rtl8139_recv;
dev->mcast = rtl8139_bcast_addr;
rtl8139_get_hwaddr(priv);
/* Non-DM compatibility */
memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
eth_register(dev);
card_number++;
pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x20);
udelay(10 * 1000);
}
return card_number;
}
#else /* DM_ETH */
static int rtl8139_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -776,4 +665,3 @@ U_BOOT_DRIVER(eth_rtl8139) = {
};
U_BOOT_PCI_DEVICE(eth_rtl8139, supported);
#endif

166
drivers/net/rtl8169.c
View File

@ -47,9 +47,6 @@
#include <malloc.h>
#include <memalign.h>
#include <net.h>
#ifndef CONFIG_DM_ETH
#include <netdev.h>
#endif
#include <asm/cache.h>
#include <asm/io.h>
#include <pci.h>
@ -514,13 +511,8 @@ static void rtl_flush_buffer(void *buf, size_t size)
/**************************************************************************
RECV - Receive a frame
***************************************************************************/
#ifdef CONFIG_DM_ETH
static int rtl_recv_common(struct udevice *dev, unsigned long dev_iobase,
uchar **packetp)
#else
static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
uchar **packetp)
#endif
{
/* return true if there's an ethernet packet ready to read */
/* nic->packet should contain data on return */
@ -551,22 +543,12 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
else
tpc->RxDescArray[cur_rx].status =
cpu_to_le32(OWNbit + RX_BUF_SIZE);
#ifdef CONFIG_DM_ETH
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#else
tpc->RxDescArray[cur_rx].buf_addr = cpu_to_le32(
pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)
tpc->RxBufferRing[cur_rx]));
#endif
rtl_flush_rx_desc(&tpc->RxDescArray[cur_rx]);
#ifdef CONFIG_DM_ETH
*packetp = rxdata;
#else
net_process_received_packet(rxdata, length);
#endif
} else {
puts("Error Rx");
length = -EIO;
@ -584,32 +566,19 @@ static int rtl_recv_common(pci_dev_t dev, unsigned long dev_iobase,
return (0); /* initially as this is called to flush the input */
}
#ifdef CONFIG_DM_ETH
int rtl8169_eth_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct rtl8169_private *priv = dev_get_priv(dev);
return rtl_recv_common(dev, priv->iobase, packetp);
}
#else
static int rtl_recv(struct eth_device *dev)
{
return rtl_recv_common((pci_dev_t)(unsigned long)dev->priv,
dev->iobase, NULL);
}
#endif /* nCONFIG_DM_ETH */
#define HZ 1000
/**************************************************************************
SEND - Transmit a frame
***************************************************************************/
#ifdef CONFIG_DM_ETH
static int rtl_send_common(struct udevice *dev, unsigned long dev_iobase,
void *packet, int length)
#else
static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
void *packet, int length)
#endif
{
/* send the packet to destination */
@ -637,13 +606,8 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
rtl_flush_buffer(ptxb, ALIGN(len, RTL8169_ALIGN));
tpc->TxDescArray[entry].buf_Haddr = 0;
#ifdef CONFIG_DM_ETH
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
dm_pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
#else
tpc->TxDescArray[entry].buf_addr = cpu_to_le32(
pci_mem_to_phys(dev, (pci_addr_t)(unsigned long)ptxb));
#endif
if (entry != (NUM_TX_DESC - 1)) {
tpc->TxDescArray[entry].status =
cpu_to_le32((OWNbit | FSbit | LSbit) |
@ -680,7 +644,6 @@ static int rtl_send_common(pci_dev_t dev, unsigned long dev_iobase,
return ret;
}
#ifdef CONFIG_DM_ETH
int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
{
struct rtl8169_private *priv = dev_get_priv(dev);
@ -688,14 +651,6 @@ int rtl8169_eth_send(struct udevice *dev, void *packet, int length)
return rtl_send_common(dev, priv->iobase, packet, length);
}
#else
static int rtl_send(struct eth_device *dev, void *packet, int length)
{
return rtl_send_common((pci_dev_t)(unsigned long)dev->priv,
dev->iobase, packet, length);
}
#endif
static void rtl8169_set_rx_mode(void)
{
u32 mc_filter[2]; /* Multicast hash filter */
@ -719,11 +674,7 @@ static void rtl8169_set_rx_mode(void)
RTL_W32(MAR0 + 4, mc_filter[1]);
}
#ifdef CONFIG_DM_ETH
static void rtl8169_hw_start(struct udevice *dev)
#else
static void rtl8169_hw_start(pci_dev_t dev)
#endif
{
u32 i;
@ -768,21 +719,11 @@ static void rtl8169_hw_start(pci_dev_t dev)
tpc->cur_rx = 0;
#ifdef CONFIG_DM_ETH
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#else
RTL_W32(TxDescStartAddrLow, pci_mem_to_phys(dev,
(pci_addr_t)(unsigned long)tpc->TxDescArray));
#endif
RTL_W32(TxDescStartAddrHigh, (unsigned long)0);
#ifdef CONFIG_DM_ETH
RTL_W32(RxDescStartAddrLow, dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#else
RTL_W32(RxDescStartAddrLow, pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxDescArray));
#endif
RTL_W32(RxDescStartAddrHigh, (unsigned long)0);
/* RTL-8169sc/8110sc or later version */
@ -804,11 +745,7 @@ static void rtl8169_hw_start(pci_dev_t dev)
#endif
}
#ifdef CONFIG_DM_ETH
static void rtl8169_init_ring(struct udevice *dev)
#else
static void rtl8169_init_ring(pci_dev_t dev)
#endif
{
int i;
@ -836,13 +773,8 @@ static void rtl8169_init_ring(pci_dev_t dev)
cpu_to_le32(OWNbit + RX_BUF_SIZE);
tpc->RxBufferRing[i] = &rxb[i * RX_BUF_SIZE];
#ifdef CONFIG_DM_ETH
tpc->RxDescArray[i].buf_addr = cpu_to_le32(dm_pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
#else
tpc->RxDescArray[i].buf_addr = cpu_to_le32(pci_mem_to_phys(
dev, (pci_addr_t)(unsigned long)tpc->RxBufferRing[i]));
#endif
rtl_flush_rx_desc(&tpc->RxDescArray[i]);
}
@ -851,13 +783,8 @@ static void rtl8169_init_ring(pci_dev_t dev)
#endif
}
#ifdef CONFIG_DM_ETH
static void rtl8169_common_start(struct udevice *dev, unsigned char *enetaddr,
unsigned long dev_iobase)
#else
static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
unsigned long dev_iobase)
#endif
{
int i;
@ -887,7 +814,6 @@ static void rtl8169_common_start(pci_dev_t dev, unsigned char *enetaddr,
#endif
}
#ifdef CONFIG_DM_ETH
static int rtl8169_eth_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -897,18 +823,6 @@ static int rtl8169_eth_start(struct udevice *dev)
return 0;
}
#else
/**************************************************************************
RESET - Finish setting up the ethernet interface
***************************************************************************/
static int rtl_reset(struct eth_device *dev, struct bd_info *bis)
{
rtl8169_common_start((pci_dev_t)(unsigned long)dev->priv,
dev->enetaddr, dev->iobase);
return 0;
}
#endif /* nCONFIG_DM_ETH */
static void rtl_halt_common(unsigned long dev_iobase)
{
@ -933,24 +847,13 @@ static void rtl_halt_common(unsigned long dev_iobase)
}
}
#ifdef CONFIG_DM_ETH
void rtl8169_eth_stop(struct udevice *dev)
{
struct rtl8169_private *priv = dev_get_priv(dev);
rtl_halt_common(priv->iobase);
}
#else
/**************************************************************************
HALT - Turn off ethernet interface
***************************************************************************/
static void rtl_halt(struct eth_device *dev)
{
rtl_halt_common(dev->iobase);
}
#endif
#ifdef CONFIG_DM_ETH
static int rtl8169_write_hwaddr(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -965,7 +868,6 @@ static int rtl8169_write_hwaddr(struct udevice *dev)
return 0;
}
#endif
/**************************************************************************
INIT - Look for an adapter, this routine's visible to the outside
@ -1118,73 +1020,6 @@ static int rtl_init(unsigned long dev_ioaddr, const char *name,
return 0;
}
#ifndef CONFIG_DM_ETH
int rtl8169_initialize(struct bd_info *bis)
{
pci_dev_t devno;
int card_number = 0;
struct eth_device *dev;
u32 iobase;
int idx=0;
while(1){
unsigned int region;
u16 device;
int err;
/* Find RTL8169 */
if ((devno = pci_find_devices(supported, idx++)) < 0)
break;
pci_read_config_word(devno, PCI_DEVICE_ID, &device);
switch (device) {
case 0x8168:
region = 2;
break;
default:
region = 1;
break;
}
pci_read_config_dword(devno, PCI_BASE_ADDRESS_0 + (region * 4), &iobase);
iobase &= ~0xf;
debug ("rtl8169: REALTEK RTL8169 @0x%x\n", iobase);
dev = (struct eth_device *)malloc(sizeof *dev);
if (!dev) {
printf("Can not allocate memory of rtl8169\n");
break;
}
memset(dev, 0, sizeof(*dev));
sprintf (dev->name, "RTL8169#%d", card_number);
dev->priv = (void *)(unsigned long)devno;
dev->iobase = (int)pci_mem_to_phys(devno, iobase);
dev->init = rtl_reset;
dev->halt = rtl_halt;
dev->send = rtl_send;
dev->recv = rtl_recv;
err = rtl_init(dev->iobase, dev->name, dev->enetaddr);
if (err < 0) {
printf(pr_fmt("failed to initialize card: %d\n"), err);
free(dev);
continue;
}
eth_register (dev);
card_number++;
}
return card_number;
}
#endif
#ifdef CONFIG_DM_ETH
static int rtl8169_eth_probe(struct udevice *dev)
{
struct pci_child_plat *pplat = dev_get_parent_plat(dev);
@ -1253,4 +1088,3 @@ U_BOOT_DRIVER(eth_rtl8169) = {
};
U_BOOT_PCI_DEVICE(eth_rtl8169, supported);
#endif

160
drivers/net/sh_eth.c
View File

@ -23,12 +23,10 @@
#include <asm/global_data.h>
#include <asm/io.h>
#ifdef CONFIG_DM_ETH
#include <clk.h>
#include <dm.h>
#include <linux/mii.h>
#include <asm/gpio.h>
#endif
#include "sh_eth.h"
@ -526,163 +524,6 @@ static int sh_eth_start_common(struct sh_eth_dev *eth)
return 0;
}
#ifndef CONFIG_DM_ETH
static int sh_eth_phy_config_legacy(struct sh_eth_dev *eth)
{
int ret = 0;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
struct eth_device *dev = port_info->dev;
struct phy_device *phydev;
phydev = phy_connect(
miiphy_get_dev_by_name(dev->name),
port_info->phy_addr, dev, CONFIG_SH_ETHER_PHY_MODE);
port_info->phydev = phydev;
phy_config(phydev);
return ret;
}
static int sh_eth_send_legacy(struct eth_device *dev, void *packet, int len)
{
struct sh_eth_dev *eth = dev->priv;
return sh_eth_send_common(eth, packet, len);
}
static int sh_eth_recv_common(struct sh_eth_dev *eth)
{
int len = 0;
struct sh_eth_info *port_info = &eth->port_info[eth->port];
uchar *packet = (uchar *)ADDR_TO_P2(port_info->rx_desc_cur->rd2);
len = sh_eth_recv_start(eth);
if (len > 0) {
invalidate_cache(packet, len);
net_process_received_packet(packet, len);
sh_eth_recv_finish(eth);
} else
len = 0;
/* Restart the receiver if disabled */
if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R))
sh_eth_write(port_info, EDRRR_R, EDRRR);
return len;
}
static int sh_eth_recv_legacy(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
return sh_eth_recv_common(eth);
}
static int sh_eth_init_legacy(struct eth_device *dev, struct bd_info *bd)
{
struct sh_eth_dev *eth = dev->priv;
int ret;
ret = sh_eth_init_common(eth, dev->enetaddr);
if (ret)
return ret;
ret = sh_eth_phy_config_legacy(eth);
if (ret) {
printf(SHETHER_NAME ": phy config timeout\n");
goto err_start;
}
ret = sh_eth_start_common(eth);
if (ret)
goto err_start;
return 0;
err_start:
sh_eth_tx_desc_free(eth);
sh_eth_rx_desc_free(eth);
return ret;
}
void sh_eth_halt_legacy(struct eth_device *dev)
{
struct sh_eth_dev *eth = dev->priv;
sh_eth_stop(eth);
}
int sh_eth_initialize(struct bd_info *bd)
{
int ret = 0;
struct sh_eth_dev *eth = NULL;
struct eth_device *dev = NULL;
struct mii_dev *mdiodev;
eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
memset(dev, 0, sizeof(struct eth_device));
memset(eth, 0, sizeof(struct sh_eth_dev));
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
eth->port_info[eth->port].iobase =
(void __iomem *)(BASE_IO_ADDR + 0x800 * eth->port);
dev->priv = (void *)eth;
dev->iobase = 0;
dev->init = sh_eth_init_legacy;
dev->halt = sh_eth_halt_legacy;
dev->send = sh_eth_send_legacy;
dev->recv = sh_eth_recv_legacy;
eth->port_info[eth->port].dev = dev;
strcpy(dev->name, SHETHER_NAME);
/* Register Device to EtherNet subsystem */
eth_register(dev);
bb_miiphy_buses[0].priv = eth;
mdiodev = mdio_alloc();
if (!mdiodev)
return -ENOMEM;
strlcpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
mdiodev->read = bb_miiphy_read;
mdiodev->write = bb_miiphy_write;
ret = mdio_register(mdiodev);
if (ret < 0)
return ret;
if (!eth_env_get_enetaddr("ethaddr", dev->enetaddr))
puts("Please set MAC address\n");
return ret;
err:
if (dev)
free(dev);
if (eth)
free(eth);
printf(SHETHER_NAME ": Failed\n");
return ret;
}
#else /* CONFIG_DM_ETH */
struct sh_ether_priv {
struct sh_eth_dev shdev;
@ -955,7 +796,6 @@ U_BOOT_DRIVER(eth_sh_ether) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif
/******* for bb_miiphy *******/
static int sh_eth_bb_init(struct bb_miiphy_bus *bus)

147
drivers/net/smc911x.c
View File

@ -22,9 +22,6 @@ struct chip_id {
};
struct smc911x_priv {
#ifndef CONFIG_DM_ETH
struct eth_device dev;
#endif
phys_addr_t iobase;
const struct chip_id *chipid;
unsigned char enetaddr[6];
@ -382,149 +379,6 @@ static int smc911x_recv_common(struct smc911x_priv *priv, u32 *data)
return pktlen;
}
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/* wrapper for smc911x_eth_phy_read */
static int smc911x_miiphy_read(struct mii_dev *bus, int phy, int devad,
int reg)
{
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
u16 val = 0;
int ret;
if (!dev || !priv)
return -ENODEV;
ret = smc911x_eth_phy_read(priv, phy, reg, &val);
if (ret < 0)
return ret;
return val;
}
/* wrapper for smc911x_eth_phy_write */
static int smc911x_miiphy_write(struct mii_dev *bus, int phy, int devad,
int reg, u16 val)
{
struct eth_device *dev = eth_get_dev_by_name(bus->name);
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
if (!dev || !priv)
return -ENODEV;
return smc911x_eth_phy_write(priv, phy, reg, val);
}
static int smc911x_initialize_mii(struct smc911x_priv *priv)
{
struct mii_dev *mdiodev = mdio_alloc();
int ret;
if (!mdiodev)
return -ENOMEM;
strlcpy(mdiodev->name, priv->dev.name, MDIO_NAME_LEN);
mdiodev->read = smc911x_miiphy_read;
mdiodev->write = smc911x_miiphy_write;
ret = mdio_register(mdiodev);
if (ret < 0) {
mdio_free(mdiodev);
return ret;
}
return 0;
}
#else
static int smc911x_initialize_mii(struct smc911x_priv *priv)
{
return 0;
}
#endif
static int smc911x_init(struct eth_device *dev, struct bd_info *bd)
{
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
return smc911x_init_common(priv);
}
static void smc911x_halt(struct eth_device *dev)
{
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
smc911x_halt_common(priv);
}
static int smc911x_send(struct eth_device *dev, void *packet, int length)
{
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
return smc911x_send_common(priv, packet, length);
}
static int smc911x_recv(struct eth_device *dev)
{
struct smc911x_priv *priv = container_of(dev, struct smc911x_priv, dev);
u32 *data = (u32 *)net_rx_packets[0];
int ret;
ret = smc911x_recv_common(priv, data);
if (ret)
net_process_received_packet(net_rx_packets[0], ret);
return ret;
}
int smc911x_initialize(u8 dev_num, phys_addr_t base_addr)
{
struct smc911x_priv *priv;
int ret;
priv = calloc(1, sizeof(*priv));
if (!priv)
return -ENOMEM;
priv->iobase = base_addr;
priv->dev.iobase = base_addr;
priv->use_32_bit_io = CONFIG_IS_ENABLED(SMC911X_32_BIT);
/* Try to detect chip. Will fail if not present. */
ret = smc911x_detect_chip(priv);
if (ret) {
ret = 0; /* Card not detected is not an error */
goto err_detect;
}
if (smc911x_read_mac_address(priv))
memcpy(priv->dev.enetaddr, priv->enetaddr, 6);
priv->dev.init = smc911x_init;
priv->dev.halt = smc911x_halt;
priv->dev.send = smc911x_send;
priv->dev.recv = smc911x_recv;
sprintf(priv->dev.name, "%s-%hu", DRIVERNAME, dev_num);
eth_register(&priv->dev);
ret = smc911x_initialize_mii(priv);
if (ret)
goto err_mii;
return 1;
err_mii:
eth_unregister(&priv->dev);
err_detect:
free(priv);
return ret;
}
#else /* ifdef CONFIG_DM_ETH */
static int smc911x_start(struct udevice *dev)
{
struct eth_pdata *plat = dev_get_plat(dev);
@ -642,4 +496,3 @@ U_BOOT_DRIVER(smc911x) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif

2
drivers/net/sunxi_emac.c
View File

@ -164,9 +164,7 @@ struct emac_eth_dev {
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
#ifdef CONFIG_DM_ETH
uchar rx_buf[EMAC_RX_BUFSIZE];
#endif
};
struct emac_rxhdr {

96
drivers/net/ti/cpsw.c
View File

@ -200,11 +200,7 @@ struct cpdma_chan {
((priv)->data)->slaves; slave++)
struct cpsw_priv {
#ifdef CONFIG_DM_ETH
struct udevice *dev;
#else
struct eth_device *dev;
#endif
struct cpsw_platform_data *data;
int host_port;
@ -455,15 +451,10 @@ static inline void setbit_and_wait_for_clear32(void *addr)
static void cpsw_set_slave_mac(struct cpsw_slave *slave,
struct cpsw_priv *priv)
{
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(priv->dev);
writel(mac_hi(pdata->enetaddr), &slave->regs->sa_hi);
writel(mac_lo(pdata->enetaddr), &slave->regs->sa_lo);
#else
__raw_writel(mac_hi(priv->dev->enetaddr), &slave->regs->sa_hi);
__raw_writel(mac_lo(priv->dev->enetaddr), &slave->regs->sa_lo);
#endif
}
static int cpsw_slave_update_link(struct cpsw_slave *slave,
@ -856,21 +847,13 @@ static int cpsw_phy_init(struct cpsw_priv *priv, struct cpsw_slave *slave)
ret = phy_set_supported(phydev, slave->data->max_speed);
if (ret)
return ret;
#if CONFIG_IS_ENABLED(DM_ETH)
dev_dbg(priv->dev, "Port %u speed forced to %uMbit\n",
slave->slave_num + 1, slave->data->max_speed);
#else
log_debug("%s: Port %u speed forced to %uMbit\n",
priv->dev->name, slave->slave_num + 1,
slave->data->max_speed);
#endif
}
phydev->advertising = phydev->supported;
#ifdef CONFIG_DM_ETH
if (ofnode_valid(slave->data->phy_of_handle))
phydev->node = slave->data->phy_of_handle;
#endif
priv->phydev = phydev;
phy_config(phydev);
@ -935,84 +918,6 @@ int _cpsw_register(struct cpsw_priv *priv)
return 0;
}
#ifndef CONFIG_DM_ETH
static int cpsw_init(struct eth_device *dev, struct bd_info *bis)
{
struct cpsw_priv *priv = dev->priv;
return _cpsw_init(priv, dev->enetaddr);
}
static void cpsw_halt(struct eth_device *dev)
{
struct cpsw_priv *priv = dev->priv;
return _cpsw_halt(priv);
}
static int cpsw_send(struct eth_device *dev, void *packet, int length)
{
struct cpsw_priv *priv = dev->priv;
return _cpsw_send(priv, packet, length);
}
static int cpsw_recv(struct eth_device *dev)
{
struct cpsw_priv *priv = dev->priv;
uchar *pkt = NULL;
int len;
len = _cpsw_recv(priv, &pkt);
if (len > 0) {
net_process_received_packet(pkt, len);
cpdma_submit(priv, &priv->rx_chan, pkt, PKTSIZE);
}
return len;
}
int cpsw_register(struct cpsw_platform_data *data)
{
struct cpsw_priv *priv;
struct eth_device *dev;
int ret;
dev = calloc(sizeof(*dev), 1);
if (!dev)
return -ENOMEM;
priv = calloc(sizeof(*priv), 1);
if (!priv) {
free(dev);
return -ENOMEM;
}
priv->dev = dev;
priv->data = data;
strcpy(dev->name, "cpsw");
dev->iobase = 0;
dev->init = cpsw_init;
dev->halt = cpsw_halt;
dev->send = cpsw_send;
dev->recv = cpsw_recv;
dev->priv = priv;
eth_register(dev);
ret = _cpsw_register(priv);
if (ret < 0) {
eth_unregister(dev);
free(dev);
free(priv);
return ret;
}
return 1;
}
#else
static int cpsw_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@ -1380,4 +1285,3 @@ U_BOOT_DRIVER(eth_cpsw) = {
.priv_auto = sizeof(struct cpsw_priv),
.flags = DM_FLAG_ALLOC_PRIV_DMA | DM_FLAG_PRE_RELOC,
};
#endif /* CONFIG_DM_ETH */

6
drivers/net/ti/keystone_net.c
View File

@ -592,10 +592,8 @@ static int ks2_eth_probe(struct udevice *dev)
if (priv->has_mdio) {
priv->phydev = phy_connect(priv->mdio_bus, priv->phy_addr,
dev, priv->phy_if);
#ifdef CONFIG_DM_ETH
if (ofnode_valid(priv->phy_ofnode))
priv->phydev->node = priv->phy_ofnode;
#endif
if (ofnode_valid(priv->phy_ofnode))
priv->phydev->node = priv->phy_ofnode;
phy_config(priv->phydev);
}

199
drivers/net/tsec.c
View File

@ -22,34 +22,6 @@
#include <asm/processor.h>
#include <asm/io.h>
#ifndef CONFIG_DM_ETH
/* Default initializations for TSEC controllers. */
static struct tsec_info_struct tsec_info[] = {
#ifdef CONFIG_TSEC1
STD_TSEC_INFO(1), /* TSEC1 */
#endif
#ifdef CONFIG_TSEC2
STD_TSEC_INFO(2), /* TSEC2 */
#endif
#ifdef CONFIG_MPC85XX_FEC
{
.regs = TSEC_GET_REGS(2, 0x2000),
.devname = CONFIG_MPC85XX_FEC_NAME,
.phyaddr = FEC_PHY_ADDR,
.flags = FEC_FLAGS,
.mii_devname = DEFAULT_MII_NAME
}, /* FEC */
#endif
#ifdef CONFIG_TSEC3
STD_TSEC_INFO(3), /* TSEC3 */
#endif
#ifdef CONFIG_TSEC4
STD_TSEC_INFO(4), /* TSEC4 */
#endif
};
#endif /* CONFIG_DM_ETH */
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
@ -124,23 +96,14 @@ static u32 ether_crc(size_t len, unsigned char const *p)
* for PowerPC (tm) is usually the case) in the register holds
* the entry.
*/
#ifndef CONFIG_DM_ETH
static int tsec_mcast_addr(struct eth_device *dev, const u8 *mcast_mac,
int join)
#else
static int tsec_mcast_addr(struct udevice *dev, const u8 *mcast_mac, int join)
#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
u32 result, value;
u8 whichbit, whichreg;
#ifndef CONFIG_DM_ETH
priv = (struct tsec_private *)dev->priv;
#else
priv = dev_get_priv(dev);
#endif
regs = priv->regs;
result = ether_crc(MAC_ADDR_LEN, mcast_mac);
whichbit = (result >> 24) & 0x1f; /* the 5 LSB = which bit to set */
@ -271,11 +234,7 @@ static void adjust_link(struct tsec_private *priv, struct phy_device *phydev)
* do the same. Presumably, this would be zero if there were no
* errors
*/
#ifndef CONFIG_DM_ETH
static int tsec_send(struct eth_device *dev, void *packet, int length)
#else
static int tsec_send(struct udevice *dev, void *packet, int length)
#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
@ -283,11 +242,7 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
u16 status;
int i;
#ifndef CONFIG_DM_ETH
priv = (struct tsec_private *)dev->priv;
#else
priv = dev_get_priv(dev);
#endif
regs = priv->regs;
/* Find an empty buffer descriptor */
for (i = 0;
@ -324,42 +279,6 @@ static int tsec_send(struct udevice *dev, void *packet, int length)
return result;
}
#ifndef CONFIG_DM_ETH
static int tsec_recv(struct eth_device *dev)
{
struct tsec_private *priv = (struct tsec_private *)dev->priv;
struct tsec __iomem *regs = priv->regs;
while (!(in_be16(&priv->rxbd[priv->rx_idx].status) & RXBD_EMPTY)) {
int length = in_be16(&priv->rxbd[priv->rx_idx].length);
u16 status = in_be16(&priv->rxbd[priv->rx_idx].status);
uchar *packet = net_rx_packets[priv->rx_idx];
/* Send the packet up if there were no errors */
if (!(status & RXBD_STATS))
net_process_received_packet(packet, length - 4);
else
printf("Got error %x\n", (status & RXBD_STATS));
out_be16(&priv->rxbd[priv->rx_idx].length, 0);
status = RXBD_EMPTY;
/* Set the wrap bit if this is the last element in the list */
if ((priv->rx_idx + 1) == PKTBUFSRX)
status |= RXBD_WRAP;
out_be16(&priv->rxbd[priv->rx_idx].status, status);
priv->rx_idx = (priv->rx_idx + 1) % PKTBUFSRX;
}
if (in_be32(&regs->ievent) & IEVENT_BSY) {
out_be32(&regs->ievent, IEVENT_BSY);
out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
}
return -1;
}
#else
static int tsec_recv(struct udevice *dev, int flags, uchar **packetp)
{
struct tsec_private *priv = (struct tsec_private *)dev_get_priv(dev);
@ -406,22 +325,12 @@ static int tsec_free_pkt(struct udevice *dev, uchar *packet, int length)
return 0;
}
#endif
/* Stop the interface */
#ifndef CONFIG_DM_ETH
static void tsec_halt(struct eth_device *dev)
#else
static void tsec_halt(struct udevice *dev)
#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
#ifndef CONFIG_DM_ETH
priv = (struct tsec_private *)dev->priv;
#else
priv = dev_get_priv(dev);
#endif
regs = priv->regs;
clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
@ -583,27 +492,15 @@ static void startup_tsec(struct tsec_private *priv)
* that it returns success if the link is up, failure otherwise.
* This allows U-Boot to find the first active controller.
*/
#ifndef CONFIG_DM_ETH
static int tsec_init(struct eth_device *dev, struct bd_info *bd)
#else
static int tsec_init(struct udevice *dev)
#endif
{
struct tsec_private *priv;
struct tsec __iomem *regs;
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(dev);
#else
struct eth_device *pdata = dev;
#endif
u32 tempval;
int ret;
#ifndef CONFIG_DM_ETH
priv = (struct tsec_private *)dev->priv;
#else
priv = dev_get_priv(dev);
#endif
regs = priv->regs;
/* Make sure the controller is stopped */
tsec_halt(dev);
@ -715,7 +612,7 @@ static int init_phy(struct tsec_private *priv)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
tsec_configure_serdes(priv);
#if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_MDIO)
#if defined(CONFIG_DM_MDIO)
phydev = dm_eth_phy_connect(priv->dev);
#else
phydev = phy_connect(priv->bus, priv->phyaddr, priv->dev,
@ -734,99 +631,6 @@ static int init_phy(struct tsec_private *priv)
return 1;
}
#ifndef CONFIG_DM_ETH
/*
* Initialize device structure. Returns success if PHY
* initialization succeeded (i.e. if it recognizes the PHY)
*/
static int tsec_initialize(struct bd_info *bis,
struct tsec_info_struct *tsec_info)
{
struct tsec_private *priv;
struct eth_device *dev;
int i;
dev = (struct eth_device *)malloc(sizeof(*dev));
if (!dev)
return 0;
memset(dev, 0, sizeof(*dev));
priv = (struct tsec_private *)malloc(sizeof(*priv));
if (!priv) {
free(dev);
return 0;
}
priv->regs = tsec_info->regs;
priv->phyregs_sgmii = tsec_info->miiregs_sgmii;
priv->phyaddr = tsec_info->phyaddr;
priv->tbiaddr = CFG_SYS_TBIPA_VALUE;
priv->flags = tsec_info->flags;
strcpy(dev->name, tsec_info->devname);
priv->interface = tsec_info->interface;
priv->bus = miiphy_get_dev_by_name(tsec_info->mii_devname);
priv->dev = dev;
dev->iobase = 0;
dev->priv = priv;
dev->init = tsec_init;
dev->halt = tsec_halt;
dev->send = tsec_send;
dev->recv = tsec_recv;
dev->mcast = tsec_mcast_addr;
/* Tell U-Boot to get the addr from the env */
for (i = 0; i < 6; i++)
dev->enetaddr[i] = 0;
eth_register(dev);
/* Reset the MAC */
setbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
udelay(2); /* Soft Reset must be asserted for 3 TX clocks */
clrbits_be32(&priv->regs->maccfg1, MACCFG1_SOFT_RESET);
/* Try to initialize PHY here, and return */
return init_phy(priv);
}
/*
* Initialize all the TSEC devices
*
* Returns the number of TSEC devices that were initialized
*/
int tsec_eth_init(struct bd_info *bis, struct tsec_info_struct *tsecs,
int num)
{
int i;
int count = 0;
for (i = 0; i < num; i++) {
int ret = tsec_initialize(bis, &tsecs[i]);
if (ret > 0)
count += ret;
}
return count;
}
int tsec_standard_init(struct bd_info *bis)
{
struct fsl_pq_mdio_info info;
info.regs = TSEC_GET_MDIO_REGS_BASE(1);
info.name = DEFAULT_MII_NAME;
fsl_pq_mdio_init(bis, &info);
return tsec_eth_init(bis, tsec_info, ARRAY_SIZE(tsec_info));
}
#else /* CONFIG_DM_ETH */
int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@ -966,4 +770,3 @@ U_BOOT_DRIVER(eth_tsec) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */

2
drivers/qe/Makefile
View File

@ -2,6 +2,6 @@
#
# Copyright (C) 2006 Freescale Semiconductor, Inc.
obj-$(CONFIG_QE) += qe.o uccf.o uec.o uec_phy.o
obj-$(CONFIG_QE) += qe.o
obj-$(CONFIG_U_QE) += qe.o
obj-$(CONFIG_OF_LIBFDT) += fdt.o

509
drivers/qe/uccf.c
View File

@ -1,509 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#include <common.h>
#include <malloc.h>
#include <linux/errno.h>
#include <asm/io.h>
#include <linux/immap_qe.h>
#include "uccf.h"
#include <fsl_qe.h>
#if !defined(CONFIG_DM_ETH)
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf)
{
out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
}
u32 ucc_fast_get_qe_cr_subblock(int ucc_num)
{
switch (ucc_num) {
case 0:
return QE_CR_SUBBLOCK_UCCFAST1;
case 1:
return QE_CR_SUBBLOCK_UCCFAST2;
case 2:
return QE_CR_SUBBLOCK_UCCFAST3;
case 3:
return QE_CR_SUBBLOCK_UCCFAST4;
case 4:
return QE_CR_SUBBLOCK_UCCFAST5;
case 5:
return QE_CR_SUBBLOCK_UCCFAST6;
case 6:
return QE_CR_SUBBLOCK_UCCFAST7;
case 7:
return QE_CR_SUBBLOCK_UCCFAST8;
default:
return QE_CR_SUBBLOCK_INVALID;
}
}
static void ucc_get_cmxucr_reg(int ucc_num, u32 **p_cmxucr,
u8 *reg_num, u8 *shift)
{
switch (ucc_num) {
case 0: /* UCC1 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 16;
break;
case 2: /* UCC3 */
*p_cmxucr = &qe_immr->qmx.cmxucr1;
*reg_num = 1;
*shift = 0;
break;
case 4: /* UCC5 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 16;
break;
case 6: /* UCC7 */
*p_cmxucr = &qe_immr->qmx.cmxucr2;
*reg_num = 2;
*shift = 0;
break;
case 1: /* UCC2 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 16;
break;
case 3: /* UCC4 */
*p_cmxucr = &qe_immr->qmx.cmxucr3;
*reg_num = 3;
*shift = 0;
break;
case 5: /* UCC6 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 16;
break;
case 7: /* UCC8 */
*p_cmxucr = &qe_immr->qmx.cmxucr4;
*reg_num = 4;
*shift = 0;
break;
default:
break;
}
}
static int ucc_set_clk_src(int ucc_num, qe_clock_e clock, comm_dir_e mode)
{
u32 *p_cmxucr = NULL;
u8 reg_num = 0;
u8 shift = 0;
u32 clk_bits;
u32 clk_mask;
int source = -1;
/* check if the UCC number is in range. */
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0)
return -EINVAL;
if (!(mode == COMM_DIR_RX || mode == COMM_DIR_TX)) {
printf("%s: bad comm mode type passed\n", __func__);
return -EINVAL;
}
ucc_get_cmxucr_reg(ucc_num, &p_cmxucr, &reg_num, &shift);
switch (reg_num) {
case 1:
switch (clock) {
case QE_BRG1:
source = 1;
break;
case QE_BRG2:
source = 2;
break;
case QE_BRG7:
source = 3;
break;
case QE_BRG8:
source = 4;
break;
case QE_CLK9:
source = 5;
break;
case QE_CLK10:
source = 6;
break;
case QE_CLK11:
source = 7;
break;
case QE_CLK12:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 2:
switch (clock) {
case QE_BRG5:
source = 1;
break;
case QE_BRG6:
source = 2;
break;
case QE_BRG7:
source = 3;
break;
case QE_BRG8:
source = 4;
break;
case QE_CLK13:
source = 5;
break;
case QE_CLK14:
source = 6;
break;
case QE_CLK19:
source = 7;
break;
case QE_CLK20:
source = 8;
break;
case QE_CLK15:
source = 9;
break;
case QE_CLK16:
source = 10;
break;
default:
source = -1;
break;
}
break;
case 3:
switch (clock) {
case QE_BRG9:
source = 1;
break;
case QE_BRG10:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK3:
source = 5;
break;
case QE_CLK4:
source = 6;
break;
case QE_CLK17:
source = 7;
break;
case QE_CLK18:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
case 4:
switch (clock) {
case QE_BRG13:
source = 1;
break;
case QE_BRG14:
source = 2;
break;
case QE_BRG15:
source = 3;
break;
case QE_BRG16:
source = 4;
break;
case QE_CLK5:
source = 5;
break;
case QE_CLK6:
source = 6;
break;
case QE_CLK21:
source = 7;
break;
case QE_CLK22:
source = 8;
break;
case QE_CLK7:
source = 9;
break;
case QE_CLK8:
source = 10;
break;
case QE_CLK16:
source = 11;
break;
default:
source = -1;
break;
}
break;
default:
source = -1;
break;
}
if (source == -1) {
printf("%s: Bad combination of clock and UCC\n", __func__);
return -ENOENT;
}
clk_bits = (u32)source;
clk_mask = QE_CMXUCR_TX_CLK_SRC_MASK;
if (mode == COMM_DIR_RX) {
clk_bits <<= 4; /* Rx field is 4 bits to left of Tx field */
clk_mask <<= 4; /* Rx field is 4 bits to left of Tx field */
}
clk_bits <<= shift;
clk_mask <<= shift;
out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clk_mask) | clk_bits);
return 0;
}
static uint ucc_get_reg_baseaddr(int ucc_num)
{
uint base = 0;
/* check if the UCC number is in range */
if ((ucc_num > UCC_MAX_NUM - 1) || ucc_num < 0) {
printf("%s: the UCC num not in ranges\n", __func__);
return 0;
}
switch (ucc_num) {
case 0:
base = 0x00002000;
break;
case 1:
base = 0x00003000;
break;
case 2:
base = 0x00002200;
break;
case 3:
base = 0x00003200;
break;
case 4:
base = 0x00002400;
break;
case 5:
base = 0x00003400;
break;
case 6:
base = 0x00002600;
break;
case 7:
base = 0x00003600;
break;
default:
break;
}
base = (uint)qe_immr + base;
return base;
}
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
/* Enable reception and/or transmission on this UCC. */
gumr = in_be32(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
}
if (mode & COMM_DIR_RX) {
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
out_be32(&uf_regs->gumr, gumr);
}
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode)
{
ucc_fast_t *uf_regs;
u32 gumr;
uf_regs = uccf->uf_regs;
/* Disable reception and/or transmission on this UCC. */
gumr = in_be32(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
}
if (mode & COMM_DIR_RX) {
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
out_be32(&uf_regs->gumr, gumr);
}
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret)
{
struct ucc_fast_priv *uccf;
ucc_fast_t *uf_regs;
if (!uf_info)
return -EINVAL;
if (uf_info->ucc_num < 0 || (uf_info->ucc_num > UCC_MAX_NUM - 1)) {
printf("%s: Illagal UCC number!\n", __func__);
return -EINVAL;
}
uccf = (struct ucc_fast_priv *)malloc(sizeof(struct ucc_fast_priv));
if (!uccf) {
printf("%s: No memory for UCC fast data structure!\n",
__func__);
return -ENOMEM;
}
memset(uccf, 0, sizeof(struct ucc_fast_priv));
/* Save fast UCC structure */
uccf->uf_info = uf_info;
uccf->uf_regs = (ucc_fast_t *)ucc_get_reg_baseaddr(uf_info->ucc_num);
if (!uccf->uf_regs) {
printf("%s: No memory map for UCC fast controller!\n",
__func__);
return -ENOMEM;
}
uccf->enabled_tx = 0;
uccf->enabled_rx = 0;
uf_regs = uccf->uf_regs;
uccf->p_ucce = (u32 *)&uf_regs->ucce;
uccf->p_uccm = (u32 *)&uf_regs->uccm;
/* Init GUEMR register, UCC both Rx and Tx is Fast protocol */
out_8(&uf_regs->guemr, UCC_GUEMR_SET_RESERVED3 | UCC_GUEMR_MODE_FAST_RX
| UCC_GUEMR_MODE_FAST_TX);
/* Set GUMR, disable UCC both Rx and Tx, Ethernet protocol */
out_be32(&uf_regs->gumr, UCC_FAST_GUMR_ETH);
/* Set the Giga ethernet VFIFO stuff */
if (uf_info->eth_type == GIGA_ETH) {
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_GIGA_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_URFS_GIGA_INIT +
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb,
uccf->ucc_fast_tx_virtual_fifo_base_offset);
out_be32(&uf_regs->urfb,
uccf->ucc_fast_rx_virtual_fifo_base_offset);
/* Set Virtual Fifo registers */
out_be16(&uf_regs->urfs, UCC_GETH_URFS_GIGA_INIT);
out_be16(&uf_regs->urfet, UCC_GETH_URFET_GIGA_INIT);
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_GIGA_INIT);
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_GIGA_INIT);
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_GIGA_INIT);
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_GIGA_INIT);
}
/* Set the Fast ethernet VFIFO stuff */
if (uf_info->eth_type == FAST_ETH) {
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_UTFS_INIT,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* Allocate memory for Rx Virtual Fifo */
uccf->ucc_fast_rx_virtual_fifo_base_offset =
qe_muram_alloc(UCC_GETH_URFS_INIT +
UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD,
UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT);
/* utfb, urfb are offsets from MURAM base */
out_be32(&uf_regs->utfb,
uccf->ucc_fast_tx_virtual_fifo_base_offset);
out_be32(&uf_regs->urfb,
uccf->ucc_fast_rx_virtual_fifo_base_offset);
/* Set Virtual Fifo registers */
out_be16(&uf_regs->urfs, UCC_GETH_URFS_INIT);
out_be16(&uf_regs->urfet, UCC_GETH_URFET_INIT);
out_be16(&uf_regs->urfset, UCC_GETH_URFSET_INIT);
out_be16(&uf_regs->utfs, UCC_GETH_UTFS_INIT);
out_be16(&uf_regs->utfet, UCC_GETH_UTFET_INIT);
out_be16(&uf_regs->utftt, UCC_GETH_UTFTT_INIT);
}
/* Rx clock routing */
if (uf_info->rx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->rx_clock, COMM_DIR_RX)) {
printf("%s: Illegal value for parameter 'RxClock'.\n",
__func__);
return -EINVAL;
}
}
/* Tx clock routing */
if (uf_info->tx_clock != QE_CLK_NONE) {
if (ucc_set_clk_src(uf_info->ucc_num,
uf_info->tx_clock, COMM_DIR_TX)) {
printf("%s: Illegal value for parameter 'TxClock'.\n",
__func__);
return -EINVAL;
}
}
/* Clear interrupt mask register to disable all of interrupts */
out_be32(&uf_regs->uccm, 0x0);
/* Writing '1' to clear all of envents */
out_be32(&uf_regs->ucce, 0xffffffff);
*uccf_ret = uccf;
return 0;
}
#endif

119
drivers/qe/uccf.h
View File

@ -1,119 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#ifndef __UCCF_H__
#define __UCCF_H__
#include "common.h"
#include "linux/immap_qe.h"
#include <fsl_qe.h>
/* Fast or Giga ethernet */
enum enet_type {
FAST_ETH,
GIGA_ETH,
};
/* General UCC Extended Mode Register */
#define UCC_GUEMR_MODE_MASK_RX 0x02
#define UCC_GUEMR_MODE_MASK_TX 0x01
#define UCC_GUEMR_MODE_FAST_RX 0x02
#define UCC_GUEMR_MODE_FAST_TX 0x01
#define UCC_GUEMR_MODE_SLOW_RX 0x00
#define UCC_GUEMR_MODE_SLOW_TX 0x00
/* Bit 3 must be set 1 */
#define UCC_GUEMR_SET_RESERVED3 0x10
/* General UCC FAST Mode Register */
#define UCC_FAST_GUMR_TCI 0x20000000
#define UCC_FAST_GUMR_TRX 0x10000000
#define UCC_FAST_GUMR_TTX 0x08000000
#define UCC_FAST_GUMR_CDP 0x04000000
#define UCC_FAST_GUMR_CTSP 0x02000000
#define UCC_FAST_GUMR_CDS 0x01000000
#define UCC_FAST_GUMR_CTSS 0x00800000
#define UCC_FAST_GUMR_TXSY 0x00020000
#define UCC_FAST_GUMR_RSYN 0x00010000
#define UCC_FAST_GUMR_RTSM 0x00002000
#define UCC_FAST_GUMR_REVD 0x00000400
#define UCC_FAST_GUMR_ENR 0x00000020
#define UCC_FAST_GUMR_ENT 0x00000010
/* GUMR [MODE] bit maps */
#define UCC_FAST_GUMR_HDLC 0x00000000
#define UCC_FAST_GUMR_QMC 0x00000002
#define UCC_FAST_GUMR_UART 0x00000004
#define UCC_FAST_GUMR_BISYNC 0x00000008
#define UCC_FAST_GUMR_ATM 0x0000000a
#define UCC_FAST_GUMR_ETH 0x0000000c
/* Transmit On Demand (UTORD) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000
/* Fast Ethernet (10/100 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_INIT 512
/* 1/2 urfs */
#define UCC_GETH_URFET_INIT 256
/* 3/4 urfs */
#define UCC_GETH_URFSET_INIT 384
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_INIT 512
/* 1/2 utfs */
#define UCC_GETH_UTFET_INIT 256
#define UCC_GETH_UTFTT_INIT 128
/* Gigabit Ethernet (1000 Mbps) */
/* Rx virtual FIFO size */
#define UCC_GETH_URFS_GIGA_INIT 4096/*2048*/
/* 1/2 urfs */
#define UCC_GETH_URFET_GIGA_INIT 2048/*1024*/
/* 3/4 urfs */
#define UCC_GETH_URFSET_GIGA_INIT 3072/*1536*/
/* Tx virtual FIFO size */
#define UCC_GETH_UTFS_GIGA_INIT 8192/*2048*/
/* 1/2 utfs */
#define UCC_GETH_UTFET_GIGA_INIT 4096/*1024*/
#define UCC_GETH_UTFTT_GIGA_INIT 0x400/*0x40*/
/* UCC fast alignment */
#define UCC_FAST_RX_ALIGN 4
#define UCC_FAST_MRBLR_ALIGNMENT 4
#define UCC_FAST_VIRT_FIFO_REGS_ALIGNMENT 8
/* Sizes */
#define UCC_FAST_RX_VIRTUAL_FIFO_SIZE_PAD 8
/* UCC fast structure. */
struct ucc_fast_inf {
int ucc_num;
qe_clock_e rx_clock;
qe_clock_e tx_clock;
enum enet_type eth_type;
};
struct ucc_fast_priv {
struct ucc_fast_inf *uf_info;
ucc_fast_t *uf_regs; /* a pointer to memory map of UCC regs */
u32 *p_ucce; /* a pointer to the event register */
u32 *p_uccm; /* a pointer to the mask register */
int enabled_tx; /* whether UCC is enabled for Tx (ENT) */
int enabled_rx; /* whether UCC is enabled for Rx (ENR) */
u32 ucc_fast_tx_virtual_fifo_base_offset;
u32 ucc_fast_rx_virtual_fifo_base_offset;
};
void ucc_fast_transmit_on_demand(struct ucc_fast_priv *uccf);
u32 ucc_fast_get_qe_cr_subblock(int ucc_num);
void ucc_fast_enable(struct ucc_fast_priv *uccf, comm_dir_e mode);
void ucc_fast_disable(struct ucc_fast_priv *uccf, comm_dir_e mode);
int ucc_fast_init(struct ucc_fast_inf *uf_info,
struct ucc_fast_priv **uccf_ret);
#endif /* __UCCF_H__ */

1436
drivers/qe/uec.c
View File

File diff suppressed because it is too large Load Diff

692
drivers/qe/uec.h
View File

@ -1,692 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2006-2010 Freescale Semiconductor, Inc.
*
* Dave Liu <daveliu@freescale.com>
* based on source code of Shlomi Gridish
*/
#ifndef __UEC_H__
#define __UEC_H__
#include "uccf.h"
#include <fsl_qe.h>
#include <phy.h>
#define MAX_TX_THREADS 8
#define MAX_RX_THREADS 8
#define MAX_TX_QUEUES 8
#define MAX_RX_QUEUES 8
#define MAX_PREFETCHED_BDS 4
#define MAX_IPH_OFFSET_ENTRY 8
#define MAX_ENET_INIT_PARAM_ENTRIES_RX 9
#define MAX_ENET_INIT_PARAM_ENTRIES_TX 8
/* UEC UPSMR (Protocol Specific Mode Register)
*/
#define UPSMR_ECM 0x04000000 /* Enable CAM Miss */
#define UPSMR_HSE 0x02000000 /* Hardware Statistics Enable */
#define UPSMR_PRO 0x00400000 /* Promiscuous */
#define UPSMR_CAP 0x00200000 /* CAM polarity */
#define UPSMR_RSH 0x00100000 /* Receive Short Frames */
#define UPSMR_RPM 0x00080000 /* Reduced Pin Mode interfaces */
#define UPSMR_R10M 0x00040000 /* RGMII/RMII 10 Mode */
#define UPSMR_RLPB 0x00020000 /* RMII Loopback Mode */
#define UPSMR_TBIM 0x00010000 /* Ten-bit Interface Mode */
#define UPSMR_RMM 0x00001000 /* RMII/RGMII Mode */
#define UPSMR_CAM 0x00000400 /* CAM Address Matching */
#define UPSMR_BRO 0x00000200 /* Broadcast Address */
#define UPSMR_RES1 0x00002000 /* Reserved feild - must be 1 */
#define UPSMR_SGMM 0x00000020 /* SGMII mode */
#define UPSMR_INIT_VALUE (UPSMR_HSE | UPSMR_RES1)
/* UEC MACCFG1 (MAC Configuration 1 Register)
*/
#define MACCFG1_FLOW_RX 0x00000020 /* Flow Control Rx */
#define MACCFG1_FLOW_TX 0x00000010 /* Flow Control Tx */
#define MACCFG1_ENABLE_SYNCHED_RX 0x00000008 /* Enable Rx Sync */
#define MACCFG1_ENABLE_RX 0x00000004 /* Enable Rx */
#define MACCFG1_ENABLE_SYNCHED_TX 0x00000002 /* Enable Tx Sync */
#define MACCFG1_ENABLE_TX 0x00000001 /* Enable Tx */
#define MACCFG1_INIT_VALUE (0)
/* UEC MACCFG2 (MAC Configuration 2 Register)
*/
#define MACCFG2_PREL 0x00007000
#define MACCFG2_PREL_SHIFT (31 - 19)
#define MACCFG2_PREL_MASK 0x0000f000
#define MACCFG2_SRP 0x00000080
#define MACCFG2_STP 0x00000040
#define MACCFG2_RESERVED_1 0x00000020 /* must be set */
#define MACCFG2_LC 0x00000010 /* Length Check */
#define MACCFG2_MPE 0x00000008
#define MACCFG2_FDX 0x00000001 /* Full Duplex */
#define MACCFG2_FDX_MASK 0x00000001
#define MACCFG2_PAD_CRC 0x00000004
#define MACCFG2_CRC_EN 0x00000002
#define MACCFG2_PAD_AND_CRC_MODE_NONE 0x00000000
#define MACCFG2_PAD_AND_CRC_MODE_CRC_ONLY 0x00000002
#define MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC 0x00000004
#define MACCFG2_INTERFACE_MODE_NIBBLE 0x00000100
#define MACCFG2_INTERFACE_MODE_BYTE 0x00000200
#define MACCFG2_INTERFACE_MODE_MASK 0x00000300
#define MACCFG2_INIT_VALUE (MACCFG2_PREL | MACCFG2_RESERVED_1 | \
MACCFG2_LC | MACCFG2_PAD_CRC | MACCFG2_FDX)
/* UEC Event Register */
#define UCCE_MPD 0x80000000
#define UCCE_SCAR 0x40000000
#define UCCE_GRA 0x20000000
#define UCCE_CBPR 0x10000000
#define UCCE_BSY 0x08000000
#define UCCE_RXC 0x04000000
#define UCCE_TXC 0x02000000
#define UCCE_TXE 0x01000000
#define UCCE_TXB7 0x00800000
#define UCCE_TXB6 0x00400000
#define UCCE_TXB5 0x00200000
#define UCCE_TXB4 0x00100000
#define UCCE_TXB3 0x00080000
#define UCCE_TXB2 0x00040000
#define UCCE_TXB1 0x00020000
#define UCCE_TXB0 0x00010000
#define UCCE_RXB7 0x00008000
#define UCCE_RXB6 0x00004000
#define UCCE_RXB5 0x00002000
#define UCCE_RXB4 0x00001000
#define UCCE_RXB3 0x00000800
#define UCCE_RXB2 0x00000400
#define UCCE_RXB1 0x00000200
#define UCCE_RXB0 0x00000100
#define UCCE_RXF7 0x00000080
#define UCCE_RXF6 0x00000040
#define UCCE_RXF5 0x00000020
#define UCCE_RXF4 0x00000010
#define UCCE_RXF3 0x00000008
#define UCCE_RXF2 0x00000004
#define UCCE_RXF1 0x00000002
#define UCCE_RXF0 0x00000001
#define UCCE_TXB (UCCE_TXB7 | UCCE_TXB6 | UCCE_TXB5 | UCCE_TXB4 | \
UCCE_TXB3 | UCCE_TXB2 | UCCE_TXB1 | UCCE_TXB0)
#define UCCE_RXB (UCCE_RXB7 | UCCE_RXB6 | UCCE_RXB5 | UCCE_RXB4 | \
UCCE_RXB3 | UCCE_RXB2 | UCCE_RXB1 | UCCE_RXB0)
#define UCCE_RXF (UCCE_RXF7 | UCCE_RXF6 | UCCE_RXF5 | UCCE_RXF4 | \
UCCE_RXF3 | UCCE_RXF2 | UCCE_RXF1 | UCCE_RXF0)
#define UCCE_OTHER (UCCE_SCAR | UCCE_GRA | UCCE_CBPR | UCCE_BSY | \
UCCE_RXC | UCCE_TXC | UCCE_TXE)
/* UEC TEMODR Register */
#define TEMODER_SCHEDULER_ENABLE 0x2000
#define TEMODER_IP_CHECKSUM_GENERATE 0x0400
#define TEMODER_PERFORMANCE_OPTIMIZATION_MODE1 0x0200
#define TEMODER_RMON_STATISTICS 0x0100
#define TEMODER_NUM_OF_QUEUES_SHIFT (15 - 15)
#define TEMODER_INIT_VALUE 0xc000
/* UEC REMODR Register */
#define REMODER_RX_RMON_STATISTICS_ENABLE 0x00001000
#define REMODER_RX_EXTENDED_FEATURES 0x80000000
#define REMODER_VLAN_OPERATION_TAGGED_SHIFT (31 - 9)
#define REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT (31 - 10)
#define REMODER_RX_QOS_MODE_SHIFT (31 - 15)
#define REMODER_RMON_STATISTICS 0x00001000
#define REMODER_RX_EXTENDED_FILTERING 0x00000800
#define REMODER_NUM_OF_QUEUES_SHIFT (31 - 23)
#define REMODER_DYNAMIC_MAX_FRAME_LENGTH 0x00000008
#define REMODER_DYNAMIC_MIN_FRAME_LENGTH 0x00000004
#define REMODER_IP_CHECKSUM_CHECK 0x00000002
#define REMODER_IP_ADDRESS_ALIGNMENT 0x00000001
#define REMODER_INIT_VALUE 0
/* BMRx - Bus Mode Register */
#define BMR_GLB 0x20
#define BMR_BO_BE 0x10
#define BMR_DTB_SECONDARY_BUS 0x02
#define BMR_BDB_SECONDARY_BUS 0x01
#define BMR_SHIFT 24
#define BMR_INIT_VALUE (BMR_GLB | BMR_BO_BE)
/* UEC UCCS (Ethernet Status Register)
*/
#define UCCS_BPR 0x02
#define UCCS_PAU 0x02
#define UCCS_MPD 0x01
/* UEC MIIMCFG (MII Management Configuration Register)
*/
#define MIIMCFG_RESET_MANAGEMENT 0x80000000
#define MIIMCFG_NO_PREAMBLE 0x00000010
#define MIIMCFG_CLOCK_DIVIDE_SHIFT (31 - 31)
#define MIIMCFG_CLOCK_DIVIDE_MASK 0x0000000f
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_4 0x00000001
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_6 0x00000002
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_8 0x00000003
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10 0x00000004
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_14 0x00000005
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_20 0x00000006
#define MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_28 0x00000007
#define MIIMCFG_MNGMNT_CLC_DIV_INIT_VALUE \
MIIMCFG_MANAGEMENT_CLOCK_DIVIDE_BY_10
/* UEC MIIMCOM (MII Management Command Register)
*/
#define MIIMCOM_SCAN_CYCLE 0x00000002 /* Scan cycle */
#define MIIMCOM_READ_CYCLE 0x00000001 /* Read cycle */
/* UEC MIIMADD (MII Management Address Register)
*/
#define MIIMADD_PHY_ADDRESS_SHIFT (31 - 23)
#define MIIMADD_PHY_REGISTER_SHIFT (31 - 31)
/* UEC MIIMCON (MII Management Control Register)
*/
#define MIIMCON_PHY_CONTROL_SHIFT (31 - 31)
#define MIIMCON_PHY_STATUS_SHIFT (31 - 31)
/* UEC MIIMIND (MII Management Indicator Register)
*/
#define MIIMIND_NOT_VALID 0x00000004
#define MIIMIND_SCAN 0x00000002
#define MIIMIND_BUSY 0x00000001
/* UEC UTBIPAR (Ten Bit Interface Physical Address Register)
*/
#define UTBIPAR_PHY_ADDRESS_SHIFT (31 - 31)
#define UTBIPAR_PHY_ADDRESS_MASK 0x0000001f
/* UEC UESCR (Ethernet Statistics Control Register)
*/
#define UESCR_AUTOZ 0x8000
#define UESCR_CLRCNT 0x4000
#define UESCR_MAXCOV_SHIFT (15 - 7)
#define UESCR_SCOV_SHIFT (15 - 15)
/****** Tx data struct collection ******/
/* Tx thread data, each Tx thread has one this struct. */
struct uec_thread_data_tx {
u8 res0[136];
} __packed;
/* Tx thread parameter, each Tx thread has one this struct. */
struct uec_thread_tx_pram {
u8 res0[64];
} __packed;
/* Send queue queue-descriptor, each Tx queue has one this QD */
struct uec_send_queue_qd {
u32 bd_ring_base; /* pointer to BD ring base address */
u8 res0[0x8];
u32 last_bd_completed_address; /* last entry in BD ring */
u8 res1[0x30];
} __packed;
/* Send queue memory region */
struct uec_send_queue_mem_region {
struct uec_send_queue_qd sqqd[MAX_TX_QUEUES];
} __packed;
/* Scheduler struct */
struct uec_scheduler {
u16 cpucount0; /* CPU packet counter */
u16 cpucount1; /* CPU packet counter */
u16 cecount0; /* QE packet counter */
u16 cecount1; /* QE packet counter */
u16 cpucount2; /* CPU packet counter */
u16 cpucount3; /* CPU packet counter */
u16 cecount2; /* QE packet counter */
u16 cecount3; /* QE packet counter */
u16 cpucount4; /* CPU packet counter */
u16 cpucount5; /* CPU packet counter */
u16 cecount4; /* QE packet counter */
u16 cecount5; /* QE packet counter */
u16 cpucount6; /* CPU packet counter */
u16 cpucount7; /* CPU packet counter */
u16 cecount6; /* QE packet counter */
u16 cecount7; /* QE packet counter */
u32 weightstatus[MAX_TX_QUEUES]; /* accumulated weight factor */
u32 rtsrshadow; /* temporary variable handled by QE */
u32 time; /* temporary variable handled by QE */
u32 ttl; /* temporary variable handled by QE */
u32 mblinterval; /* max burst length interval */
u16 nortsrbytetime; /* normalized value of byte time in tsr units */
u8 fracsiz;
u8 res0[1];
u8 strictpriorityq; /* Strict Priority Mask register */
u8 txasap; /* Transmit ASAP register */
u8 extrabw; /* Extra BandWidth register */
u8 oldwfqmask; /* temporary variable handled by QE */
u8 weightfactor[MAX_TX_QUEUES]; /**< weight factor for queues */
u32 minw; /* temporary variable handled by QE */
u8 res1[0x70 - 0x64];
} __packed;
/* Tx firmware counters */
struct uec_tx_firmware_statistics_pram {
u32 sicoltx; /* single collision */
u32 mulcoltx; /* multiple collision */
u32 latecoltxfr; /* late collision */
u32 frabortduecol; /* frames aborted due to tx collision */
u32 frlostinmactxer; /* frames lost due to internal MAC error tx */
u32 carriersenseertx; /* carrier sense error */
u32 frtxok; /* frames transmitted OK */
u32 txfrexcessivedefer;
u32 txpkts256; /* total packets(including bad) 256~511 B */
u32 txpkts512; /* total packets(including bad) 512~1023B */
u32 txpkts1024; /* total packets(including bad) 1024~1518B */
u32 txpktsjumbo; /* total packets(including bad) >1024 */
} __packed;
/* Tx global parameter table */
struct uec_tx_global_pram {
u16 temoder;
u8 res0[0x38 - 0x02];
u32 sqptr;
u32 schedulerbasepointer;
u32 txrmonbaseptr;
u32 tstate;
u8 iphoffset[MAX_IPH_OFFSET_ENTRY];
u32 vtagtable[0x8];
u32 tqptr;
u8 res2[0x80 - 0x74];
} __packed;
/****** Rx data struct collection ******/
/* Rx thread data, each Rx thread has one this struct. */
struct uec_thread_data_rx {
u8 res0[40];
} __packed;
/* Rx thread parameter, each Rx thread has one this struct. */
struct uec_thread_rx_pram {
u8 res0[128];
} __packed;
/* Rx firmware counters */
struct uec_rx_firmware_statistics_pram {
u32 frrxfcser; /* frames with crc error */
u32 fraligner; /* frames with alignment error */
u32 inrangelenrxer; /* in range length error */
u32 outrangelenrxer; /* out of range length error */
u32 frtoolong; /* frame too long */
u32 runt; /* runt */
u32 verylongevent; /* very long event */
u32 symbolerror; /* symbol error */
u32 dropbsy; /* drop because of BD not ready */
u8 res0[0x8];
u32 mismatchdrop; /* drop because of MAC filtering */
u32 underpkts; /* total frames less than 64 octets */
u32 pkts256; /* total frames(including bad)256~511 B */
u32 pkts512; /* total frames(including bad)512~1023 B */
u32 pkts1024; /* total frames(including bad)1024~1518 B */
u32 pktsjumbo; /* total frames(including bad) >1024 B */
u32 frlossinmacer;
u32 pausefr; /* pause frames */
u8 res1[0x4];
u32 removevlan;
u32 replacevlan;
u32 insertvlan;
} __packed;
/* Rx interrupt coalescing entry, each Rx queue has one this entry. */
struct uec_rx_interrupt_coalescing_entry {
u32 maxvalue;
u32 counter;
} __packed;
struct uec_rx_interrupt_coalescing_table {
struct uec_rx_interrupt_coalescing_entry entry[MAX_RX_QUEUES];
} __packed;
/* RxBD queue entry, each Rx queue has one this entry. */
struct uec_rx_bd_queues_entry {
u32 bdbaseptr; /* BD base pointer */
u32 bdptr; /* BD pointer */
u32 externalbdbaseptr; /* external BD base pointer */
u32 externalbdptr; /* external BD pointer */
} __packed;
/* Rx global parameter table */
struct uec_rx_global_pram {
u32 remoder; /* ethernet mode reg. */
u32 rqptr; /* base pointer to the Rx Queues */
u32 res0[0x1];
u8 res1[0x20 - 0xc];
u16 typeorlen;
u8 res2[0x1];
u8 rxgstpack; /* ack on GRACEFUL STOP RX command */
u32 rxrmonbaseptr; /* Rx RMON statistics base */
u8 res3[0x30 - 0x28];
u32 intcoalescingptr; /* Interrupt coalescing table pointer */
u8 res4[0x36 - 0x34];
u8 rstate;
u8 res5[0x46 - 0x37];
u16 mrblr; /* max receive buffer length reg. */
u32 rbdqptr; /* RxBD parameter table description */
u16 mflr; /* max frame length reg. */
u16 minflr; /* min frame length reg. */
u16 maxd1; /* max dma1 length reg. */
u16 maxd2; /* max dma2 length reg. */
u32 ecamptr; /* external CAM address */
u32 l2qt; /* VLAN priority mapping table. */
u32 l3qt[0x8]; /* IP priority mapping table. */
u16 vlantype; /* vlan type */
u16 vlantci; /* default vlan tci */
u8 addressfiltering[64];/* address filtering data structure */
u32 exf_global_param; /* extended filtering global parameters */
u8 res6[0x100 - 0xc4]; /* Initialize to zero */
} __packed;
#define GRACEFUL_STOP_ACKNOWLEDGE_RX 0x01
/****** UEC common ******/
/* UCC statistics - hardware counters */
struct uec_hardware_statistics {
u32 tx64;
u32 tx127;
u32 tx255;
u32 rx64;
u32 rx127;
u32 rx255;
u32 txok;
u16 txcf;
u32 tmca;
u32 tbca;
u32 rxfok;
u32 rxbok;
u32 rbyt;
u32 rmca;
u32 rbca;
} __packed;
/* InitEnet command parameter */
struct uec_init_cmd_pram {
u8 resinit0;
u8 resinit1;
u8 resinit2;
u8 resinit3;
u16 resinit4;
u8 res1[0x1];
u8 largestexternallookupkeysize;
u32 rgftgfrxglobal;
u32 rxthread[MAX_ENET_INIT_PARAM_ENTRIES_RX]; /* rx threads */
u8 res2[0x38 - 0x30];
u32 txglobal; /* tx global */
u32 txthread[MAX_ENET_INIT_PARAM_ENTRIES_TX]; /* tx threads */
u8 res3[0x1];
} __packed;
#define ENET_INIT_PARAM_RGF_SHIFT (32 - 4)
#define ENET_INIT_PARAM_TGF_SHIFT (32 - 8)
#define ENET_INIT_PARAM_RISC_MASK 0x0000003f
#define ENET_INIT_PARAM_PTR_MASK 0x00ffffc0
#define ENET_INIT_PARAM_SNUM_MASK 0xff000000
#define ENET_INIT_PARAM_SNUM_SHIFT 24
#define ENET_INIT_PARAM_MAGIC_RES_INIT0 0x06
#define ENET_INIT_PARAM_MAGIC_RES_INIT1 0x30
#define ENET_INIT_PARAM_MAGIC_RES_INIT2 0xff
#define ENET_INIT_PARAM_MAGIC_RES_INIT3 0x00
#define ENET_INIT_PARAM_MAGIC_RES_INIT4 0x0400
/* structure representing 82xx Address Filtering Enet Address in PRAM */
struct uec_82xx_enet_addr {
u8 res1[0x2];
u16 h; /* address (MSB) */
u16 m; /* address */
u16 l; /* address (LSB) */
} __packed;
/* structure representing 82xx Address Filtering PRAM */
struct uec_82xx_add_filtering_pram {
u32 iaddr_h; /* individual address filter, high */
u32 iaddr_l; /* individual address filter, low */
u32 gaddr_h; /* group address filter, high */
u32 gaddr_l; /* group address filter, low */
struct uec_82xx_enet_addr taddr;
struct uec_82xx_enet_addr paddr[4];
u8 res0[0x40 - 0x38];
} __packed;
/* Buffer Descriptor */
struct buffer_descriptor {
u16 status;
u16 len;
u32 data;
} __packed;
#define SIZEOFBD sizeof(struct buffer_descriptor)
/* Common BD flags */
#define BD_WRAP 0x2000
#define BD_INT 0x1000
#define BD_LAST 0x0800
#define BD_CLEAN 0x3000
/* TxBD status flags */
#define TX_BD_READY 0x8000
#define TX_BD_PADCRC 0x4000
#define TX_BD_WRAP BD_WRAP
#define TX_BD_INT BD_INT
#define TX_BD_LAST BD_LAST
#define TX_BD_TXCRC 0x0400
#define TX_BD_DEF 0x0200
#define TX_BD_PP 0x0100
#define TX_BD_LC 0x0080
#define TX_BD_RL 0x0040
#define TX_BD_RC 0x003C
#define TX_BD_UNDERRUN 0x0002
#define TX_BD_TRUNC 0x0001
#define TX_BD_ERROR (TX_BD_UNDERRUN | TX_BD_TRUNC)
/* RxBD status flags */
#define RX_BD_EMPTY 0x8000
#define RX_BD_OWNER 0x4000
#define RX_BD_WRAP BD_WRAP
#define RX_BD_INT BD_INT
#define RX_BD_LAST BD_LAST
#define RX_BD_FIRST 0x0400
#define RX_BD_CMR 0x0200
#define RX_BD_MISS 0x0100
#define RX_BD_BCAST 0x0080
#define RX_BD_MCAST 0x0040
#define RX_BD_LG 0x0020
#define RX_BD_NO 0x0010
#define RX_BD_SHORT 0x0008
#define RX_BD_CRCERR 0x0004
#define RX_BD_OVERRUN 0x0002
#define RX_BD_IPCH 0x0001
#define RX_BD_ERROR (RX_BD_LG | RX_BD_NO | RX_BD_SHORT | \
RX_BD_CRCERR | RX_BD_OVERRUN)
/* BD access macros */
#define BD_STATUS(_bd) (in_be16(&((_bd)->status)))
#define BD_STATUS_SET(_bd, _v) (out_be16(&((_bd)->status), _v))
#define BD_LENGTH(_bd) (in_be16(&((_bd)->len)))
#define BD_LENGTH_SET(_bd, _v) (out_be16(&((_bd)->len), _v))
#define BD_DATA_CLEAR(_bd) (out_be32(&((_bd)->data), 0))
#define BD_DATA(_bd) ((u8 *)(((_bd)->data)))
#define BD_DATA_SET(_bd, _data) (out_be32(&((_bd)->data), (u32)_data))
#define BD_ADVANCE(_bd, _status, _base) \
(((_status) & BD_WRAP) ? (_bd) = \
((struct buffer_descriptor *)(_base)) : ++(_bd))
/* Rx Prefetched BDs */
struct uec_rx_pref_bds {
struct buffer_descriptor bd[MAX_PREFETCHED_BDS]; /* prefetched bd */
} __packed;
/* Alignments */
#define UEC_RX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_TX_GLOBAL_PRAM_ALIGNMENT 64
#define UEC_THREAD_RX_PRAM_ALIGNMENT 128
#define UEC_THREAD_TX_PRAM_ALIGNMENT 64
#define UEC_THREAD_DATA_ALIGNMENT 256
#define UEC_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT 32
#define UEC_SCHEDULER_ALIGNMENT 4
#define UEC_TX_STATISTICS_ALIGNMENT 4
#define UEC_RX_STATISTICS_ALIGNMENT 4
#define UEC_RX_INTERRUPT_COALESCING_ALIGNMENT 4
#define UEC_RX_BD_QUEUES_ALIGNMENT 8
#define UEC_RX_PREFETCHED_BDS_ALIGNMENT 128
#define UEC_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT 4
#define UEC_RX_BD_RING_ALIGNMENT 32
#define UEC_TX_BD_RING_ALIGNMENT 32
#define UEC_MRBLR_ALIGNMENT 128
#define UEC_RX_BD_RING_SIZE_ALIGNMENT 4
#define UEC_TX_BD_RING_SIZE_MEMORY_ALIGNMENT 32
#define UEC_RX_DATA_BUF_ALIGNMENT 64
#define UEC_VLAN_PRIORITY_MAX 8
#define UEC_IP_PRIORITY_MAX 64
#define UEC_TX_VTAG_TABLE_ENTRY_MAX 8
#define UEC_RX_BD_RING_SIZE_MIN 8
#define UEC_TX_BD_RING_SIZE_MIN 2
/* TBI / MII Set Register */
enum enet_tbi_mii_reg {
ENET_TBI_MII_CR = 0x00,
ENET_TBI_MII_SR = 0x01,
ENET_TBI_MII_ANA = 0x04,
ENET_TBI_MII_ANLPBPA = 0x05,
ENET_TBI_MII_ANEX = 0x06,
ENET_TBI_MII_ANNPT = 0x07,
ENET_TBI_MII_ANLPANP = 0x08,
ENET_TBI_MII_EXST = 0x0F,
ENET_TBI_MII_JD = 0x10,
ENET_TBI_MII_TBICON = 0x11
};
/* TBI MDIO register bit fields*/
#define TBICON_CLK_SELECT 0x0020
#define TBIANA_ASYMMETRIC_PAUSE 0x0100
#define TBIANA_SYMMETRIC_PAUSE 0x0080
#define TBIANA_HALF_DUPLEX 0x0040
#define TBIANA_FULL_DUPLEX 0x0020
#define TBICR_PHY_RESET 0x8000
#define TBICR_ANEG_ENABLE 0x1000
#define TBICR_RESTART_ANEG 0x0200
#define TBICR_FULL_DUPLEX 0x0100
#define TBICR_SPEED1_SET 0x0040
#define TBIANA_SETTINGS ( \
TBIANA_ASYMMETRIC_PAUSE \
| TBIANA_SYMMETRIC_PAUSE \
| TBIANA_FULL_DUPLEX \
)
#define TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
/* UEC number of threads */
enum uec_num_of_threads {
UEC_NUM_OF_THREADS_1 = 0x1, /* 1 */
UEC_NUM_OF_THREADS_2 = 0x2, /* 2 */
UEC_NUM_OF_THREADS_4 = 0x0, /* 4 */
UEC_NUM_OF_THREADS_6 = 0x3, /* 6 */
UEC_NUM_OF_THREADS_8 = 0x4 /* 8 */
};
/* UEC initialization info struct */
#define STD_UEC_INFO(num) \
{ \
.uf_info = { \
.ucc_num = CFG_SYS_UEC##num##_UCC_NUM,\
.rx_clock = CFG_SYS_UEC##num##_RX_CLK, \
.tx_clock = CFG_SYS_UEC##num##_TX_CLK, \
.eth_type = CFG_SYS_UEC##num##_ETH_TYPE,\
}, \
.num_threads_tx = UEC_NUM_OF_THREADS_1, \
.num_threads_rx = UEC_NUM_OF_THREADS_1, \
.risc_tx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.risc_rx = QE_RISC_ALLOCATION_RISC1_AND_RISC2, \
.tx_bd_ring_len = 16, \
.rx_bd_ring_len = 16, \
.phy_address = CFG_SYS_UEC##num##_PHY_ADDR, \
.enet_interface_type = CFG_SYS_UEC##num##_INTERFACE_TYPE, \
.speed = CFG_SYS_UEC##num##_INTERFACE_SPEED, \
}
struct uec_inf {
struct ucc_fast_inf uf_info;
enum uec_num_of_threads num_threads_tx;
enum uec_num_of_threads num_threads_rx;
unsigned int risc_tx;
unsigned int risc_rx;
u16 rx_bd_ring_len;
u16 tx_bd_ring_len;
u8 phy_address;
phy_interface_t enet_interface_type;
int speed;
};
/* UEC driver initialized info */
#define MAX_RXBUF_LEN 1536
#define MAX_FRAME_LEN 1518
#define MIN_FRAME_LEN 64
#define MAX_DMA1_LEN 1520
#define MAX_DMA2_LEN 1520
/* UEC driver private struct */
struct uec_priv {
struct uec_inf *uec_info;
struct ucc_fast_priv *uccf;
struct eth_device *dev;
uec_t *uec_regs;
uec_mii_t *uec_mii_regs;
/* enet init command parameter */
struct uec_init_cmd_pram *p_init_enet_param;
u32 init_enet_param_offset;
/* Rx and Tx parameter */
struct uec_rx_global_pram *p_rx_glbl_pram;
u32 rx_glbl_pram_offset;
struct uec_tx_global_pram *p_tx_glbl_pram;
u32 tx_glbl_pram_offset;
struct uec_send_queue_mem_region *p_send_q_mem_reg;
u32 send_q_mem_reg_offset;
struct uec_thread_data_tx *p_thread_data_tx;
u32 thread_dat_tx_offset;
struct uec_thread_data_rx *p_thread_data_rx;
u32 thread_dat_rx_offset;
struct uec_rx_bd_queues_entry *p_rx_bd_qs_tbl;
u32 rx_bd_qs_tbl_offset;
/* BDs specific */
u8 *p_tx_bd_ring;
u32 tx_bd_ring_offset;
u8 *p_rx_bd_ring;
u32 rx_bd_ring_offset;
u8 *p_rx_buf;
u32 rx_buf_offset;
struct buffer_descriptor *tx_bd;
struct buffer_descriptor *rx_bd;
/* Status */
int mac_tx_enabled;
int mac_rx_enabled;
int grace_stopped_tx;
int grace_stopped_rx;
int the_first_run;
/* PHY specific */
struct uec_mii_info *mii_info;
int oldspeed;
int oldduplex;
int oldlink;
};
int uec_initialize(struct bd_info *bis, struct uec_inf *uec_info);
int uec_eth_init(struct bd_info *bis, struct uec_inf *uecs, int num);
int uec_standard_init(struct bd_info *bis);
#endif /* __UEC_H__ */

930
drivers/qe/uec_phy.c
View File

@ -1,930 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2005,2010-2011 Freescale Semiconductor, Inc.
*
* Author: Shlomi Gridish
*
* Description: UCC GETH Driver -- PHY handling
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
*/
#include <common.h>
#include <net.h>
#include <malloc.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <linux/immap_qe.h>
#include <asm/io.h>
#include "uccf.h"
#include "uec.h"
#include "uec_phy.h"
#include "miiphy.h"
#include <fsl_qe.h>
#include <phy.h>
#if !defined(CONFIG_DM_ETH)
#define ugphy_printk(format, arg...) \
printf(format "\n", ## arg)
#define ugphy_dbg(format, arg...) \
ugphy_printk(format, ## arg)
#define ugphy_err(format, arg...) \
ugphy_printk(format, ## arg)
#define ugphy_info(format, arg...) \
ugphy_printk(format, ## arg)
#define ugphy_warn(format, arg...) \
ugphy_printk(format, ## arg)
#ifdef UEC_VERBOSE_DEBUG
#define ugphy_vdbg ugphy_dbg
#else
#define ugphy_vdbg(ugeth, fmt, args...) do { } while (0)
#endif /* UEC_VERBOSE_DEBUG */
/*
* --------------------------------------------------------------------
* Fixed PHY (PHY-less) support for Ethernet Ports.
*
* Copied from arch/powerpc/cpu/ppc4xx/4xx_enet.c
*--------------------------------------------------------------------
*
* Some boards do not have a PHY for each ethernet port. These ports are known
* as Fixed PHY (or PHY-less) ports. For such ports, set the appropriate
* CFG_SYS_UECx_PHY_ADDR equal to CONFIG_FIXED_PHY_ADDR (an unused address)
* When the drver tries to identify the PHYs, CONFIG_FIXED_PHY will be returned
* and the driver will search CONFIG_SYS_FIXED_PHY_PORTS to find what network
* speed and duplex should be for the port.
*
* Example board header configuration file:
* #define CONFIG_FIXED_PHY 0xFFFFFFFF
* #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E (pick an unused phy address)
*
* #define CFG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
* #define CFG_SYS_UEC2_PHY_ADDR 0x02
* #define CFG_SYS_UEC3_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR
* #define CFG_SYS_UEC4_PHY_ADDR 0x04
*
* #define CONFIG_SYS_FIXED_PHY_PORT(name,speed,duplex) \
* {name, speed, duplex},
*
* #define CONFIG_SYS_FIXED_PHY_PORTS \
* CONFIG_SYS_FIXED_PHY_PORT("UEC0",SPEED_100,DUPLEX_FULL) \
* CONFIG_SYS_FIXED_PHY_PORT("UEC2",SPEED_100,DUPLEX_HALF)
*/
#ifndef CONFIG_FIXED_PHY
#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
#endif
#ifndef CONFIG_SYS_FIXED_PHY_PORTS
#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
#endif
struct fixed_phy_port {
char name[16]; /* ethernet port name */
unsigned int speed; /* specified speed 10,100 or 1000 */
unsigned int duplex; /* specified duplex FULL or HALF */
};
static const struct fixed_phy_port fixed_phy_port[] = {
CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
};
/*
* -------------------------------------------------------------------
* BitBang MII support for ethernet ports
*
* Based from MPC8560ADS implementation
*--------------------------------------------------------------------
*
* Example board header file to define bitbang ethernet ports:
*
* #define CONFIG_SYS_BITBANG_PHY_PORT(name) name,
* #define CONFIG_SYS_BITBANG_PHY_PORTS CONFIG_SYS_BITBANG_PHY_PORT("UEC0")
*/
#ifndef CONFIG_SYS_BITBANG_PHY_PORTS
#define CONFIG_SYS_BITBANG_PHY_PORTS /* default is an empty array */
#endif
#if defined(CONFIG_BITBANGMII)
static const char * const bitbang_phy_port[] = {
CONFIG_SYS_BITBANG_PHY_PORTS /* defined in board configuration file */
};
#endif /* CONFIG_BITBANGMII */
static void config_genmii_advert(struct uec_mii_info *mii_info);
static void genmii_setup_forced(struct uec_mii_info *mii_info);
static void genmii_restart_aneg(struct uec_mii_info *mii_info);
static int gbit_config_aneg(struct uec_mii_info *mii_info);
static int genmii_config_aneg(struct uec_mii_info *mii_info);
static int genmii_update_link(struct uec_mii_info *mii_info);
static int genmii_read_status(struct uec_mii_info *mii_info);
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum);
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum,
u16 val);
/*
* Write value to the PHY for this device to the register at regnum,
* waiting until the write is done before it returns. All PHY
* configuration has to be done through the TSEC1 MIIM regs
*/
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
int value)
{
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
uec_mii_t *ug_regs;
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
u32 tmp_reg;
#if defined(CONFIG_BITBANGMII)
u32 i = 0;
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
if (strncmp(dev->name, bitbang_phy_port[i],
sizeof(dev->name)) == 0) {
(void)bb_miiphy_write(NULL, mii_id, regnum, value);
return;
}
}
#endif /* CONFIG_BITBANGMII */
ug_regs = ugeth->uec_mii_regs;
/* Stop the MII management read cycle */
out_be32 (&ug_regs->miimcom, 0);
/* Setting up the MII Management Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* Setting up the MII Management Control Register with the value */
out_be32 (&ug_regs->miimcon, (u32)value);
sync();
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) & MIIMIND_BUSY)
;
}
/*
* Reads from register regnum in the PHY for device dev,
* returning the value. Clears miimcom first. All PHY
* configuration has to be done through the TSEC1 MIIM regs
*/
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum)
{
struct uec_priv *ugeth = (struct uec_priv *)dev->priv;
uec_mii_t *ug_regs;
enum enet_tbi_mii_reg mii_reg = (enum enet_tbi_mii_reg)regnum;
u32 tmp_reg;
u16 value;
#if defined(CONFIG_BITBANGMII)
u32 i = 0;
for (i = 0; i < ARRAY_SIZE(bitbang_phy_port); i++) {
if (strncmp(dev->name, bitbang_phy_port[i],
sizeof(dev->name)) == 0) {
(void)bb_miiphy_read(NULL, mii_id, regnum, &value);
return value;
}
}
#endif /* CONFIG_BITBANGMII */
ug_regs = ugeth->uec_mii_regs;
/* Setting up the MII Management Address Register */
tmp_reg = ((u32)mii_id << MIIMADD_PHY_ADDRESS_SHIFT) | mii_reg;
out_be32 (&ug_regs->miimadd, tmp_reg);
/* clear MII management command cycle */
out_be32 (&ug_regs->miimcom, 0);
sync();
/* Perform an MII management read cycle */
out_be32 (&ug_regs->miimcom, MIIMCOM_READ_CYCLE);
/* Wait till MII management write is complete */
while ((in_be32 (&ug_regs->miimind)) &
(MIIMIND_NOT_VALID | MIIMIND_BUSY))
;
/* Read MII management status */
value = (u16)in_be32 (&ug_regs->miimstat);
if (value == 0xffff)
ugphy_vdbg
("read wrong value : mii_id %d,mii_reg %d, base %08x",
mii_id, mii_reg, (u32)&ug_regs->miimcfg);
return value;
}
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info)
{
if (mii_info->phyinfo->ack_interrupt)
mii_info->phyinfo->ack_interrupt(mii_info);
}
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
u32 interrupts)
{
mii_info->interrupts = interrupts;
if (mii_info->phyinfo->config_intr)
mii_info->phyinfo->config_intr(mii_info);
}
/* Writes MII_ADVERTISE with the appropriate values, after
* sanitizing advertise to make sure only supported features
* are advertised
*/
static void config_genmii_advert(struct uec_mii_info *mii_info)
{
u32 advertise;
u16 adv;
/* Only allow advertising what this PHY supports */
mii_info->advertising &= mii_info->phyinfo->features;
advertise = mii_info->advertising;
/* Setup standard advertisement */
adv = uec_phy_read(mii_info, MII_ADVERTISE);
adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
if (advertise & ADVERTISED_10baseT_Half)
adv |= ADVERTISE_10HALF;
if (advertise & ADVERTISED_10baseT_Full)
adv |= ADVERTISE_10FULL;
if (advertise & ADVERTISED_100baseT_Half)
adv |= ADVERTISE_100HALF;
if (advertise & ADVERTISED_100baseT_Full)
adv |= ADVERTISE_100FULL;
uec_phy_write(mii_info, MII_ADVERTISE, adv);
}
static void genmii_setup_forced(struct uec_mii_info *mii_info)
{
u16 ctrl;
u32 features = mii_info->phyinfo->features;
ctrl = uec_phy_read(mii_info, MII_BMCR);
ctrl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 |
BMCR_SPEED1000 | BMCR_ANENABLE);
ctrl |= BMCR_RESET;
switch (mii_info->speed) {
case SPEED_1000:
if (features & (SUPPORTED_1000baseT_Half
| SUPPORTED_1000baseT_Full)) {
ctrl |= BMCR_SPEED1000;
break;
}
mii_info->speed = SPEED_100;
case SPEED_100:
if (features & (SUPPORTED_100baseT_Half
| SUPPORTED_100baseT_Full)) {
ctrl |= BMCR_SPEED100;
break;
}
mii_info->speed = SPEED_10;
case SPEED_10:
if (features & (SUPPORTED_10baseT_Half
| SUPPORTED_10baseT_Full))
break;
default: /* Unsupported speed! */
ugphy_err("%s: Bad speed!", mii_info->dev->name);
break;
}
uec_phy_write(mii_info, MII_BMCR, ctrl);
}
/* Enable and Restart Autonegotiation */
static void genmii_restart_aneg(struct uec_mii_info *mii_info)
{
u16 ctl;
ctl = uec_phy_read(mii_info, MII_BMCR);
ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
uec_phy_write(mii_info, MII_BMCR, ctl);
}
static int gbit_config_aneg(struct uec_mii_info *mii_info)
{
u16 adv;
u32 advertise;
if (mii_info->autoneg) {
/* Configure the ADVERTISE register */
config_genmii_advert(mii_info);
advertise = mii_info->advertising;
adv = uec_phy_read(mii_info, MII_CTRL1000);
adv &= ~(ADVERTISE_1000FULL |
ADVERTISE_1000HALF);
if (advertise & SUPPORTED_1000baseT_Half)
adv |= ADVERTISE_1000HALF;
if (advertise & SUPPORTED_1000baseT_Full)
adv |= ADVERTISE_1000FULL;
uec_phy_write(mii_info, MII_CTRL1000, adv);
/* Start/Restart aneg */
genmii_restart_aneg(mii_info);
} else {
genmii_setup_forced(mii_info);
}
return 0;
}
static int marvell_config_aneg(struct uec_mii_info *mii_info)
{
/*
* The Marvell PHY has an errata which requires
* that certain registers get written in order
* to restart autonegotiation
*/
uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
uec_phy_write(mii_info, 0x1d, 0x1f);
uec_phy_write(mii_info, 0x1e, 0x200c);
uec_phy_write(mii_info, 0x1d, 0x5);
uec_phy_write(mii_info, 0x1e, 0);
uec_phy_write(mii_info, 0x1e, 0x100);
gbit_config_aneg(mii_info);
return 0;
}
static int genmii_config_aneg(struct uec_mii_info *mii_info)
{
if (mii_info->autoneg) {
/*
* Speed up the common case, if link is already up, speed and
* duplex match, skip auto neg as it already matches
*/
if (!genmii_read_status(mii_info) && mii_info->link)
if (mii_info->duplex == DUPLEX_FULL &&
mii_info->speed == SPEED_100)
if (mii_info->advertising &
ADVERTISED_100baseT_Full)
return 0;
config_genmii_advert(mii_info);
genmii_restart_aneg(mii_info);
} else {
genmii_setup_forced(mii_info);
}
return 0;
}
static int genmii_update_link(struct uec_mii_info *mii_info)
{
u16 status;
/* Status is read once to clear old link state */
uec_phy_read(mii_info, MII_BMSR);
/*
* Wait if the link is up, and autonegotiation is in progress
* (ie - we're capable and it's not done)
*/
status = uec_phy_read(mii_info, MII_BMSR);
if ((status & BMSR_LSTATUS) && (status & BMSR_ANEGCAPABLE) &&
!(status & BMSR_ANEGCOMPLETE)) {
int i = 0;
while (!(status & BMSR_ANEGCOMPLETE)) {
/*
* Timeout reached ?
*/
if (i > UGETH_AN_TIMEOUT) {
mii_info->link = 0;
return 0;
}
i++;
udelay(1000); /* 1 ms */
status = uec_phy_read(mii_info, MII_BMSR);
}
mii_info->link = 1;
} else {
if (status & BMSR_LSTATUS)
mii_info->link = 1;
else
mii_info->link = 0;
}
return 0;
}
static int genmii_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
if (mii_info->autoneg) {
status = uec_phy_read(mii_info, MII_STAT1000);
if (status & (LPA_1000FULL | LPA_1000HALF)) {
mii_info->speed = SPEED_1000;
if (status & LPA_1000FULL)
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
} else {
status = uec_phy_read(mii_info, MII_LPA);
if (status & (LPA_10FULL | LPA_100FULL))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
if (status & (LPA_100FULL | LPA_100HALF))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
}
mii_info->pause = 0;
}
/* On non-aneg, we assume what we put in BMCR is the speed,
* though magic-aneg shouldn't prevent this case from occurring
*/
return 0;
}
static int bcm_init(struct uec_mii_info *mii_info)
{
struct eth_device *edev = mii_info->dev;
struct uec_priv *uec = edev->priv;
gbit_config_aneg(mii_info);
if (uec->uec_info->enet_interface_type ==
PHY_INTERFACE_MODE_RGMII_RXID &&
uec->uec_info->speed == SPEED_1000) {
u16 val;
int cnt = 50;
/* Wait for aneg to complete. */
do
val = uec_phy_read(mii_info, MII_BMSR);
while (--cnt && !(val & BMSR_ANEGCOMPLETE));
/* Set RDX clk delay. */
uec_phy_write(mii_info, 0x18, 0x7 | (7 << 12));
val = uec_phy_read(mii_info, 0x18);
/* Set RDX-RXC skew. */
val |= (1 << 8);
val |= (7 | (7 << 12));
/* Write bits 14:0. */
val |= (1 << 15);
uec_phy_write(mii_info, 0x18, val);
}
return 0;
}
static int uec_marvell_init(struct uec_mii_info *mii_info)
{
struct eth_device *edev = mii_info->dev;
struct uec_priv *uec = edev->priv;
phy_interface_t iface = uec->uec_info->enet_interface_type;
int speed = uec->uec_info->speed;
if (speed == SPEED_1000 &&
(iface == PHY_INTERFACE_MODE_RGMII_ID ||
iface == PHY_INTERFACE_MODE_RGMII_RXID ||
iface == PHY_INTERFACE_MODE_RGMII_TXID)) {
int temp;
temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_CR);
if (iface == PHY_INTERFACE_MODE_RGMII_ID) {
temp |= MII_M1111_RX_DELAY | MII_M1111_TX_DELAY;
} else if (iface == PHY_INTERFACE_MODE_RGMII_RXID) {
temp &= ~MII_M1111_TX_DELAY;
temp |= MII_M1111_RX_DELAY;
} else if (iface == PHY_INTERFACE_MODE_RGMII_TXID) {
temp &= ~MII_M1111_RX_DELAY;
temp |= MII_M1111_TX_DELAY;
}
uec_phy_write(mii_info, MII_M1111_PHY_EXT_CR, temp);
temp = uec_phy_read(mii_info, MII_M1111_PHY_EXT_SR);
temp &= ~MII_M1111_HWCFG_MODE_MASK;
temp |= MII_M1111_HWCFG_MODE_RGMII;
uec_phy_write(mii_info, MII_M1111_PHY_EXT_SR, temp);
uec_phy_write(mii_info, MII_BMCR, BMCR_RESET);
}
return 0;
}
static int marvell_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating, assume speeds
* are as set
*/
if (mii_info->autoneg && mii_info->link) {
int speed;
status = uec_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
/* Get the duplexity */
if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
/* Get the speed */
speed = status & MII_M1011_PHY_SPEC_STATUS_SPD_MASK;
switch (speed) {
case MII_M1011_PHY_SPEC_STATUS_1000:
mii_info->speed = SPEED_1000;
break;
case MII_M1011_PHY_SPEC_STATUS_100:
mii_info->speed = SPEED_100;
break;
default:
mii_info->speed = SPEED_10;
break;
}
mii_info->pause = 0;
}
return 0;
}
static int marvell_ack_interrupt(struct uec_mii_info *mii_info)
{
/* Clear the interrupts by reading the reg */
uec_phy_read(mii_info, MII_M1011_IEVENT);
return 0;
}
static int marvell_config_intr(struct uec_mii_info *mii_info)
{
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
uec_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
else
uec_phy_write(mii_info, MII_M1011_IMASK,
MII_M1011_IMASK_CLEAR);
return 0;
}
static int dm9161_init(struct uec_mii_info *mii_info)
{
/* Reset the PHY */
uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) |
BMCR_RESET);
/* PHY and MAC connect */
uec_phy_write(mii_info, MII_BMCR, uec_phy_read(mii_info, MII_BMCR) &
~BMCR_ISOLATE);
uec_phy_write(mii_info, MII_DM9161_SCR, MII_DM9161_SCR_INIT);
config_genmii_advert(mii_info);
/* Start/restart aneg */
genmii_config_aneg(mii_info);
return 0;
}
static int dm9161_config_aneg(struct uec_mii_info *mii_info)
{
return 0;
}
static int dm9161_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating assume speeds are as set
*/
if (mii_info->autoneg && mii_info->link) {
status = uec_phy_read(mii_info, MII_DM9161_SCSR);
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
mii_info->speed = SPEED_100;
else
mii_info->speed = SPEED_10;
if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_10F))
mii_info->duplex = DUPLEX_FULL;
else
mii_info->duplex = DUPLEX_HALF;
}
return 0;
}
static int dm9161_ack_interrupt(struct uec_mii_info *mii_info)
{
/* Clear the interrupt by reading the reg */
uec_phy_read(mii_info, MII_DM9161_INTR);
return 0;
}
static int dm9161_config_intr(struct uec_mii_info *mii_info)
{
if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
else
uec_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
return 0;
}
static void dm9161_close(struct uec_mii_info *mii_info)
{
}
static int fixed_phy_aneg(struct uec_mii_info *mii_info)
{
mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */
return 0;
}
static int fixed_phy_read_status(struct uec_mii_info *mii_info)
{
int i = 0;
for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
if (strncmp(mii_info->dev->name, fixed_phy_port[i].name,
strlen(mii_info->dev->name)) == 0) {
mii_info->speed = fixed_phy_port[i].speed;
mii_info->duplex = fixed_phy_port[i].duplex;
mii_info->link = 1; /* Link is always UP */
mii_info->pause = 0;
break;
}
}
return 0;
}
static int smsc_config_aneg(struct uec_mii_info *mii_info)
{
return 0;
}
static int smsc_read_status(struct uec_mii_info *mii_info)
{
u16 status;
int err;
/* Update the link, but return if there was an error */
err = genmii_update_link(mii_info);
if (err)
return err;
/*
* If the link is up, read the speed and duplex
* If we aren't autonegotiating, assume speeds
* are as set
*/
if (mii_info->autoneg && mii_info->link) {
int val;
status = uec_phy_read(mii_info, 0x1f);
val = (status & 0x1c) >> 2;
switch (val) {
case 1:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_10;
break;
case 5:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_10;
break;
case 2:
mii_info->duplex = DUPLEX_HALF;
mii_info->speed = SPEED_100;
break;
case 6:
mii_info->duplex = DUPLEX_FULL;
mii_info->speed = SPEED_100;
break;
}
mii_info->pause = 0;
}
return 0;
}
static struct phy_info phy_info_dm9161 = {
.phy_id = 0x0181b880,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161E",
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.close = dm9161_close,
};
static struct phy_info phy_info_dm9161a = {
.phy_id = 0x0181b8a0,
.phy_id_mask = 0x0ffffff0,
.name = "Davicom DM9161A",
.features = MII_BASIC_FEATURES,
.init = dm9161_init,
.config_aneg = dm9161_config_aneg,
.read_status = dm9161_read_status,
.ack_interrupt = dm9161_ack_interrupt,
.config_intr = dm9161_config_intr,
.close = dm9161_close,
};
static struct phy_info phy_info_marvell = {
.phy_id = 0x01410c00,
.phy_id_mask = 0xffffff00,
.name = "Marvell 88E11x1",
.features = MII_GBIT_FEATURES,
.init = &uec_marvell_init,
.config_aneg = &marvell_config_aneg,
.read_status = &marvell_read_status,
.ack_interrupt = &marvell_ack_interrupt,
.config_intr = &marvell_config_intr,
};
static struct phy_info phy_info_bcm5481 = {
.phy_id = 0x0143bca0,
.phy_id_mask = 0xffffff0,
.name = "Broadcom 5481",
.features = MII_GBIT_FEATURES,
.read_status = genmii_read_status,
.init = bcm_init,
};
static struct phy_info phy_info_fixedphy = {
.phy_id = CONFIG_FIXED_PHY,
.phy_id_mask = CONFIG_FIXED_PHY,
.name = "Fixed PHY",
.config_aneg = fixed_phy_aneg,
.read_status = fixed_phy_read_status,
};
static struct phy_info phy_info_smsclan8700 = {
.phy_id = 0x0007c0c0,
.phy_id_mask = 0xfffffff0,
.name = "SMSC LAN8700",
.features = MII_BASIC_FEATURES,
.config_aneg = smsc_config_aneg,
.read_status = smsc_read_status,
};
static struct phy_info phy_info_genmii = {
.phy_id = 0x00000000,
.phy_id_mask = 0x00000000,
.name = "Generic MII",
.features = MII_BASIC_FEATURES,
.config_aneg = genmii_config_aneg,
.read_status = genmii_read_status,
};
static struct phy_info *phy_info[] = {
&phy_info_dm9161,
&phy_info_dm9161a,
&phy_info_marvell,
&phy_info_bcm5481,
&phy_info_smsclan8700,
&phy_info_fixedphy,
&phy_info_genmii,
NULL
};
static u16 uec_phy_read(struct uec_mii_info *mii_info, u16 regnum)
{
return mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
}
static void uec_phy_write(struct uec_mii_info *mii_info, u16 regnum, u16 val)
{
mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
}
/* Use the PHY ID registers to determine what type of PHY is attached
* to device dev. return a struct phy_info structure describing that PHY
*/
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info)
{
u16 phy_reg;
u32 phy_ID;
int i;
struct phy_info *info = NULL;
/* Grab the bits from PHYIR1, and put them in the upper half */
phy_reg = uec_phy_read(mii_info, MII_PHYSID1);
phy_ID = (phy_reg & 0xffff) << 16;
/* Grab the bits from PHYIR2, and put them in the lower half */
phy_reg = uec_phy_read(mii_info, MII_PHYSID2);
phy_ID |= (phy_reg & 0xffff);
/* loop through all the known PHY types, and find one that */
/* matches the ID we read from the PHY. */
for (i = 0; phy_info[i]; i++)
if (phy_info[i]->phy_id ==
(phy_ID & phy_info[i]->phy_id_mask)) {
info = phy_info[i];
break;
}
/* This shouldn't happen, as we have generic PHY support */
if (!info) {
ugphy_info("UEC: PHY id %x is not supported!", phy_ID);
return NULL;
}
ugphy_info("UEC: PHY is %s (%x)", info->name, phy_ID);
return info;
}
void marvell_phy_interface_mode(struct eth_device *dev, phy_interface_t type,
int speed)
{
struct uec_priv *uec = (struct uec_priv *)dev->priv;
struct uec_mii_info *mii_info;
u16 status;
if (!uec->mii_info) {
printf("%s: the PHY not initialized\n", __func__);
return;
}
mii_info = uec->mii_info;
if (type == PHY_INTERFACE_MODE_RGMII) {
if (speed == SPEED_100) {
uec_phy_write(mii_info, 0x00, 0x9140);
uec_phy_write(mii_info, 0x1d, 0x001f);
uec_phy_write(mii_info, 0x1e, 0x200c);
uec_phy_write(mii_info, 0x1d, 0x0005);
uec_phy_write(mii_info, 0x1e, 0x0000);
uec_phy_write(mii_info, 0x1e, 0x0100);
uec_phy_write(mii_info, 0x09, 0x0e00);
uec_phy_write(mii_info, 0x04, 0x01e1);
uec_phy_write(mii_info, 0x00, 0x9140);
uec_phy_write(mii_info, 0x00, 0x1000);
mdelay(100);
uec_phy_write(mii_info, 0x00, 0x2900);
uec_phy_write(mii_info, 0x14, 0x0cd2);
uec_phy_write(mii_info, 0x00, 0xa100);
uec_phy_write(mii_info, 0x09, 0x0000);
uec_phy_write(mii_info, 0x1b, 0x800b);
uec_phy_write(mii_info, 0x04, 0x05e1);
uec_phy_write(mii_info, 0x00, 0xa100);
uec_phy_write(mii_info, 0x00, 0x2100);
mdelay(1000);
} else if (speed == SPEED_10) {
uec_phy_write(mii_info, 0x14, 0x8e40);
uec_phy_write(mii_info, 0x1b, 0x800b);
uec_phy_write(mii_info, 0x14, 0x0c82);
uec_phy_write(mii_info, 0x00, 0x8100);
mdelay(1000);
}
}
/* handle 88e1111 rev.B2 erratum 5.6 */
if (mii_info->autoneg) {
status = uec_phy_read(mii_info, MII_BMCR);
uec_phy_write(mii_info, MII_BMCR, status | BMCR_ANENABLE);
}
/* now the B2 will correctly report autoneg completion status */
}
void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t type, int speed)
{
#ifdef CONFIG_PHY_MODE_NEED_CHANGE
marvell_phy_interface_mode(dev, type, speed);
#endif
}
#endif

214
drivers/qe/uec_phy.h
View File

@ -1,214 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2005, 2011 Freescale Semiconductor, Inc.
*
* Author: Shlomi Gridish <gridish@freescale.com>
*
* Description: UCC ethernet driver -- PHY handling
* Driver for UEC on QE
* Based on 8260_io/fcc_enet.c
*/
#ifndef __UEC_PHY_H__
#define __UEC_PHY_H__
#include <linux/bitops.h>
#define MII_end ((u32)-2)
#define MII_read ((u32)-1)
#define MIIMIND_BUSY 0x00000001
#define MIIMIND_NOTVALID 0x00000004
#define UGETH_AN_TIMEOUT 2000
/* Cicada Extended Control Register 1 */
#define MII_CIS8201_EXT_CON1 0x17
#define MII_CIS8201_EXTCON1_INIT 0x0000
/* Cicada Interrupt Mask Register */
#define MII_CIS8201_IMASK 0x19
#define MII_CIS8201_IMASK_IEN 0x8000
#define MII_CIS8201_IMASK_SPEED 0x4000
#define MII_CIS8201_IMASK_LINK 0x2000
#define MII_CIS8201_IMASK_DUPLEX 0x1000
#define MII_CIS8201_IMASK_MASK 0xf000
/* Cicada Interrupt Status Register */
#define MII_CIS8201_ISTAT 0x1a
#define MII_CIS8201_ISTAT_STATUS 0x8000
#define MII_CIS8201_ISTAT_SPEED 0x4000
#define MII_CIS8201_ISTAT_LINK 0x2000
#define MII_CIS8201_ISTAT_DUPLEX 0x1000
/* Cicada Auxiliary Control/Status Register */
#define MII_CIS8201_AUX_CONSTAT 0x1c
#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
#define MII_CIS8201_AUXCONSTAT_100 0x0008
/* 88E1011 PHY Status Register */
#define MII_M1011_PHY_SPEC_STATUS 0x11
#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
#define MII_M1011_IEVENT 0x13
#define MII_M1011_IEVENT_CLEAR 0x0000
#define MII_M1011_IMASK 0x12
#define MII_M1011_IMASK_INIT 0x6400
#define MII_M1011_IMASK_CLEAR 0x0000
/* 88E1111 PHY Register */
#define MII_M1111_PHY_EXT_CR 0x14
#define MII_M1111_RX_DELAY 0x80
#define MII_M1111_TX_DELAY 0x2
#define MII_M1111_PHY_EXT_SR 0x1b
#define MII_M1111_HWCFG_MODE_MASK 0xf
#define MII_M1111_HWCFG_MODE_RGMII 0xb
#define MII_DM9161_SCR 0x10
#define MII_DM9161_SCR_INIT 0x0610
#define MII_DM9161_SCR_RMII_INIT 0x0710
/* DM9161 Specified Configuration and Status Register */
#define MII_DM9161_SCSR 0x11
#define MII_DM9161_SCSR_100F 0x8000
#define MII_DM9161_SCSR_100H 0x4000
#define MII_DM9161_SCSR_10F 0x2000
#define MII_DM9161_SCSR_10H 0x1000
/* DM9161 Interrupt Register */
#define MII_DM9161_INTR 0x15
#define MII_DM9161_INTR_PEND 0x8000
#define MII_DM9161_INTR_DPLX_MASK 0x0800
#define MII_DM9161_INTR_SPD_MASK 0x0400
#define MII_DM9161_INTR_LINK_MASK 0x0200
#define MII_DM9161_INTR_MASK 0x0100
#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
#define MII_DM9161_INTR_SPD_CHANGE 0x0008
#define MII_DM9161_INTR_LINK_CHANGE 0x0004
#define MII_DM9161_INTR_INIT 0x0000
#define MII_DM9161_INTR_STOP \
(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK | \
MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
/* DM9161 10BT Configuration/Status */
#define MII_DM9161_10BTCSR 0x12
#define MII_DM9161_10BTCSR_INIT 0x7800
#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
SUPPORTED_10baseT_Full | \
SUPPORTED_100baseT_Half | \
SUPPORTED_100baseT_Full | \
SUPPORTED_Autoneg | \
SUPPORTED_TP | \
SUPPORTED_MII)
#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
SUPPORTED_1000baseT_Half | \
SUPPORTED_1000baseT_Full)
#define MII_READ_COMMAND 0x00000001
#define MII_INTERRUPT_DISABLED 0x0
#define MII_INTERRUPT_ENABLED 0x1
#define SPEED_10 10
#define SPEED_100 100
#define SPEED_1000 1000
/* Duplex, half or full. */
#define DUPLEX_HALF 0x00
#define DUPLEX_FULL 0x01
/* Taken from mii_if_info and sungem_phy.h */
struct uec_mii_info {
/* Information about the PHY type */
/* And management functions */
struct phy_info *phyinfo;
struct eth_device *dev;
/* forced speed & duplex (no autoneg)
* partner speed & duplex & pause (autoneg)
*/
int speed;
int duplex;
int pause;
/* The most recently read link state */
int link;
/* Enabled Interrupts */
u32 interrupts;
u32 advertising;
int autoneg;
int mii_id;
/* private data pointer */
/* For use by PHYs to maintain extra state */
void *priv;
/* Provided by ethernet driver */
int (*mdio_read)(struct eth_device *dev, int mii_id, int reg);
void (*mdio_write)(struct eth_device *dev, int mii_id, int reg,
int val);
};
/* struct phy_info: a structure which defines attributes for a PHY
*
* id will contain a number which represents the PHY. During
* startup, the driver will poll the PHY to find out what its
* UID--as defined by registers 2 and 3--is. The 32-bit result
* gotten from the PHY will be ANDed with phy_id_mask to
* discard any bits which may change based on revision numbers
* unimportant to functionality
*
* There are 6 commands which take a ugeth_mii_info structure.
* Each PHY must declare config_aneg, and read_status.
*/
struct phy_info {
u32 phy_id;
char *name;
unsigned int phy_id_mask;
u32 features;
/* Called to initialize the PHY */
int (*init)(struct uec_mii_info *mii_info);
/* Called to suspend the PHY for power */
int (*suspend)(struct uec_mii_info *mii_info);
/* Reconfigures autonegotiation (or disables it) */
int (*config_aneg)(struct uec_mii_info *mii_info);
/* Determines the negotiated speed and duplex */
int (*read_status)(struct uec_mii_info *mii_info);
/* Clears any pending interrupts */
int (*ack_interrupt)(struct uec_mii_info *mii_info);
/* Enables or disables interrupts */
int (*config_intr)(struct uec_mii_info *mii_info);
/* Clears up any memory if needed */
void (*close)(struct uec_mii_info *mii_info);
};
struct phy_info *uec_get_phy_info(struct uec_mii_info *mii_info);
void uec_write_phy_reg(struct eth_device *dev, int mii_id, int regnum,
int value);
int uec_read_phy_reg(struct eth_device *dev, int mii_id, int regnum);
void mii_clear_phy_interrupt(struct uec_mii_info *mii_info);
void mii_configure_phy_interrupt(struct uec_mii_info *mii_info,
u32 interrupts);
void change_phy_interface_mode(struct eth_device *dev,
phy_interface_t type, int speed);
#endif /* __UEC_PHY_H__ */

255
drivers/usb/eth/asix.c
View File

@ -101,16 +101,9 @@
/* driver private */
struct asix_private {
int flags;
#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
#endif
};
#ifndef CONFIG_DM_ETH
/* local vars */
static int curr_eth_dev; /* index for name of next device detected */
#endif
/*
* Asix infrastructure commands
*/
@ -494,253 +487,6 @@ static int asix_send_common(struct ueth_data *dev, void *packet, int length)
return err;
}
#ifndef CONFIG_DM_ETH
/*
* Asix callbacks
*/
static int asix_init(struct eth_device *eth, struct bd_info *bd)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return asix_init_common(dev, eth->enetaddr);
}
static int asix_send(struct eth_device *eth, void *packet, int length)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return asix_send_common(dev, packet, length);
}
static int asix_recv(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
unsigned char *buf_ptr;
int err;
int actual_len;
u32 packet_len;
debug("** %s()\n", __func__);
err = usb_bulk_msg(dev->pusb_dev,
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
(void *)recv_buf,
AX_RX_URB_SIZE,
&actual_len,
USB_BULK_RECV_TIMEOUT);
debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
actual_len, err);
if (err != 0) {
debug("Rx: failed to receive\n");
return -1;
}
if (actual_len > AX_RX_URB_SIZE) {
debug("Rx: received too many bytes %d\n", actual_len);
return -1;
}
buf_ptr = recv_buf;
while (actual_len > 0) {
/*
* 1st 4 bytes contain the length of the actual data as two
* complementary 16-bit words. Extract the length of the data.
*/
if (actual_len < sizeof(packet_len)) {
debug("Rx: incomplete packet length\n");
return -1;
}
memcpy(&packet_len, buf_ptr, sizeof(packet_len));
le32_to_cpus(&packet_len);
if (((~packet_len >> 16) & 0x7ff) != (packet_len & 0x7ff)) {
debug("Rx: malformed packet length: %#x (%#x:%#x)\n",
packet_len, (~packet_len >> 16) & 0x7ff,
packet_len & 0x7ff);
return -1;
}
packet_len = packet_len & 0x7ff;
if (packet_len > actual_len - sizeof(packet_len)) {
debug("Rx: too large packet: %d\n", packet_len);
return -1;
}
/* Notify net stack */
net_process_received_packet(buf_ptr + sizeof(packet_len),
packet_len);
/* Adjust for next iteration. Packets are padded to 16-bits */
if (packet_len & 1)
packet_len++;
actual_len -= sizeof(packet_len) + packet_len;
buf_ptr += sizeof(packet_len) + packet_len;
}
return err;
}
static void asix_halt(struct eth_device *eth)
{
debug("** %s()\n", __func__);
}
static int asix_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return asix_write_hwaddr_common(dev, eth->enetaddr);
}
/*
* Asix probing functions
*/
void asix_eth_before_probe(void)
{
curr_eth_dev = 0;
}
struct asix_dongle {
unsigned short vendor;
unsigned short product;
int flags;
};
static const struct asix_dongle asix_dongles[] = {
{ 0x05ac, 0x1402, FLAG_TYPE_AX88772 }, /* Apple USB Ethernet Adapter */
{ 0x07d1, 0x3c05, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver B1 */
{ 0x2001, 0x1a02, FLAG_TYPE_AX88772 }, /* D-Link DUB-E100 H/W Ver C1 */
/* Cables-to-Go USB Ethernet Adapter */
{ 0x0b95, 0x772a, FLAG_TYPE_AX88772 },
{ 0x0b95, 0x7720, FLAG_TYPE_AX88772 }, /* Trendnet TU2-ET100 V3.0R */
{ 0x0b95, 0x1720, FLAG_TYPE_AX88172 }, /* SMC */
{ 0x0db0, 0xa877, FLAG_TYPE_AX88772 }, /* MSI - ASIX 88772a */
{ 0x13b1, 0x0018, FLAG_TYPE_AX88172 }, /* Linksys 200M v2.1 */
{ 0x1557, 0x7720, FLAG_TYPE_AX88772 }, /* 0Q0 cable ethernet */
/* DLink DUB-E100 H/W Ver B1 Alternate */
{ 0x2001, 0x3c05, FLAG_TYPE_AX88772 },
/* ASIX 88772B */
{ 0x0b95, 0x772b, FLAG_TYPE_AX88772B | FLAG_EEPROM_MAC },
{ 0x0b95, 0x7e2b, FLAG_TYPE_AX88772B },
{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
};
/* Probe to see if a new device is actually an asix device */
int asix_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss)
{
struct usb_interface *iface;
struct usb_interface_descriptor *iface_desc;
int ep_in_found = 0, ep_out_found = 0;
int i;
/* let's examine the device now */
iface = &dev->config.if_desc[ifnum];
iface_desc = &dev->config.if_desc[ifnum].desc;
for (i = 0; asix_dongles[i].vendor != 0; i++) {
if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
dev->descriptor.idProduct == asix_dongles[i].product)
/* Found a supported dongle */
break;
}
if (asix_dongles[i].vendor == 0)
return 0;
memset(ss, 0, sizeof(struct ueth_data));
/* At this point, we know we've got a live one */
debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* Initialize the ueth_data structure with some useful info */
ss->ifnum = ifnum;
ss->pusb_dev = dev;
ss->subclass = iface_desc->bInterfaceSubClass;
ss->protocol = iface_desc->bInterfaceProtocol;
/* alloc driver private */
ss->dev_priv = calloc(1, sizeof(struct asix_private));
if (!ss->dev_priv)
return 0;
((struct asix_private *)ss->dev_priv)->flags = asix_dongles[i].flags;
/*
* We are expecting a minimum of 3 endpoints - in, out (bulk), and
* int. We will ignore any others.
*/
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
/* is it an BULK endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
if (ep_addr & USB_DIR_IN) {
if (!ep_in_found) {
ss->ep_in = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
ep_in_found = 1;
}
} else {
if (!ep_out_found) {
ss->ep_out = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
ep_out_found = 1;
}
}
}
/* is it an interrupt endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
ss->irqinterval = iface->ep_desc[i].bInterval;
}
}
debug("Endpoints In %d Out %d Int %d\n",
ss->ep_in, ss->ep_out, ss->ep_int);
/* Do some basic sanity checks, and bail if we find a problem */
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
debug("Problems with device\n");
return 0;
}
dev->privptr = (void *)ss;
return 1;
}
int asix_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth)
{
struct asix_private *priv = (struct asix_private *)ss->dev_priv;
if (!eth) {
debug("%s: missing parameter.\n", __func__);
return 0;
}
sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
eth->init = asix_init;
eth->send = asix_send;
eth->recv = asix_recv;
eth->halt = asix_halt;
if (!(priv->flags & FLAG_TYPE_AX88172))
eth->write_hwaddr = asix_write_hwaddr;
eth->priv = ss;
if (asix_basic_reset(ss))
return 0;
/* Get the MAC address */
if (asix_read_mac_common(ss, priv, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
#endif
#ifdef CONFIG_DM_ETH
static int asix_eth_start(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
@ -909,4 +655,3 @@ static const struct usb_device_id asix_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(asix_eth, asix_eth_id_table);
#endif

250
drivers/usb/eth/asix88179.c
View File

@ -199,18 +199,12 @@ static const struct {
{7, 0xcc, 0x4c, 0x04, 8},
};
#ifndef CONFIG_DM_ETH
static int curr_eth_dev; /* index for name of next device detected */
#endif
/* driver private */
struct asix_private {
#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
unsigned pkt_cnt;
uint8_t *pkt_data;
uint32_t *pkt_hdr;
#endif
int flags;
int rx_urb_size;
int maxpacketsize;
@ -505,249 +499,6 @@ static int asix_send_common(struct ueth_data *dev,
return err;
}
#ifndef CONFIG_DM_ETH
/*
* Asix callbacks
*/
static int asix_init(struct eth_device *eth, struct bd_info *bd)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
return asix_init_common(dev, dev_priv);
}
static int asix_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return asix_write_mac(dev, eth->enetaddr);
}
static int asix_send(struct eth_device *eth, void *packet, int length)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
return asix_send_common(dev, dev_priv, packet, length);
}
static int asix_recv(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct asix_private *dev_priv = (struct asix_private *)dev->dev_priv;
u16 frame_pos;
int err;
int actual_len;
int pkt_cnt;
u32 rx_hdr;
u16 hdr_off;
u32 *pkt_hdr;
ALLOC_CACHE_ALIGN_BUFFER(u8, recv_buf, dev_priv->rx_urb_size);
actual_len = -1;
debug("** %s()\n", __func__);
err = usb_bulk_msg(dev->pusb_dev,
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
(void *)recv_buf,
dev_priv->rx_urb_size,
&actual_len,
USB_BULK_RECV_TIMEOUT);
debug("Rx: len = %u, actual = %u, err = %d\n", dev_priv->rx_urb_size,
actual_len, err);
if (err != 0) {
debug("Rx: failed to receive\n");
return -ECOMM;
}
if (actual_len > dev_priv->rx_urb_size) {
debug("Rx: received too many bytes %d\n", actual_len);
return -EMSGSIZE;
}
rx_hdr = *(u32 *)(recv_buf + actual_len - 4);
le32_to_cpus(&rx_hdr);
pkt_cnt = (u16)rx_hdr;
hdr_off = (u16)(rx_hdr >> 16);
pkt_hdr = (u32 *)(recv_buf + hdr_off);
frame_pos = 0;
while (pkt_cnt--) {
u16 pkt_len;
le32_to_cpus(pkt_hdr);
pkt_len = (*pkt_hdr >> 16) & 0x1fff;
frame_pos += 2;
net_process_received_packet(recv_buf + frame_pos, pkt_len);
pkt_hdr++;
frame_pos += ((pkt_len + 7) & 0xFFF8)-2;
if (pkt_cnt == 0)
return 0;
}
return err;
}
static void asix_halt(struct eth_device *eth)
{
debug("** %s()\n", __func__);
}
/*
* Asix probing functions
*/
void ax88179_eth_before_probe(void)
{
curr_eth_dev = 0;
}
struct asix_dongle {
unsigned short vendor;
unsigned short product;
int flags;
};
static const struct asix_dongle asix_dongles[] = {
{ 0x0b95, 0x1790, FLAG_TYPE_AX88179 },
{ 0x0b95, 0x178a, FLAG_TYPE_AX88178a },
{ 0x2001, 0x4a00, FLAG_TYPE_DLINK_DUB1312 },
{ 0x0df6, 0x0072, FLAG_TYPE_SITECOM },
{ 0x04e8, 0xa100, FLAG_TYPE_SAMSUNG },
{ 0x17ef, 0x304b, FLAG_TYPE_LENOVO },
{ 0x04b4, 0x3610, FLAG_TYPE_GX3 },
{ 0x0000, 0x0000, FLAG_NONE } /* END - Do not remove */
};
/* Probe to see if a new device is actually an asix device */
int ax88179_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss)
{
struct usb_interface *iface;
struct usb_interface_descriptor *iface_desc;
struct asix_private *dev_priv;
int ep_in_found = 0, ep_out_found = 0;
int i;
/* let's examine the device now */
iface = &dev->config.if_desc[ifnum];
iface_desc = &dev->config.if_desc[ifnum].desc;
for (i = 0; asix_dongles[i].vendor != 0; i++) {
if (dev->descriptor.idVendor == asix_dongles[i].vendor &&
dev->descriptor.idProduct == asix_dongles[i].product)
/* Found a supported dongle */
break;
}
if (asix_dongles[i].vendor == 0)
return 0;
memset(ss, 0, sizeof(struct ueth_data));
/* At this point, we know we've got a live one */
debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* Initialize the ueth_data structure with some useful info */
ss->ifnum = ifnum;
ss->pusb_dev = dev;
ss->subclass = iface_desc->bInterfaceSubClass;
ss->protocol = iface_desc->bInterfaceProtocol;
/* alloc driver private */
ss->dev_priv = calloc(1, sizeof(struct asix_private));
if (!ss->dev_priv)
return 0;
dev_priv = ss->dev_priv;
dev_priv->flags = asix_dongles[i].flags;
/*
* We are expecting a minimum of 3 endpoints - in, out (bulk), and
* int. We will ignore any others.
*/
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
/* is it an interrupt endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
ss->irqinterval = iface->ep_desc[i].bInterval;
continue;
}
/* is it an BULK endpoint? */
if (!((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK))
continue;
u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
if ((ep_addr & USB_DIR_IN) && !ep_in_found) {
ss->ep_in = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
ep_in_found = 1;
}
if (!(ep_addr & USB_DIR_IN) && !ep_out_found) {
ss->ep_out = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
dev_priv->maxpacketsize =
dev->epmaxpacketout[AX_ENDPOINT_OUT];
ep_out_found = 1;
}
}
debug("Endpoints In %d Out %d Int %d\n",
ss->ep_in, ss->ep_out, ss->ep_int);
/* Do some basic sanity checks, and bail if we find a problem */
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
debug("Problems with device\n");
return 0;
}
dev->privptr = (void *)ss;
return 1;
}
int ax88179_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth)
{
struct asix_private *dev_priv = (struct asix_private *)ss->dev_priv;
if (!eth) {
debug("%s: missing parameter.\n", __func__);
return 0;
}
sprintf(eth->name, "%s%d", ASIX_BASE_NAME, curr_eth_dev++);
eth->init = asix_init;
eth->send = asix_send;
eth->recv = asix_recv;
eth->halt = asix_halt;
eth->write_hwaddr = asix_write_hwaddr;
eth->priv = ss;
if (asix_basic_reset(ss, dev_priv))
return 0;
/* Get the MAC address */
if (asix_read_mac(ss, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
#else /* !CONFIG_DM_ETH */
static int ax88179_eth_start(struct udevice *dev)
{
struct asix_private *priv = dev_get_priv(dev);
@ -918,4 +669,3 @@ static const struct usb_device_id ax88179_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(ax88179_eth, ax88179_eth_id_table);
#endif /* !CONFIG_DM_ETH */

276
drivers/usb/eth/mcs7830.c
View File

@ -86,10 +86,8 @@ struct mcs7830_regs {
* @mchash: shadow for the network adapter's multicast hash registers
*/
struct mcs7830_private {
#ifdef CONFIG_DM_ETH
uint8_t rx_buf[MCS7830_RX_URB_SIZE];
struct ueth_data ueth;
#endif
uint8_t config;
uint8_t mchash[8];
};
@ -575,279 +573,6 @@ static int mcs7830_recv_common(struct ueth_data *ueth, uint8_t *buf)
return -EIO;
}
#ifndef CONFIG_DM_ETH
/*
* mcs7830_init() - network interface's init callback
* @udev: network device to initialize
* @bd: board information
* Return: zero upon success, negative upon error
*
* after initial setup during probe() and get_info(), this init() callback
* ensures that the link is up and subsequent send() and recv() calls can
* exchange ethernet frames
*/
static int mcs7830_init(struct eth_device *eth, struct bd_info *bd)
{
struct ueth_data *dev = eth->priv;
return mcs7830_init_common(dev->pusb_dev);
}
/*
* mcs7830_send() - network interface's send callback
* @eth: network device to send the frame from
* @packet: ethernet frame content
* @length: ethernet frame length
* Return: zero upon success, negative upon error
*
* this routine send an ethernet frame out of the network interface
*/
static int mcs7830_send(struct eth_device *eth, void *packet, int length)
{
struct ueth_data *dev = eth->priv;
return mcs7830_send_common(dev, packet, length);
}
/*
* mcs7830_recv() - network interface's recv callback
* @eth: network device to receive frames from
* Return: zero upon success, negative upon error
*
* this routine checks for available ethernet frames that the network
* interface might have received, and notifies the network stack
*/
static int mcs7830_recv(struct eth_device *eth)
{
ALLOC_CACHE_ALIGN_BUFFER(uint8_t, buf, MCS7830_RX_URB_SIZE);
struct ueth_data *ueth = eth->priv;
int len;
len = mcs7830_recv_common(ueth, buf);
if (len >= 0) {
net_process_received_packet(buf, len);
return 0;
}
return len;
}
/*
* mcs7830_halt() - network interface's halt callback
* @eth: network device to cease operation of
* Return: none
*
* this routine is supposed to undo the effect of previous initialization and
* ethernet frames exchange; in this implementation it's a NOP
*/
static void mcs7830_halt(struct eth_device *eth)
{
debug("%s()\n", __func__);
}
/*
* mcs7830_write_mac() - write an ethernet adapter's MAC address
* @eth: network device to write to
* Return: zero upon success, negative upon error
*
* this routine takes the MAC address from the ethernet interface's data
* structure, and writes it into the ethernet adapter such that subsequent
* exchange of ethernet frames uses this address
*/
static int mcs7830_write_mac(struct eth_device *eth)
{
struct ueth_data *ueth = eth->priv;
return mcs7830_write_mac_common(ueth->pusb_dev, eth->enetaddr);
}
/*
* mcs7830_iface_idx - index of detected network interfaces
*
* this counter keeps track of identified supported interfaces,
* to assign unique names as more interfaces are found
*/
static int mcs7830_iface_idx;
/*
* mcs7830_eth_before_probe() - network driver's before_probe callback
* Return: none
*
* this routine initializes driver's internal data in preparation of
* subsequent probe callbacks
*/
void mcs7830_eth_before_probe(void)
{
mcs7830_iface_idx = 0;
}
/*
* struct mcs7830_dongle - description of a supported Moschip ethernet dongle
* @vendor: 16bit USB vendor identification
* @product: 16bit USB product identification
*
* this structure describes a supported USB ethernet dongle by means of the
* vendor and product codes found during USB enumeration; no flags are held
* here since all supported dongles have identical behaviour, and required
* fixups get determined at runtime, such that no manual configuration is
* needed
*/
struct mcs7830_dongle {
uint16_t vendor;
uint16_t product;
};
/*
* mcs7830_dongles - the list of supported Moschip based USB ethernet dongles
*/
static const struct mcs7830_dongle mcs7830_dongles[] = {
{ 0x9710, 0x7832, }, /* Moschip 7832 */
{ 0x9710, 0x7830, }, /* Moschip 7830 */
{ 0x9710, 0x7730, }, /* Moschip 7730 */
{ 0x0df6, 0x0021, }, /* Sitecom LN 30 */
};
/*
* mcs7830_eth_probe() - network driver's probe callback
* @dev: detected USB device to check
* @ifnum: detected USB interface to check
* @ss: USB ethernet data structure to fill in upon match
* Return: #1 upon match, #0 upon mismatch or error
*
* this routine checks whether the found USB device is supported by
* this ethernet driver, and upon match fills in the USB ethernet
* data structure which later is passed to the get_info callback
*/
int mcs7830_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss)
{
struct usb_interface *iface;
struct usb_interface_descriptor *iface_desc;
int i;
struct mcs7830_private *priv;
int ep_in_found, ep_out_found, ep_intr_found;
debug("%s()\n", __func__);
/* iterate the list of supported dongles */
iface = &dev->config.if_desc[ifnum];
iface_desc = &iface->desc;
for (i = 0; i < ARRAY_SIZE(mcs7830_dongles); i++) {
if (dev->descriptor.idVendor == mcs7830_dongles[i].vendor &&
dev->descriptor.idProduct == mcs7830_dongles[i].product)
break;
}
if (i == ARRAY_SIZE(mcs7830_dongles))
return 0;
debug("detected USB ethernet device: %04X:%04X\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* fill in driver private data */
priv = calloc(1, sizeof(*priv));
if (!priv)
return 0;
/* fill in the ueth_data structure, attach private data */
memset(ss, 0, sizeof(*ss));
ss->ifnum = ifnum;
ss->pusb_dev = dev;
ss->subclass = iface_desc->bInterfaceSubClass;
ss->protocol = iface_desc->bInterfaceProtocol;
ss->dev_priv = priv;
/*
* a minimum of three endpoints is expected: in (bulk),
* out (bulk), and interrupt; ignore all others
*/
ep_in_found = ep_out_found = ep_intr_found = 0;
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
uint8_t eptype, epaddr;
bool is_input;
eptype = iface->ep_desc[i].bmAttributes;
eptype &= USB_ENDPOINT_XFERTYPE_MASK;
epaddr = iface->ep_desc[i].bEndpointAddress;
is_input = epaddr & USB_DIR_IN;
epaddr &= USB_ENDPOINT_NUMBER_MASK;
if (eptype == USB_ENDPOINT_XFER_BULK) {
if (is_input && !ep_in_found) {
ss->ep_in = epaddr;
ep_in_found++;
}
if (!is_input && !ep_out_found) {
ss->ep_out = epaddr;
ep_out_found++;
}
}
if (eptype == USB_ENDPOINT_XFER_INT) {
if (is_input && !ep_intr_found) {
ss->ep_int = epaddr;
ss->irqinterval = iface->ep_desc[i].bInterval;
ep_intr_found++;
}
}
}
debug("endpoints: in %d, out %d, intr %d\n",
ss->ep_in, ss->ep_out, ss->ep_int);
/* apply basic sanity checks */
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
debug("device probe incomplete\n");
return 0;
}
dev->privptr = ss;
return 1;
}
/*
* mcs7830_eth_get_info() - network driver's get_info callback
* @dev: detected USB device
* @ss: USB ethernet data structure filled in at probe()
* @eth: ethernet interface data structure to fill in
* Return: #1 upon success, #0 upon error
*
* this routine registers the mandatory init(), send(), recv(), and
* halt() callbacks with the ethernet interface, can register the
* optional write_hwaddr() callback with the ethernet interface,
* and initiates configuration of the interface such that subsequent
* calls to those callbacks results in network communication
*/
int mcs7830_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth)
{
debug("%s()\n", __func__);
if (!eth) {
debug("%s: missing parameter.\n", __func__);
return 0;
}
snprintf(eth->name, sizeof(eth->name), "%s%d",
MCS7830_BASE_NAME, mcs7830_iface_idx++);
eth->init = mcs7830_init;
eth->send = mcs7830_send;
eth->recv = mcs7830_recv;
eth->halt = mcs7830_halt;
eth->write_hwaddr = mcs7830_write_mac;
eth->priv = ss;
if (mcs7830_basic_reset(ss->pusb_dev, ss->dev_priv))
return 0;
if (mcs7830_read_mac(ss->pusb_dev, eth->enetaddr))
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
#endif
#ifdef CONFIG_DM_ETH
static int mcs7830_eth_start(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
@ -942,4 +667,3 @@ static const struct usb_device_id mcs7830_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(mcs7830_eth, mcs7830_eth_id_table);
#endif

275
drivers/usb/eth/r8152.c
View File

@ -18,43 +18,6 @@
#include "usb_ether.h"
#include "r8152.h"
#ifndef CONFIG_DM_ETH
/* local vars */
static int curr_eth_dev; /* index for name of next device detected */
struct r8152_dongle {
unsigned short vendor;
unsigned short product;
};
static const struct r8152_dongle r8152_dongles[] = {
/* Realtek */
{ 0x0bda, 0x8050 },
{ 0x0bda, 0x8152 },
{ 0x0bda, 0x8153 },
/* Samsung */
{ 0x04e8, 0xa101 },
/* Lenovo */
{ 0x17ef, 0x304f },
{ 0x17ef, 0x3052 },
{ 0x17ef, 0x3054 },
{ 0x17ef, 0x3057 },
{ 0x17ef, 0x7205 },
{ 0x17ef, 0x720a },
{ 0x17ef, 0x720b },
{ 0x17ef, 0x720c },
/* TP-LINK */
{ 0x2357, 0x0601 },
{ 0x2357, 0x0602 },
/* Nvidia */
{ 0x0955, 0x09ff },
};
#endif
struct r8152_version {
unsigned short tcr;
unsigned short version;
@ -1479,243 +1442,6 @@ static int r8152_send_common(struct ueth_data *ueth, void *packet, int length)
return err;
}
#ifndef CONFIG_DM_ETH
static int r8152_init(struct eth_device *eth, struct bd_info *bd)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct r8152 *tp = (struct r8152 *)dev->dev_priv;
return r8152_init_common(tp);
}
static int r8152_send(struct eth_device *eth, void *packet, int length)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return r8152_send_common(dev, packet, length);
}
static int r8152_recv(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
ALLOC_CACHE_ALIGN_BUFFER(uint8_t, recv_buf, RTL8152_AGG_BUF_SZ);
unsigned char *pkt_ptr;
int err;
int actual_len;
u16 packet_len;
u32 bytes_process = 0;
struct rx_desc *rx_desc;
debug("** %s()\n", __func__);
err = usb_bulk_msg(dev->pusb_dev,
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
(void *)recv_buf,
RTL8152_AGG_BUF_SZ,
&actual_len,
USB_BULK_RECV_TIMEOUT);
debug("Rx: len = %u, actual = %u, err = %d\n", RTL8152_AGG_BUF_SZ,
actual_len, err);
if (err != 0) {
debug("Rx: failed to receive\n");
return -1;
}
if (actual_len > RTL8152_AGG_BUF_SZ) {
debug("Rx: received too many bytes %d\n", actual_len);
return -1;
}
while (bytes_process < actual_len) {
rx_desc = (struct rx_desc *)(recv_buf + bytes_process);
pkt_ptr = recv_buf + sizeof(struct rx_desc) + bytes_process;
packet_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
packet_len -= CRC_SIZE;
net_process_received_packet(pkt_ptr, packet_len);
bytes_process +=
(packet_len + sizeof(struct rx_desc) + CRC_SIZE);
if (bytes_process % 8)
bytes_process = bytes_process + 8 - (bytes_process % 8);
}
return 0;
}
static void r8152_halt(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct r8152 *tp = (struct r8152 *)dev->dev_priv;
debug("** %s()\n", __func__);
tp->rtl_ops.disable(tp);
}
static int r8152_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct r8152 *tp = (struct r8152 *)dev->dev_priv;
unsigned char enetaddr[8] = {0};
memcpy(enetaddr, eth->enetaddr, ETH_ALEN);
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr);
ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
debug("MAC %pM\n", eth->enetaddr);
return 0;
}
void r8152_eth_before_probe(void)
{
curr_eth_dev = 0;
}
/* Probe to see if a new device is actually an realtek device */
int r8152_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss)
{
struct usb_interface *iface;
struct usb_interface_descriptor *iface_desc;
int ep_in_found = 0, ep_out_found = 0;
struct r8152 *tp;
int i;
/* let's examine the device now */
iface = &dev->config.if_desc[ifnum];
iface_desc = &dev->config.if_desc[ifnum].desc;
for (i = 0; i < ARRAY_SIZE(r8152_dongles); i++) {
if (dev->descriptor.idVendor == r8152_dongles[i].vendor &&
dev->descriptor.idProduct == r8152_dongles[i].product)
/* Found a supported dongle */
break;
}
if (i == ARRAY_SIZE(r8152_dongles))
return 0;
memset(ss, 0, sizeof(struct ueth_data));
/* At this point, we know we've got a live one */
debug("\n\nUSB Ethernet device detected: %#04x:%#04x\n",
dev->descriptor.idVendor, dev->descriptor.idProduct);
/* Initialize the ueth_data structure with some useful info */
ss->ifnum = ifnum;
ss->pusb_dev = dev;
ss->subclass = iface_desc->bInterfaceSubClass;
ss->protocol = iface_desc->bInterfaceProtocol;
/* alloc driver private */
ss->dev_priv = calloc(1, sizeof(struct r8152));
if (!ss->dev_priv)
return 0;
/*
* We are expecting a minimum of 3 endpoints - in, out (bulk), and
* int. We will ignore any others.
*/
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
/* is it an BULK endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
u8 ep_addr = iface->ep_desc[i].bEndpointAddress;
if (ep_addr & USB_DIR_IN) {
if (!ep_in_found) {
ss->ep_in = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
ep_in_found = 1;
}
} else {
if (!ep_out_found) {
ss->ep_out = ep_addr &
USB_ENDPOINT_NUMBER_MASK;
ep_out_found = 1;
}
}
}
/* is it an interrupt endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
ss->irqinterval = iface->ep_desc[i].bInterval;
}
}
debug("Endpoints In %d Out %d Int %d\n",
ss->ep_in, ss->ep_out, ss->ep_int);
/* Do some basic sanity checks, and bail if we find a problem */
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
debug("Problems with device\n");
goto error;
}
dev->privptr = (void *)ss;
tp = ss->dev_priv;
tp->udev = dev;
tp->intf = iface;
r8152b_get_version(tp);
if (rtl_ops_init(tp))
goto error;
tp->rtl_ops.init(tp);
tp->rtl_ops.up(tp);
rtl8152_set_speed(tp, AUTONEG_ENABLE,
tp->supports_gmii ? SPEED_1000 : SPEED_100,
DUPLEX_FULL);
return 1;
error:
cfree(ss->dev_priv);
ss->dev_priv = 0;
return 0;
}
int r8152_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth)
{
if (!eth) {
debug("%s: missing parameter.\n", __func__);
return 0;
}
sprintf(eth->name, "%s#%d", R8152_BASE_NAME, curr_eth_dev++);
eth->init = r8152_init;
eth->send = r8152_send;
eth->recv = r8152_recv;
eth->halt = r8152_halt;
eth->write_hwaddr = r8152_write_hwaddr;
eth->priv = ss;
/* Get the MAC address */
if (r8152_read_mac(ss->dev_priv, eth->enetaddr) < 0)
return 0;
debug("MAC %pM\n", eth->enetaddr);
return 1;
}
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_DM_ETH
static int r8152_eth_start(struct udevice *dev)
{
struct r8152 *tp = dev_get_priv(dev);
@ -1895,4 +1621,3 @@ static const struct usb_device_id r8152_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(r8152_eth, r8152_eth_id_table);
#endif /* CONFIG_DM_ETH */

2
drivers/usb/eth/r8152.h
View File

@ -642,9 +642,7 @@ struct r8152 {
u8 version;
#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
#endif
};
int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,

234
drivers/usb/eth/smsc95xx.c
View File

@ -143,16 +143,9 @@
#define TURBO_MODE
#ifndef CONFIG_DM_ETH
/* local vars */
static int curr_eth_dev; /* index for name of next device detected */
#endif
/* driver private */
struct smsc95xx_private {
#ifdef CONFIG_DM_ETH
struct ueth_data ueth;
#endif
size_t rx_urb_size; /* maximum USB URB size */
u32 mac_cr; /* MAC control register value */
int have_hwaddr; /* 1 if we have a hardware MAC address */
@ -521,11 +514,6 @@ static int smsc95xx_init_common(struct usb_device *udev, struct ueth_data *dev,
debug("timeout waiting for PHY Reset\n");
return -ETIMEDOUT;
}
#ifndef CONFIG_DM_ETH
if (!priv->have_hwaddr && smsc95xx_init_mac_address(enetaddr, udev) ==
0)
priv->have_hwaddr = 1;
#endif
if (!priv->have_hwaddr) {
puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
return -EADDRNOTAVAIL;
@ -712,227 +700,6 @@ static int smsc95xx_send_common(struct ueth_data *dev, void *packet, int length)
return err;
}
#ifndef CONFIG_DM_ETH
/*
* Smsc95xx callbacks
*/
static int smsc95xx_init(struct eth_device *eth, struct bd_info *bd)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
struct usb_device *udev = dev->pusb_dev;
struct smsc95xx_private *priv =
(struct smsc95xx_private *)dev->dev_priv;
return smsc95xx_init_common(udev, dev, priv, eth->enetaddr);
}
static int smsc95xx_send(struct eth_device *eth, void *packet, int length)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
return smsc95xx_send_common(dev, packet, length);
}
static int smsc95xx_recv(struct eth_device *eth)
{
struct ueth_data *dev = (struct ueth_data *)eth->priv;
DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, RX_URB_SIZE);
unsigned char *buf_ptr;
int err;
int actual_len;
u32 packet_len;
int cur_buf_align;
debug("** %s()\n", __func__);
err = usb_bulk_msg(dev->pusb_dev,
usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
(void *)recv_buf, RX_URB_SIZE, &actual_len,
USB_BULK_RECV_TIMEOUT);
debug("Rx: len = %u, actual = %u, err = %d\n", RX_URB_SIZE,
actual_len, err);
if (err != 0) {
debug("Rx: failed to receive\n");
return -err;
}
if (actual_len > RX_URB_SIZE) {
debug("Rx: received too many bytes %d\n", actual_len);
return -ENOSPC;
}
buf_ptr = recv_buf;
while (actual_len > 0) {
/*
* 1st 4 bytes contain the length of the actual data plus error
* info. Extract data length.
*/
if (actual_len < sizeof(packet_len)) {
debug("Rx: incomplete packet length\n");
return -EIO;
}
memcpy(&packet_len, buf_ptr, sizeof(packet_len));
le32_to_cpus(&packet_len);
if (packet_len & RX_STS_ES_) {
debug("Rx: Error header=%#x", packet_len);
return -EIO;
}
packet_len = ((packet_len & RX_STS_FL_) >> 16);
if (packet_len > actual_len - sizeof(packet_len)) {
debug("Rx: too large packet: %d\n", packet_len);
return -EIO;
}
/* Notify net stack */
net_process_received_packet(buf_ptr + sizeof(packet_len),
packet_len - 4);
/* Adjust for next iteration */
actual_len -= sizeof(packet_len) + packet_len;
buf_ptr += sizeof(packet_len) + packet_len;
cur_buf_align = (ulong)buf_ptr - (ulong)recv_buf;
if (cur_buf_align & 0x03) {
int align = 4 - (cur_buf_align & 0x03);
actual_len -= align;
buf_ptr += align;
}
}
return err;
}
static void smsc95xx_halt(struct eth_device *eth)
{
debug("** %s()\n", __func__);
}
static int smsc95xx_write_hwaddr(struct eth_device *eth)
{
struct ueth_data *dev = eth->priv;
struct usb_device *udev = dev->pusb_dev;
struct smsc95xx_private *priv = dev->dev_priv;
return smsc95xx_write_hwaddr_common(udev, priv, eth->enetaddr);
}
/*
* SMSC probing functions
*/
void smsc95xx_eth_before_probe(void)
{
curr_eth_dev = 0;
}
struct smsc95xx_dongle {
unsigned short vendor;
unsigned short product;
};
static const struct smsc95xx_dongle smsc95xx_dongles[] = {
{ 0x0424, 0xec00 }, /* LAN9512/LAN9514 Ethernet */
{ 0x0424, 0x9500 }, /* LAN9500 Ethernet */
{ 0x0424, 0x9730 }, /* LAN9730 Ethernet (HSIC) */
{ 0x0424, 0x9900 }, /* SMSC9500 USB Ethernet Device (SAL10) */
{ 0x0424, 0x9e00 }, /* LAN9500A Ethernet */
{ 0x0000, 0x0000 } /* END - Do not remove */
};
/* Probe to see if a new device is actually an SMSC device */
int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss)
{
struct usb_interface *iface;
struct usb_interface_descriptor *iface_desc;
int i;
/* let's examine the device now */
iface = &dev->config.if_desc[ifnum];
iface_desc = &dev->config.if_desc[ifnum].desc;
for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
dev->descriptor.idProduct == smsc95xx_dongles[i].product)
/* Found a supported dongle */
break;
}
if (smsc95xx_dongles[i].vendor == 0)
return 0;
/* At this point, we know we've got a live one */
debug("\n\nUSB Ethernet device detected\n");
memset(ss, '\0', sizeof(struct ueth_data));
/* Initialize the ueth_data structure with some useful info */
ss->ifnum = ifnum;
ss->pusb_dev = dev;
ss->subclass = iface_desc->bInterfaceSubClass;
ss->protocol = iface_desc->bInterfaceProtocol;
/*
* We are expecting a minimum of 3 endpoints - in, out (bulk), and int.
* We will ignore any others.
*/
for (i = 0; i < iface_desc->bNumEndpoints; i++) {
/* is it an BULK endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
ss->ep_in =
iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
else
ss->ep_out =
iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
}
/* is it an interrupt endpoint? */
if ((iface->ep_desc[i].bmAttributes &
USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
ss->ep_int = iface->ep_desc[i].bEndpointAddress &
USB_ENDPOINT_NUMBER_MASK;
ss->irqinterval = iface->ep_desc[i].bInterval;
}
}
debug("Endpoints In %d Out %d Int %d\n",
ss->ep_in, ss->ep_out, ss->ep_int);
/* Do some basic sanity checks, and bail if we find a problem */
if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
!ss->ep_in || !ss->ep_out || !ss->ep_int) {
debug("Problems with device\n");
return 0;
}
dev->privptr = (void *)ss;
/* alloc driver private */
ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
if (!ss->dev_priv)
return 0;
return 1;
}
int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *eth)
{
debug("** %s()\n", __func__);
if (!eth) {
debug("%s: missing parameter.\n", __func__);
return 0;
}
sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
eth->init = smsc95xx_init;
eth->send = smsc95xx_send;
eth->recv = smsc95xx_recv;
eth->halt = smsc95xx_halt;
eth->write_hwaddr = smsc95xx_write_hwaddr;
eth->priv = ss;
return 1;
}
#endif /* !CONFIG_DM_ETH */
#ifdef CONFIG_DM_ETH
static int smsc95xx_eth_start(struct udevice *dev)
{
struct usb_device *udev = dev_get_parent_priv(dev);
@ -1077,4 +844,3 @@ static const struct usb_device_id smsc95xx_eth_id_table[] = {
};
U_BOOT_USB_DEVICE(smsc95xx_eth, smsc95xx_eth_id_table);
#endif

199
drivers/usb/eth/usb_ether.c
View File

@ -15,8 +15,6 @@
#include "usb_ether.h"
#ifdef CONFIG_DM_ETH
#define USB_BULK_RECV_TIMEOUT 500
int usb_ether_register(struct udevice *dev, struct ueth_data *ueth, int rxsize)
@ -137,200 +135,3 @@ int usb_ether_get_rx_bytes(struct ueth_data *ueth, uint8_t **ptrp)
return ueth->rxlen - ueth->rxptr;
}
#else
typedef void (*usb_eth_before_probe)(void);
typedef int (*usb_eth_probe)(struct usb_device *dev, unsigned int ifnum,
struct ueth_data *ss);
typedef int (*usb_eth_get_info)(struct usb_device *dev, struct ueth_data *ss,
struct eth_device *dev_desc);
struct usb_eth_prob_dev {
usb_eth_before_probe before_probe; /* optional */
usb_eth_probe probe;
usb_eth_get_info get_info;
};
/* driver functions go here, each bracketed by #ifdef CONFIG_USB_ETHER_xxx */
static const struct usb_eth_prob_dev prob_dev[] = {
#ifdef CONFIG_USB_ETHER_ASIX
{
.before_probe = asix_eth_before_probe,
.probe = asix_eth_probe,
.get_info = asix_eth_get_info,
},
#endif
#ifdef CONFIG_USB_ETHER_ASIX88179
{
.before_probe = ax88179_eth_before_probe,
.probe = ax88179_eth_probe,
.get_info = ax88179_eth_get_info,
},
#endif
#ifdef CONFIG_USB_ETHER_MCS7830
{
.before_probe = mcs7830_eth_before_probe,
.probe = mcs7830_eth_probe,
.get_info = mcs7830_eth_get_info,
},
#endif
#ifdef CONFIG_USB_ETHER_SMSC95XX
{
.before_probe = smsc95xx_eth_before_probe,
.probe = smsc95xx_eth_probe,
.get_info = smsc95xx_eth_get_info,
},
#endif
#ifdef CONFIG_USB_ETHER_RTL8152
{
.before_probe = r8152_eth_before_probe,
.probe = r8152_eth_probe,
.get_info = r8152_eth_get_info,
},
#endif
{ }, /* END */
};
static int usb_max_eth_dev; /* number of highest available usb eth device */
static struct ueth_data usb_eth[USB_MAX_ETH_DEV];
/*******************************************************************************
* tell if current ethernet device is a usb dongle
*/
int is_eth_dev_on_usb_host(void)
{
int i;
struct eth_device *dev = eth_get_dev();
if (dev) {
for (i = 0; i < usb_max_eth_dev; i++)
if (&usb_eth[i].eth_dev == dev)
return 1;
}
return 0;
}
/*
* Given a USB device, ask each driver if it can support it, and attach it
* to the first driver that says 'yes'
*/
static void probe_valid_drivers(struct usb_device *dev)
{
struct eth_device *eth;
int j;
for (j = 0; prob_dev[j].probe && prob_dev[j].get_info; j++) {
if (!prob_dev[j].probe(dev, 0, &usb_eth[usb_max_eth_dev]))
continue;
/*
* ok, it is a supported eth device. Get info and fill it in
*/
eth = &usb_eth[usb_max_eth_dev].eth_dev;
if (prob_dev[j].get_info(dev,
&usb_eth[usb_max_eth_dev],
eth)) {
/* found proper driver */
/* register with networking stack */
usb_max_eth_dev++;
/*
* usb_max_eth_dev must be incremented prior to this
* call since eth_current_changed (internally called)
* relies on it
*/
eth_register(eth);
if (eth_write_hwaddr(eth, "usbeth",
usb_max_eth_dev - 1))
puts("Warning: failed to set MAC address\n");
break;
}
}
}
/*******************************************************************************
* scan the usb and reports device info
* to the user if mode = 1
* returns current device or -1 if no
*/
int usb_host_eth_scan(int mode)
{
int i, old_async;
if (mode == 1)
printf(" scanning usb for ethernet devices... ");
old_async = usb_disable_asynch(1); /* asynch transfer not allowed */
/* unregister a previously detected device */
for (i = 0; i < usb_max_eth_dev; i++)
eth_unregister(&usb_eth[i].eth_dev);
memset(usb_eth, 0, sizeof(usb_eth));
for (i = 0; prob_dev[i].probe; i++) {
if (prob_dev[i].before_probe)
prob_dev[i].before_probe();
}
usb_max_eth_dev = 0;
#if CONFIG_IS_ENABLED(DM_USB)
/*
* TODO: We should add U_BOOT_USB_DEVICE() declarations to each USB
* Ethernet driver and then most of this file can be removed.
*/
struct udevice *bus;
struct uclass *uc;
int ret;
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
return ret;
uclass_foreach_dev(bus, uc) {
for (i = 0; i < USB_MAX_DEVICE; i++) {
struct usb_device *dev;
dev = usb_get_dev_index(bus, i); /* get device */
debug("i=%d, %s\n", i, dev ? dev->dev->name : "(done)");
if (!dev)
break; /* no more devices available */
/*
* find valid usb_ether driver for this device,
* if any
*/
probe_valid_drivers(dev);
/* check limit */
if (usb_max_eth_dev == USB_MAX_ETH_DEV)
break;
} /* for */
}
#else
for (i = 0; i < USB_MAX_DEVICE; i++) {
struct usb_device *dev;
dev = usb_get_dev_index(i); /* get device */
debug("i=%d\n", i);
if (!dev)
break; /* no more devices available */
/* find valid usb_ether driver for this device, if any */
probe_valid_drivers(dev);
/* check limit */
if (usb_max_eth_dev == USB_MAX_ETH_DEV)
break;
} /* for */
#endif
if (usb_max_eth_dev == USB_MAX_ETH_DEV) {
printf("max USB Ethernet Device reached: %d stopping\n",
usb_max_eth_dev);
}
usb_disable_asynch(old_async); /* restore asynch value */
printf("%d Ethernet Device(s) found\n", usb_max_eth_dev);
if (usb_max_eth_dev > 0)
return 0;
return -1;
}
#endif

97
drivers/usb/gadget/ether.c
View File

@ -109,11 +109,7 @@ struct eth_dev {
struct usb_request *tx_req, *rx_req;
#ifndef CONFIG_DM_ETH
struct eth_device *net;
#else
struct udevice *net;
#endif
struct net_device_stats stats;
unsigned int tx_qlen;
@ -140,11 +136,7 @@ struct eth_dev {
/*-------------------------------------------------------------------------*/
struct ether_priv {
struct eth_dev ethdev;
#ifndef CONFIG_DM_ETH
struct eth_device netdev;
#else
struct udevice *netdev;
#endif
struct usb_gadget_driver eth_driver;
};
@ -1827,22 +1819,14 @@ static void rndis_control_ack_complete(struct usb_ep *ep,
static char rndis_resp_buf[8] __attribute__((aligned(sizeof(__le32))));
#ifndef CONFIG_DM_ETH
static int rndis_control_ack(struct eth_device *net)
#else
static int rndis_control_ack(struct udevice *net)
#endif
{
struct ether_priv *priv;
struct eth_dev *dev;
int length;
struct usb_request *resp;
#ifndef CONFIG_DM_ETH
priv = (struct ether_priv *)net->priv;
#else
priv = dev_get_priv(net);
#endif
dev = &priv->ethdev;
resp = dev->stat_req;
@ -1989,9 +1973,7 @@ static int eth_bind(struct usb_gadget *gadget)
int status = -ENOMEM;
int gcnum;
u8 tmp[7];
#ifdef CONFIG_DM_ETH
struct eth_pdata *pdata = dev_get_plat(l_priv->netdev);
#endif
/* these flags are only ever cleared; compiler take note */
#ifndef CONFIG_USB_ETH_CDC
@ -2168,11 +2150,7 @@ autoconf_fail:
/* network device setup */
#ifndef CONFIG_DM_ETH
dev->net = &l_priv->netdev;
#else
dev->net = l_priv->netdev;
#endif
dev->cdc = cdc;
dev->zlp = zlp;
@ -2189,13 +2167,8 @@ autoconf_fail:
* host side code for the SAFE thing cares -- its original BLAN
* thing didn't, Sharp never assigned those addresses on Zaurii.
*/
#ifndef CONFIG_DM_ETH
get_ether_addr(dev_addr, dev->net->enetaddr);
memcpy(tmp, dev->net->enetaddr, sizeof(dev->net->enetaddr));
#else
get_ether_addr(dev_addr, pdata->enetaddr);
memcpy(tmp, pdata->enetaddr, sizeof(pdata->enetaddr));
#endif
get_ether_addr(host_addr, dev->host_mac);
@ -2256,11 +2229,7 @@ autoconf_fail:
status_ep ? " STATUS " : "",
status_ep ? status_ep->name : ""
);
#ifndef CONFIG_DM_ETH
printf("MAC %pM\n", dev->net->enetaddr);
#else
printf("MAC %pM\n", pdata->enetaddr);
#endif
if (cdc || rndis)
printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
@ -2490,71 +2459,6 @@ static void _usb_eth_halt(struct ether_priv *priv)
usb_gadget_release(0);
}
#ifndef CONFIG_DM_ETH
static int usb_eth_init(struct eth_device *netdev, struct bd_info *bd)
{
struct ether_priv *priv = (struct ether_priv *)netdev->priv;
return _usb_eth_init(priv);
}
static int usb_eth_send(struct eth_device *netdev, void *packet, int length)
{
struct ether_priv *priv = (struct ether_priv *)netdev->priv;
return _usb_eth_send(priv, packet, length);
}
static int usb_eth_recv(struct eth_device *netdev)
{
struct ether_priv *priv = (struct ether_priv *)netdev->priv;
struct eth_dev *dev = &priv->ethdev;
int ret;
ret = _usb_eth_recv(priv);
if (ret) {
pr_err("error packet receive\n");
return ret;
}
if (!packet_received)
return 0;
if (dev->rx_req) {
net_process_received_packet(net_rx_packets[0],
dev->rx_req->length);
} else {
pr_err("dev->rx_req invalid");
}
packet_received = 0;
rx_submit(dev, dev->rx_req, 0);
return 0;
}
void usb_eth_halt(struct eth_device *netdev)
{
struct ether_priv *priv = (struct ether_priv *)netdev->priv;
_usb_eth_halt(priv);
}
int usb_eth_initialize(struct bd_info *bi)
{
struct eth_device *netdev = &l_priv->netdev;
strlcpy(netdev->name, USB_NET_NAME, sizeof(netdev->name));
netdev->init = usb_eth_init;
netdev->send = usb_eth_send;
netdev->recv = usb_eth_recv;
netdev->halt = usb_eth_halt;
netdev->priv = l_priv;
eth_register(netdev);
return 0;
}
#else
static int usb_eth_start(struct udevice *dev)
{
struct ether_priv *priv = dev_get_priv(dev);
@ -2663,4 +2567,3 @@ U_BOOT_DRIVER(eth_usb) = {
.plat_auto = sizeof(struct eth_pdata),
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
#endif /* CONFIG_DM_ETH */

9
drivers/usb/gadget/rndis.c
View File

@ -1115,11 +1115,7 @@ int rndis_msg_parser(u8 configNr, u8 *buf)
return -ENOTSUPP;
}
#ifndef CONFIG_DM_ETH
int rndis_register(int (*rndis_control_ack)(struct eth_device *))
#else
int rndis_register(int (*rndis_control_ack)(struct udevice *))
#endif
{
u8 i;
@ -1147,13 +1143,8 @@ void rndis_deregister(int configNr)
return;
}
#ifndef CONFIG_DM_ETH
int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter)
#else
int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter)
#endif
{
debug("%s: configNr = %d\n", __func__, configNr);
if (!dev || !stats)

11
drivers/usb/gadget/rndis.h
View File

@ -226,13 +226,8 @@ typedef struct rndis_params {
u32 vendorID;
const char *vendorDescr;
#ifndef CONFIG_DM_ETH
struct eth_device *dev;
int (*ack)(struct eth_device *);
#else
struct udevice *dev;
int (*ack)(struct udevice *);
#endif
struct list_head resp_queue;
} rndis_params;
@ -240,15 +235,9 @@ typedef struct rndis_params {
int rndis_msg_parser(u8 configNr, u8 *buf);
enum rndis_state rndis_get_state(int configNr);
void rndis_deregister(int configNr);
#ifndef CONFIG_DM_ETH
int rndis_register(int (*rndis_control_ack)(struct eth_device *));
int rndis_set_param_dev(u8 configNr, struct eth_device *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter);
#else
int rndis_register(int (*rndis_control_ack)(struct udevice *));
int rndis_set_param_dev(u8 configNr, struct udevice *dev, int mtu,
struct net_device_stats *stats, u16 *cdc_filter);
#endif
int rndis_set_param_vendor(u8 configNr, u32 vendorID,
const char *vendorDescr);
int rndis_set_param_medium(u8 configNr, u32 medium, u32 speed);

43
drivers/usb/host/usb-uclass.c
View File

@ -346,49 +346,6 @@ int usb_init(void)
return usb_started ? 0 : -1;
}
/*
* TODO(sjg@chromium.org): Remove this legacy function. At present it is needed
* to support boards which use driver model for USB but not Ethernet, and want
* to use USB Ethernet.
*
* The #if clause is here to ensure that remains the only case.
*/
#if !defined(CONFIG_DM_ETH) && defined(CONFIG_USB_HOST_ETHER)
static struct usb_device *find_child_devnum(struct udevice *parent, int devnum)
{
struct usb_device *udev;
struct udevice *dev;
if (!device_active(parent))
return NULL;
udev = dev_get_parent_priv(parent);
if (udev->devnum == devnum)
return udev;
for (device_find_first_child(parent, &dev);
dev;
device_find_next_child(&dev)) {
udev = find_child_devnum(dev, devnum);
if (udev)
return udev;
}
return NULL;
}
struct usb_device *usb_get_dev_index(struct udevice *bus, int index)
{
struct udevice *dev;
int devnum = index + 1; /* Addresses are allocated from 1 on USB */
device_find_first_child(bus, &dev);
if (!dev)
return NULL;
return find_child_devnum(dev, devnum);
}
#endif
int usb_setup_ehci_gadget(struct ehci_ctrl **ctlrp)
{
struct usb_plat *plat;

27
include/configs/MPC837XERDB.h
View File

@ -41,8 +41,6 @@
#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE 0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE 8192
@ -178,31 +176,6 @@
#define CFG_SYS_PCIE2_MEM_PHYS 0xC8000000
#define CFG_SYS_PCIE2_IO_PHYS 0xD8000000
/*
* TSEC
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_GMII /* MII PHY management */
#define CONFIG_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_SYS_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_TSEC2
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC2_PHY_ADDR 0x1c
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_PHYIDX 0
#endif
#endif
#ifdef CONFIG_MMC
#define CONFIG_FSL_ESDHC_PIN_MUX
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR

27
include/configs/MPC8548CDS.h
View File

@ -283,33 +283,6 @@
#endif
#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#define CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC3_PHY_ADDR 2
#define TSEC4_PHY_ADDR 3
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC4_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC2_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#endif /* CONFIG_TSEC_ENET */
/*
* Miscellaneous configurable options
*/

31
include/configs/P1010RDB.h
View File

@ -349,37 +349,6 @@ extern unsigned long get_sdram_size(void);
/* eSPI - Enhanced SPI */
#endif
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 1
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 2
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
/* TBI PHY configuration for SGMII mode */
#define CONFIG_TSEC_TBICR_SETTINGS ( \
TBICR_PHY_RESET \
| TBICR_ANEG_ENABLE \
| TBICR_FULL_DUPLEX \
| TBICR_SPEED1_SET \
)
#endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC
#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR
#endif

21
include/configs/ls1021aiot.h
View File

@ -66,27 +66,6 @@
/* SPI */
/*
* eTSEC
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC 1
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define TSEC1_PHY_ADDR 1
#define TSEC2_PHY_ADDR 3
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#endif
#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
#define CONFIG_PEN_ADDR_BIG_ENDIAN

26
include/configs/ls1021aqds.h
View File

@ -247,32 +247,6 @@
* MMC
*/
/*
* eTSEC
*/
#ifdef CONFIG_TSEC_ENET
#define CONFIG_MII_DEFAULT_TSEC 3
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 1
#define TSEC2_PHY_ADDR 2
#define TSEC3_PHY_ADDR 3
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#endif
#define CONFIG_PEN_ADDR_BIG_ENDIAN
#define CONFIG_SMP_PEN_ADDR 0x01ee0200

21
include/configs/p1_p2_rdb_pc.h
View File

@ -366,27 +366,6 @@
#endif
#endif /* CONFIG_PCI */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3
#define CONFIG_TSEC3_NAME "eTSEC3"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC1_PHYIDX 0
#define TSEC2_PHYIDX 0
#define TSEC3_PHYIDX 0
#endif /* CONFIG_TSEC_ENET */
/*
* Environment
*/

16
include/configs/socrates.h
View File

@ -111,22 +111,6 @@
#define CFG_SYS_PCI1_MEM_PHYS 0x80000000
#define CFG_SYS_PCI1_IO_PHYS 0xE2000000
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC3_PHY_ADDR 1
#define TSEC1_PHYIDX 0
#define TSEC3_PHYIDX 0
#define TSEC1_FLAGS TSEC_GIGABIT
#define TSEC3_FLAGS TSEC_GIGABIT
/* Options are: TSEC[0,1] */
/*
* Miscellaneous configurable options
*/

4
include/dm/platform_data/net_ethoc.h
View File

@ -8,13 +8,9 @@
#include <net.h>
#ifdef CONFIG_DM_ETH
struct ethoc_eth_pdata {
struct eth_pdata eth_pdata;
phys_addr_t packet_base;
};
#endif
#endif /* _ETHOC_H */

Some files were not shown because too many files have changed in this diff Show More