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board: gdsys: a38x: Enable PCIe link 2 in spl_board_init()

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A385 controlcenterdc board does not use PCI DM properly and touches some
PCIe devices directly in its board code.

This controlcenterdc spl_board_init() function expects that PCIe link is
already initialized. Link itself is initialized in a38x serdes code but
this will change in future and link initialization will be postponed from
U-Boot SPL to proper U-Boot.

So explicitly enable PCIe link 2 in spl_board_init() function via
SoC Control Register 1 to not break this code by future changes. This board
has PCIe link 2 just x1, so no additional initialization (except enabling
PCIe port) is needed.

Signed-off-by: Pali Rohár <pali@kernel.org>
This commit is contained in:
Pali Rohár 2021-12-21 12:20:12 +01:00 committed by Stefan Roese
parent 8f9e0f4d20
commit 2ac06f3e66
1 changed files with 4 additions and 0 deletions
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4
board/gdsys/a38x/controlcenterdc.c
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@ -100,6 +100,10 @@ void spl_board_init(void)
uint k; uint k;
struct gpio_desc gpio = {}; struct gpio_desc gpio = {};
/* Enable PCIe link 2 */
setbits_32(MVEBU_REGISTER(0x18204), BIT(2));
mdelay(10);
if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) { if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
/* prepare FPGA reconfiguration */ /* prepare FPGA reconfiguration */
dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT); dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);