drivers/net/phy: Add CORTINA_NO_FW_UPLOAD to Kconfig
Move CORTINA_NO_FW_UPLOAD to Kconfig file so that it can be controlled via defconfig files. Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -56,6 +56,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_DM_ETH=y
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@ -63,6 +63,7 @@ CONFIG_SPI_FLASH_SST=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_VITESSE=y
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CONFIG_DM_ETH=y
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@ -52,6 +52,7 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -61,6 +61,7 @@ CONFIG_PHYLIB=y
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CONFIG_PHY_AQUANTIA=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_CORTINA=y
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CONFIG_SYS_CORTINA_NO_FW_UPLOAD=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_E1000=y
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@ -100,6 +100,15 @@ config PHY_BROADCOM
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config PHY_CORTINA
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bool "Cortina Ethernet PHYs support"
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config SYS_CORTINA_NO_FW_UPLOAD
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bool "Cortina firmware loading support"
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default n
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depends on PHY_CORTINA
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help
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Cortina phy has provision to store phy firmware in attached dedicated
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EEPROM. And boards designed with such EEPROM does not require firmware
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upload.
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choice
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prompt "Location of the Cortina firmware"
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default SYS_CORTINA_FW_IN_NOR
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@ -3,7 +3,7 @@
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* Cortina CS4315/CS4340 10G PHY drivers
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*
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* Copyright 2014 Freescale Semiconductor, Inc.
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* Copyright 2018 NXP
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* Copyright 2018, 2020 NXP
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*
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*/
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@ -29,7 +29,7 @@
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#error The Cortina PHY needs 10G support
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#endif
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#ifndef CORTINA_NO_FW_UPLOAD
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#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
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struct cortina_reg_config cortina_reg_cfg[] = {
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/* CS4315_enable_sr_mode */
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{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
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@ -227,7 +227,7 @@ void cs4340_upload_firmware(struct phy_device *phydev)
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int cs4340_phy_init(struct phy_device *phydev)
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{
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#ifndef CORTINA_NO_FW_UPLOAD
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#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
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int timeout = 100; /* 100ms */
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#endif
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int reg_value;
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@ -238,7 +238,7 @@ int cs4340_phy_init(struct phy_device *phydev)
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* Boards designed with EEPROM attached to Cortina
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* does not require FW upload.
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*/
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#ifndef CORTINA_NO_FW_UPLOAD
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#ifndef CONFIG_SYS_CORTINA_NO_FW_UPLOAD
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/* step1: BIST test */
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phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
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phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
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@ -93,7 +93,6 @@ u8 qixis_esdhc_detect_quirk(void);
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#define AQ_PHY_ADDR3 0x02
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#define AQ_PHY_ADDR4 0x03
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#define CORTINA_NO_FW_UPLOAD
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#define CORTINA_PHY_ADDR1 0x0
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#define INPHI_PHY_ADDR1 0x0
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@ -64,7 +64,6 @@
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#define AQR107_PHY_ADDR2 0x05
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#define AQR107_IRQ_MASK 0x0C
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#define CORTINA_NO_FW_UPLOAD
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#define CORTINA_PHY_ADDR1 0x0
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#define INPHI_PHY_ADDR1 0x0
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