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cyclic: Use schedule() instead of WATCHDOG_RESET()

Browse Source 
Globally replace all occurances of WATCHDOG_RESET() with schedule(),
which handles the HW_WATCHDOG functionality and the cyclic
infrastructure.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm, mx6cuboxi, rpi_3,dra7xx_evm, pine64_plus, am65x_evm, j721e_evm]
This commit is contained in:
Stefan Roese 2022-09-02 14:10:46 +02:00
parent 881d410825
commit 29caf9305b
103 changed files with 235 additions and 241 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/mach-at91/phy.c
View File

@ -42,7 +42,7 @@ void at91_phy_reset(void)
/* Wait for end of hardware reset */
while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL)) {
/* avoid shutdown by watchdog */
WATCHDOG_RESET();
schedule();
mdelay(10);
/* timeout for not getting stuck in an endless loop */

2
arch/arm/mach-imx/i2c-mxv7.c
View File

@ -46,7 +46,7 @@ int force_idle_bus(void *priv)
scl = gpio_get_value(p->scl.gp);
if ((sda & scl) == 1)
break;
WATCHDOG_RESET();
schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;

8
arch/arm/mach-socfpga/spl_a10.c
View File

@ -117,7 +117,7 @@ void spl_board_init(void)
/* enable console uart printing */
preloader_console_init();
WATCHDOG_RESET();
schedule();
arch_early_init_r();
@ -203,7 +203,7 @@ void spl_board_init(void)
*/
set_regular_boot(true);
WATCHDOG_RESET();
schedule();
reset_cpu();
}
@ -268,11 +268,11 @@ void board_init_f(ulong dummy)
/* reconfigure and enable the watchdog */
hw_watchdog_init();
WATCHDOG_RESET();
schedule();
#endif /* CONFIG_HW_WATCHDOG */
config_dedicated_pins(gd->fdt_blob);
WATCHDOG_RESET();
schedule();
}
/* board specific function prior loading SSBL / U-Boot proper */

6
arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog_serial.c
View File

@ -247,7 +247,7 @@ static int stm32prog_serial_getc_err(void)
err = ops->getc(down_serial_dev);
if (err == -EAGAIN) {
ctrlc();
WATCHDOG_RESET();
schedule();
}
} while ((err == -EAGAIN) && (!had_ctrlc()));
@ -276,7 +276,7 @@ static bool stm32prog_serial_get_buffer(u8 *buffer, u32 *count)
*count -= 1;
} else if (err == -EAGAIN) {
ctrlc();
WATCHDOG_RESET();
schedule();
if (get_timer(start) > TIMEOUT_SERIAL_BUFFER) {
err = -ETIMEDOUT;
break;
@ -852,7 +852,7 @@ bool stm32prog_serial_loop(struct stm32prog_data *data)
stm32prog_serial_result(ACK_BYTE);
cmd_func[counter](data);
}
WATCHDOG_RESET();
schedule();
}
/* clean device */

2
arch/m68k/lib/time.c
View File

@ -72,7 +72,7 @@ void dtimer_interrupt(void *not_used)
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0) {
WATCHDOG_RESET ();
schedule();
}
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
return;

2
arch/powerpc/cpu/mpc8xx/cpu_init.c
View File

@ -31,7 +31,7 @@ void cpu_init_f(immap_t __iomem *immr)
out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
#endif
WATCHDOG_RESET();
schedule();
/* SIUMCR - contains debug pin configuration (11-6) */
setbits_be32(&immr->im_siu_conf.sc_siumcr, CONFIG_SYS_SIUMCR);

6
arch/powerpc/lib/bootm.c
View File

@ -84,7 +84,7 @@ static void boot_jump_linux(bootm_headers_t *images)
* r9: 0
*/
debug(" Booting using OF flat tree...\n");
WATCHDOG_RESET ();
schedule();
(*kernel) ((struct bd_info *)of_flat_tree, 0, 0, EPAPR_MAGIC,
env_get_bootm_mapsize(), 0, 0);
/* does not return */
@ -108,7 +108,7 @@ static void boot_jump_linux(bootm_headers_t *images)
struct bd_info *kbd = images->kbd;
debug(" Booting using board info...\n");
WATCHDOG_RESET ();
schedule();
(*kernel) (kbd, initrd_start, initrd_end,
cmd_start, cmd_end, 0, 0);
/* does not return */
@ -319,7 +319,7 @@ void boot_jump_vxworks(bootm_headers_t *images)
* r9: 0
* TCR: WRC = 0, no watchdog timer reset will occur
*/
WATCHDOG_RESET();
schedule();
((void (*)(void *, ulong, ulong, ulong,
ulong, ulong, ulong))images->ep)(images->ft_addr,

2
arch/powerpc/lib/cache.c
View File

@ -13,7 +13,7 @@ static ulong maybe_watchdog_reset(ulong flushed)
{
flushed += CONFIG_SYS_CACHELINE_SIZE;
if (flushed >= CONFIG_CACHE_FLUSH_WATCHDOG_THRESHOLD) {
WATCHDOG_RESET();
schedule();
flushed = 0;
}
return flushed;

2
arch/powerpc/lib/interrupts.c
View File

@ -81,7 +81,7 @@ void timer_interrupt(struct pt_regs *regs)
#if defined(CONFIG_WATCHDOG) || defined (CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
WATCHDOG_RESET ();
schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
#ifdef CONFIG_LED_STATUS

4
board/astro/mcf5373l/fpga.c
View File

@ -123,7 +123,7 @@ int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
if (bytecount % len_40 == 0) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */
@ -343,7 +343,7 @@ int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
}
if (bytecount % len_40 == 0) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
putc('.'); /* let them know we are alive */

2
board/dhelectronics/dh_stm32mp1/board.c
View File

@ -423,7 +423,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
for (i = 0; i < 2 * nb_blink; i++) {
led_set_state(led, LEDST_TOGGLE);
mdelay(125);
WATCHDOG_RESET();
schedule();
}
}
#endif

2
board/liebherr/display5/spl.c
View File

@ -329,7 +329,7 @@ void board_init_f(ulong dummy)
/* Initialize and reset WDT in SPL */
#ifdef CONFIG_SPL_WATCHDOG
hw_watchdog_init();
WATCHDOG_RESET();
schedule();
#endif
/* load/boot image from boot device */

2
board/nokia/rx51/rx51.c
View File

@ -722,7 +722,7 @@ static int rx51_kp_getc(struct udevice *dev)
{
keybuf_head %= KEYBUF_SIZE;
while (!rx51_kp_tstc(dev))
WATCHDOG_RESET();
schedule();
return keybuf[keybuf_head++];
}

2
board/st/stm32mp1/stm32mp1.c
View File

@ -289,7 +289,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
for (i = 0; i < 2 * nb_blink; i++) {
led_set_state(led, LEDST_TOGGLE);
mdelay(125);
WATCHDOG_RESET();
schedule();
}
led_set_state(led, LEDST_ON);
}

2
boot/bootretry.c
View File

@ -44,7 +44,7 @@ int bootretry_tstc_timeout(void)
while (!tstc()) { /* while no incoming data */
if (retry_time >= 0 && get_ticks() > endtime)
return -ETIMEDOUT;
WATCHDOG_RESET();
schedule();
}
return 0;

2
boot/image-board.c
View File

@ -181,7 +181,7 @@ void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
while (len > 0) {
size_t tail = (len > chunksz) ? chunksz : len;
WATCHDOG_RESET();
schedule();
if (to > from) {
to -= tail;
from -= tail;

2
cmd/fastboot.c
View File

@ -76,7 +76,7 @@ static int do_fastboot_usb(int argc, char *const argv[],
break;
if (ctrlc())
break;
WATCHDOG_RESET();
schedule();
usb_gadget_handle_interrupts(controller_index);
}

16
cmd/mem.c
View File

@ -300,7 +300,7 @@ static int do_mem_cmp(struct cmd_tbl *cmdtp, int flag, int argc,
/* reset watchdog from time to time */
if ((ngood % (64 << 10)) == 0)
WATCHDOG_RESET();
schedule();
}
unmap_sysmem(buf1);
unmap_sysmem(buf2);
@ -848,7 +848,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
}
}
addr[test_offset] = pattern;
WATCHDOG_RESET();
schedule();
/*
* Check for addr bits stuck low or shorted.
@ -890,7 +890,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
* Fill memory with a known pattern.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
WATCHDOG_RESET();
schedule();
addr[offset] = pattern;
}
@ -898,7 +898,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
* Check each location and invert it for the second pass.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
WATCHDOG_RESET();
schedule();
temp = addr[offset];
if (temp != pattern) {
printf("\nFAILURE (read/write) @ 0x%.8lx:"
@ -918,7 +918,7 @@ static ulong mem_test_alt(vu_long *buf, ulong start_addr, ulong end_addr,
* Check each location for the inverted pattern and zero it.
*/
for (pattern = 1, offset = 0; offset < num_words; pattern++, offset++) {
WATCHDOG_RESET();
schedule();
anti_pattern = ~pattern;
temp = addr[offset];
if (temp != anti_pattern) {
@ -972,7 +972,7 @@ static ulong test_bitflip_comparison(volatile unsigned long *bufa,
for (k = 0; k < max; k++) {
q = 0x00000001L << k;
for (j = 0; j < 8; j++) {
WATCHDOG_RESET();
schedule();
q = ~q;
p1 = (volatile unsigned long *)bufa;
p2 = (volatile unsigned long *)bufb;
@ -1033,7 +1033,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
pattern, "");
for (addr = buf, val = pattern; addr < end; addr++) {
WATCHDOG_RESET();
schedule();
*addr = val;
val += incr;
}
@ -1041,7 +1041,7 @@ static ulong mem_test_quick(vu_long *buf, ulong start_addr, ulong end_addr,
puts("Reading...");
for (addr = buf, val = pattern; addr < end; addr++) {
WATCHDOG_RESET();
schedule();
readback = *addr;
if (readback != val) {
ulong offset = addr - buf;

2
cmd/usb_mass_storage.c
View File

@ -231,7 +231,7 @@ static int do_usb_mass_storage(struct cmd_tbl *cmdtp, int flag,
goto cleanup_register;
}
WATCHDOG_RESET();
schedule();
}
cleanup_register:

2
cmd/ximg.c
View File

@ -200,7 +200,7 @@ do_imgextract(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
while (l > 0) {
tail = (l > CHUNKSZ) ? CHUNKSZ : l;
WATCHDOG_RESET();
schedule();
memmove(to, from, tail);
to += tail;
from += tail;

4
common/board_f.c
View File

@ -114,14 +114,14 @@ static int init_func_watchdog_init(void)
hw_watchdog_init();
puts(" Watchdog enabled\n");
# endif
WATCHDOG_RESET();
schedule();
return 0;
}
int init_func_watchdog_reset(void)
{
WATCHDOG_RESET();
schedule();
return 0;
}

2
common/board_r.c
View File

@ -341,7 +341,7 @@ static int initr_flash(void)
/*
* Compute and print flash CRC if flashchecksum is set to 'y'
*
* NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
* NOTE: Maybe we should add some schedule()? XXX
*/
if (env_get_yesno("flashchecksum") == 1) {
const uchar *flash_base = (const uchar *)CONFIG_SYS_FLASH_BASE;

4
common/cli_readline.c
View File

@ -274,7 +274,7 @@ static int cread_line(const char *const prompt, char *buf, unsigned int *len,
while (!tstc()) { /* while no incoming data */
if (get_ticks() >= etime)
return -2; /* timed out */
WATCHDOG_RESET();
schedule();
}
first = 0;
}
@ -595,7 +595,7 @@ int cli_readline_into_buffer(const char *const prompt, char *buffer,
for (;;) {
if (bootretry_tstc_timeout())
return -2; /* timed out */
WATCHDOG_RESET(); /* Trigger watchdog, if needed */
schedule(); /* Trigger watchdog, if needed */
c = getchar();

2
common/console.c
View File

@ -480,7 +480,7 @@ int fgetc(int file)
* Effectively poll for input wherever it may be available.
*/
for (;;) {
WATCHDOG_RESET();
schedule();
if (CONFIG_IS_ENABLED(CONSOLE_MUX)) {
/*
* Upper layer may have already called tstc() so

2
common/dfu.c
View File

@ -101,7 +101,7 @@ int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget)
if (dfu_reinit_needed)
goto exit;
WATCHDOG_RESET();
schedule();
usb_gadget_handle_interrupts(usbctrl_index);
}
exit:

10
common/lcd.c
View File

@ -294,9 +294,9 @@ void lcd_logo_plot(int x, int y)
BMP_LOGO_WIDTH, BMP_LOGO_HEIGHT, BMP_LOGO_COLORS);
if (bpix < 12) {
WATCHDOG_RESET();
schedule();
lcd_logo_set_cmap();
WATCHDOG_RESET();
schedule();
for (i = 0; i < BMP_LOGO_HEIGHT; ++i) {
memcpy(fb, bmap, BMP_LOGO_WIDTH);
@ -320,7 +320,7 @@ void lcd_logo_plot(int x, int y)
}
}
WATCHDOG_RESET();
schedule();
lcd_sync();
}
#else
@ -459,7 +459,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
byte_width = width * 2;
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
schedule();
for (j = 0; j < width; j++) {
if (bpix != 16) {
fb_put_byte(&fb, &bmap);
@ -488,7 +488,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y)
#if defined(CONFIG_BMP_16BPP)
case 16:
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
schedule();
for (j = 0; j < width; j++)
fb_put_word(&fb, &bmap);

6
common/menu.c
View File

@ -435,7 +435,7 @@ void bootmenu_autoboot_loop(struct bootmenu_data *menu,
printf("Hit any key to stop autoboot: %d ", menu->delay);
for (i = 0; i < 100; ++i) {
if (!tstc()) {
WATCHDOG_RESET();
schedule();
mdelay(10);
continue;
}
@ -483,7 +483,7 @@ void bootmenu_loop(struct bootmenu_data *menu,
if (tstc()) {
c = getchar();
} else {
WATCHDOG_RESET();
schedule();
mdelay(10);
if (tstc())
c = getchar();
@ -492,7 +492,7 @@ void bootmenu_loop(struct bootmenu_data *menu,
}
} else {
while (!tstc()) {
WATCHDOG_RESET();
schedule();
mdelay(10);
}
c = getchar();

2
common/usb_kbd.c
View File

@ -446,7 +446,7 @@ static int usb_kbd_getc(struct stdio_dev *sdev)
data = usb_kbd_dev->privptr;
while (data->usb_in_pointer == data->usb_out_pointer) {
WATCHDOG_RESET();
schedule();
usb_kbd_poll_for_event(usb_kbd_dev);
}

2
common/xyzModem.c
View File

@ -68,7 +68,7 @@ CYGACC_COMM_IF_GETC_TIMEOUT (char chan, char *c)
{
ulong now = get_timer(0);
WATCHDOG_RESET();
schedule();
while (!tstc ())
{
if (get_timer(now) > xyzModem_CHAR_TIMEOUT)

8
drivers/block/ide.c
View File

@ -62,7 +62,7 @@ static void ide_reset(void)
/* the reset signal shall be asserted for et least 25 us */
udelay(25);
WATCHDOG_RESET();
schedule();
/* de-assert RESET signal */
ide_set_reset(0);
@ -695,7 +695,7 @@ void ide_init(void)
unsigned char c;
int i, bus;
WATCHDOG_RESET();
schedule();
/* ATAPI Drives seems to need a proper IDE Reset */
ide_reset();
@ -745,7 +745,7 @@ void ide_init(void)
puts("OK ");
ide_bus_ok[bus] = 1;
}
WATCHDOG_RESET();
schedule();
}
putc('\n');
@ -775,7 +775,7 @@ void ide_init(void)
}
#endif
}
WATCHDOG_RESET();
schedule();
#ifdef CONFIG_BLK
struct udevice *dev;

2
drivers/crypto/aspeed/aspeed_hace.c
View File

@ -302,7 +302,7 @@ static int aspeed_hace_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
return rc;
cur += chunk;
WATCHDOG_RESET();
schedule();
}
} else {
rc = aspeed_hace_update(dev, ctx, ibuf, ilen);

2
drivers/crypto/hash/hash_sw.c
View File

@ -258,7 +258,7 @@ static int sw_hash_digest_wd(struct udevice *dev, enum HASH_ALGO algo,
return rc;
cur += chunk;
WATCHDOG_RESET();
schedule();
}
} else {
rc = sw_hash_update(dev, ctx, ibuf, ilen);

4
drivers/ddr/altera/sdram_arria10.c
View File

@ -671,7 +671,7 @@ static int of_sdram_firewall_setup(const void *blob)
int ddr_calibration_sequence(void)
{
WATCHDOG_RESET();
schedule();
/* Check to see if SDRAM cal was success */
if (sdram_startup()) {
@ -681,7 +681,7 @@ int ddr_calibration_sequence(void)
puts("DDRCAL: Success\n");
WATCHDOG_RESET();
schedule();
/* initialize the MMR register */
sdram_mmr_init();

4
drivers/ddr/altera/sdram_n5x.c
View File

@ -517,7 +517,7 @@ static int ensure_retry_procedure_complete(phys_addr_t umctl2_base)
DDR4_CRCPARSTAT_CMD_IN_ERR_WINDOW;
udelay(1);
WATCHDOG_RESET();
schedule();
}
return 0;
@ -1349,7 +1349,7 @@ static int ddr_post_handoff_config(phys_addr_t umctl2_base,
}
udelay(1);
WATCHDOG_RESET();
schedule();
/* Polling until SDRAM entered normal operating mode */
value = readl(umctl2_base + DDR4_STAT_OFFSET) &

2
drivers/ddr/altera/sdram_soc64.c
View File

@ -161,7 +161,7 @@ void sdram_init_ecc_bits(struct bd_info *bd)
sdram_clear_mem(start_addr, size_init);
size -= size_init;
start_addr += size_init;
WATCHDOG_RESET();
schedule();
}
bank++;

8
drivers/fpga/intel_sdm_mb.c
View File

@ -44,7 +44,7 @@ static int reconfig_status_polling_resp(void)
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
WATCHDOG_RESET();
schedule();
}
return -ETIMEDOUT;
@ -104,7 +104,7 @@ static int send_bitstream(const void *rbf_data, size_t rbf_size)
udelay(20000);
}
WATCHDOG_RESET();
schedule();
}
return 0;
@ -252,7 +252,7 @@ static int reconfig_status_polling_resp(void)
puts(".");
udelay(RECONFIG_STATUS_INTERVAL_DELAY_US);
WATCHDOG_RESET();
schedule();
}
return -ETIMEDOUT;
@ -378,7 +378,7 @@ static int send_reconfig_data(const void *rbf_data, size_t rbf_size,
if (resp_err && !xfer_count)
return resp_err;
}
WATCHDOG_RESET();
schedule();
}
return 0;

8
drivers/fpga/socfpga_arria10.c
View File

@ -383,7 +383,7 @@ static int fpgamgr_program_poll_cd(void)
printf("nstatus == 0 while waiting for condone\n");
return -EPERM;
}
WATCHDOG_RESET();
schedule();
}
if (i == FPGA_TIMEOUT_CNT)
@ -534,7 +534,7 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)
rbf->section = unknown;
break;
WATCHDOG_RESET();
schedule();
}
}
@ -635,7 +635,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
break;
}
}
WATCHDOG_RESET();
schedule();
}
if (!fpga_node_name) {
@ -879,7 +879,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,
total_sizeof_image += buffer_sizebytes_ori;
WATCHDOG_RESET();
schedule();
}
wait_for_fifo_empty();

4
drivers/i2c/mxc_i2c.c
View File

@ -199,7 +199,7 @@ static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state)
}
if ((sr & (state >> 8)) == (unsigned char)state)
return sr;
WATCHDOG_RESET();
schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */
break;
@ -447,7 +447,7 @@ int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus)
sda = dm_gpio_get_value(sda_gpio);
if ((sda & scl) == 1)
break;
WATCHDOG_RESET();
schedule();
elapsed = get_timer(start_time);
if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */
ret = -EBUSY;

12
drivers/mmc/octeontx_hsmmc.c
View File

@ -1023,7 +1023,7 @@ static void octeontx_mmc_cleanup_dma(struct mmc *mmc,
start = get_timer(0);
do {
rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
WATCHDOG_RESET();
schedule();
} while (get_timer(start) < 100 &&
(rsp_sts.s.dma_val || rsp_sts.s.dma_pend));
} while (retries-- >= 0 && rsp_sts.s.dma_pend);
@ -1107,7 +1107,7 @@ static int octeontx_mmc_wait_dma(struct mmc *mmc, bool write, ulong timeout,
} else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) {
break;
}
WATCHDOG_RESET();
schedule();
timed_out = (get_timer(start_time) > timeout);
} while (!timed_out);
@ -1219,7 +1219,7 @@ static int octeontx_mmc_read_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
}
return blkcnt - count;
}
WATCHDOG_RESET();
schedule();
} while (--count);
}
#ifdef DEBUG
@ -1253,7 +1253,7 @@ static int octeontx_mmc_poll_ready(struct mmc *mmc, ulong timeout)
} else if (cmd.response[0] & R1_READY_FOR_DATA) {
return 0;
}
WATCHDOG_RESET();
schedule();
} while (get_timer(start) < timeout);
if (not_ready)
@ -1328,7 +1328,7 @@ static ulong octeontx_mmc_write_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
read_csr(mmc, MIO_EMM_DMA()));
return blkcnt - count;
}
WATCHDOG_RESET();
schedule();
} while (--count);
}
@ -1491,7 +1491,7 @@ static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
start = get_timer(0);
do {
rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
WATCHDOG_RESET();
schedule();
} while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout &&
(get_timer(start) < timeout + 10));
octeontx_mmc_print_rsp_errors(mmc, rsp_sts);

6
drivers/mmc/sh_mmcif.c
View File

@ -242,7 +242,7 @@ static int sh_mmcif_multi_read(struct sh_mmcif_host *host,
for (i = 0; i < blocksize / 4; i++)
*p++ = sh_mmcif_read(&host->regs->ce_data);
WATCHDOG_RESET();
schedule();
}
return 0;
}
@ -309,7 +309,7 @@ static int sh_mmcif_multi_write(struct sh_mmcif_host *host,
for (i = 0; i < blocksize / 4; i++)
sh_mmcif_write(*p++, &host->regs->ce_data);
WATCHDOG_RESET();
schedule();
}
return 0;
}
@ -523,7 +523,7 @@ static int sh_mmcif_send_cmd_common(struct sh_mmcif_host *host,
{
int ret;
WATCHDOG_RESET();
schedule();
switch (cmd->cmdidx) {
case MMC_CMD_APP_CMD:

2
drivers/mmc/stm32_sdmmc2.c
View File

@ -445,7 +445,7 @@ static int stm32_sdmmc2_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
u32 cmdat = data ? SDMMC_CMD_CMDTRANS : 0;
int ret, retry = 3;
WATCHDOG_RESET();
schedule();
retry_cmd:
ctx.data_length = 0;

4
drivers/mtd/cfi_flash.c
View File

@ -584,7 +584,7 @@ static int flash_status_check(flash_info_t *info, flash_sect_t sector,
reset_timer();
#endif
start = get_timer(0);
WATCHDOG_RESET();
schedule();
while (flash_is_busy(info, sector)) {
if (get_timer(start) > tout) {
printf("Flash %s timeout at address %lx data %lx\n",
@ -677,7 +677,7 @@ static int flash_status_poll(flash_info_t *info, void *src, void *dst,
reset_timer();
#endif
start = get_timer(0);
WATCHDOG_RESET();
schedule();
while (1) {
switch (info->portwidth) {
case FLASH_CFI_8BIT:

2
drivers/mtd/nand/core.c
View File

@ -173,7 +173,7 @@ int nanddev_mtd_erase(struct mtd_info *mtd, struct erase_info *einfo)
nanddev_offs_to_pos(nand, einfo->addr, &pos);
nanddev_offs_to_pos(nand, einfo->addr + einfo->len - 1, &last);
while (nanddev_pos_cmp(&pos, &last) <= 0) {
WATCHDOG_RESET();
schedule();
ret = nanddev_erase(nand, &pos);
if (ret) {
einfo->fail_addr = nanddev_pos_to_offs(nand, &pos);

6
drivers/mtd/nand/raw/atmel_nand.c
View File

@ -420,7 +420,7 @@ static int pmecc_err_location(struct mtd_info *mtd)
while (--timeout) {
if (pmecc_readl(host->pmerrloc, elisr) & PMERRLOC_CALC_DONE)
break;
WATCHDOG_RESET();
schedule();
udelay(1);
}
@ -558,7 +558,7 @@ static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
while (--timeout) {
if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
break;
WATCHDOG_RESET();
schedule();
udelay(1);
}
@ -598,7 +598,7 @@ static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
while (--timeout) {
if (!(pmecc_readl(host->pmecc, sr) & PMECC_SR_BUSY))
break;
WATCHDOG_RESET();
schedule();
udelay(1);
}

10
drivers/mtd/nand/raw/nand_base.c
View File

@ -595,7 +595,7 @@ static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
if (status & NAND_STATUS_READY)
break;
WATCHDOG_RESET();
schedule();
}
};
@ -2342,7 +2342,7 @@ static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
while (1) {
unsigned int ecc_failures = mtd->ecc_stats.failed;
WATCHDOG_RESET();
schedule();
bytes = min(mtd->writesize - col, readlen);
aligned = (bytes == mtd->writesize);
@ -2695,7 +2695,7 @@ static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
page = realpage & chip->pagemask;
while (1) {
WATCHDOG_RESET();
schedule();
if (ops->mode == MTD_OPS_RAW)
ret = chip->ecc.read_oob_raw(mtd, chip, page);
@ -3263,7 +3263,7 @@ static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
else
use_bufpoi = 0;
WATCHDOG_RESET();
schedule();
/* Partial page write?, or need to use bounce buffer */
if (use_bufpoi) {
pr_debug("%s: using write bounce buffer for buf@%p\n",
@ -3556,7 +3556,7 @@ int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
instr->state = MTD_ERASING;
while (len) {
WATCHDOG_RESET();
schedule();
/* Check if we have a bad block, we do not erase bad blocks! */
if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<

6
drivers/mtd/nand/raw/nand_util.c
View File

@ -103,7 +103,7 @@ int nand_erase_opts(struct mtd_info *mtd,
erased_length < erase_length;
erase.addr += mtd->erasesize) {
WATCHDOG_RESET();
schedule();
if (opts->lim && (erase.addr >= (opts->offset + opts->lim))) {
puts("Size of erase exceeds limit\n");
@ -638,7 +638,7 @@ int nand_write_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
size_t block_offset = offset & (mtd->erasesize - 1);
size_t write_size, truncated_write_size;
WATCHDOG_RESET();
schedule();
if (nand_block_isbad(mtd, block_start)) {
printf("Skip bad block 0x%08llx\n", block_start);
@ -753,7 +753,7 @@ int nand_read_skip_bad(struct mtd_info *mtd, loff_t offset, size_t *length,
size_t block_offset = offset & (mtd->erasesize - 1);
size_t read_length;
WATCHDOG_RESET();
schedule();
if (nand_block_isbad(mtd, offset & ~(mtd->erasesize - 1))) {
printf("Skipping bad block 0x%08llx\n",

4
drivers/mtd/nand/spi/core.c
View File

@ -579,7 +579,7 @@ static int spinand_mtd_read(struct mtd_info *mtd, loff_t from,
#endif
nanddev_io_for_each_page(nand, from, ops, &iter) {
WATCHDOG_RESET();
schedule();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;
@ -631,7 +631,7 @@ static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
#endif
nanddev_io_for_each_page(nand, to, ops, &iter) {
WATCHDOG_RESET();
schedule();
ret = spinand_select_target(spinand, iter.req.pos.target);
if (ret)
break;

4
drivers/mtd/onenand/onenand_base.c
View File

@ -478,7 +478,7 @@ static int onenand_wait(struct mtd_info *mtd, int state)
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
WATCHDOG_RESET();
schedule();
if (get_timer(time_start) > timeo)
return -EIO;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);
@ -1170,7 +1170,7 @@ static int onenand_bbt_wait(struct mtd_info *mtd, int state)
u32 timeo = (CONFIG_SYS_HZ * 20) / 1000;
u32 time_start = get_timer(0);
do {
WATCHDOG_RESET();
schedule();
if (get_timer(time_start) > timeo)
return ONENAND_BBT_READ_FATAL_ERROR;
interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT);

4
drivers/mtd/spi/spi-nor-core.c
View File

@ -958,7 +958,7 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
addr_known = true;
while (len) {
WATCHDOG_RESET();
schedule();
if (!IS_ENABLED(CONFIG_SPL_BUILD) && ctrlc()) {
addr_known = false;
ret = -EINTR;
@ -1721,7 +1721,7 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
for (i = 0; i < len; ) {
ssize_t written;
loff_t addr = to + i;
WATCHDOG_RESET();
schedule();
/*
* If page_size is a power of two, the offset can be quickly

2
drivers/net/octeontx2/nix.c
View File

@ -580,7 +580,7 @@ int nix_lf_xmit(struct udevice *dev, void *pkt, int pkt_len)
__iowmb();
result = lmt_submit((u64)(nix->nix_base +
NIXX_LF_OP_SENDX(0)));
WATCHDOG_RESET();
schedule();
} while (result == 0);
return 0;

32
drivers/net/octeontx2/nix_af.c
View File

@ -65,7 +65,7 @@ int npa_attach_aura(struct nix_af *nix_af, int lf,
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
WATCHDOG_RESET();
schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good\n",
__func__, res->s.compcode);
@ -111,7 +111,7 @@ int npa_attach_pool(struct nix_af *nix_af, int lf,
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
WATCHDOG_RESET();
schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good\n",
@ -136,7 +136,7 @@ int npa_lf_admin_setup(struct npa *npa, int lf, dma_addr_t aura_base)
do {
lf_rst.u = npa_af_reg_read(npa_af, NPA_AF_LF_RST());
WATCHDOG_RESET();
schedule();
} while (lf_rst.s.exec);
/* Set Aura size and enable caching of contexts */
@ -199,7 +199,7 @@ int npa_lf_admin_shutdown(struct nix_af *nix_af, int lf, u32 pool_count)
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
WATCHDOG_RESET();
schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good for lf %d\n"
@ -235,7 +235,7 @@ int npa_lf_admin_shutdown(struct nix_af *nix_af, int lf, u32 pool_count)
start = get_timer(0);
while ((res->s.compcode == NPA_AQ_COMP_E_NOTDONE) &&
(get_timer(start) < 1000))
WATCHDOG_RESET();
schedule();
if (res->s.compcode != NPA_AQ_COMP_E_GOOD) {
printf("%s: Error: result 0x%x not good for lf %d\n"
@ -255,7 +255,7 @@ int npa_lf_admin_shutdown(struct nix_af *nix_af, int lf, u32 pool_count)
do {
lf_rst.u = npa_af_reg_read(npa, NPA_AF_LF_RST());
WATCHDOG_RESET();
schedule();
} while (lf_rst.s.exec);
return 0;
@ -286,7 +286,7 @@ int npa_af_setup(struct npa_af *npa_af)
/* Wait for reset to complete */
do {
blk_rst.u = npa_af_reg_read(npa_af, NPA_AF_BLK_RST());
WATCHDOG_RESET();
schedule();
} while (blk_rst.s.busy);
/* Set little Endian */
@ -318,7 +318,7 @@ int npa_af_shutdown(struct npa_af *npa_af)
/* Wait for reset to complete */
do {
blk_rst.u = npa_af_reg_read(npa_af, NPA_AF_BLK_RST());
WATCHDOG_RESET();
schedule();
} while (blk_rst.s.busy);
rvu_aq_free(&npa_af->aq);
@ -481,7 +481,7 @@ static int nix_aq_issue_command(struct nix_af *nix_af,
start = get_timer(0);
/* Wait for completion */
do {
WATCHDOG_RESET();
schedule();
dsb();
} while (result->s.compcode == 0 && get_timer(start) < 2);
@ -645,7 +645,7 @@ int nix_lf_admin_setup(struct nix *nix)
do {
lf_rst.u = nix_af_reg_read(nix_af, NIXX_AF_LF_RST());
WATCHDOG_RESET();
schedule();
} while (lf_rst.s.exec);
/* Config NIX RQ HW context and base*/
@ -767,7 +767,7 @@ int nix_lf_admin_shutdown(struct nix_af *nix_af, int lf,
do {
sw_sync.u = nix_af_reg_read(nix_af, NIXX_AF_RX_SW_SYNC());
WATCHDOG_RESET();
schedule();
} while (sw_sync.s.ena);
for (index = 0; index < rq_count; index++) {
@ -832,7 +832,7 @@ int nix_lf_admin_shutdown(struct nix_af *nix_af, int lf,
do {
lf_rst.u = nix_af_reg_read(nix_af, NIXX_AF_LF_RST());
WATCHDOG_RESET();
schedule();
} while (lf_rst.s.exec);
return 0;
@ -972,7 +972,7 @@ int npc_af_shutdown(struct nix_af *nix_af)
/* Wait for reset to complete */
do {
blk_rst.u = npc_af_reg_read(nix_af, NPC_AF_BLK_RST());
WATCHDOG_RESET();
schedule();
} while (blk_rst.s.busy);
debug("%s: npc af reset --\n", __func__);
@ -1008,7 +1008,7 @@ int nix_af_setup(struct nix_af *nix_af)
/* Wait for reset to complete */
do {
blk_rst.u = nix_af_reg_read(nix_af, NIXX_AF_BLK_RST());
WATCHDOG_RESET();
schedule();
} while (blk_rst.s.busy);
/* Put in LE mode */
@ -1031,7 +1031,7 @@ int nix_af_setup(struct nix_af *nix_af)
/* Wait for calibration to complete */
do {
af_status.u = nix_af_reg_read(nix_af, NIXX_AF_STATUS());
WATCHDOG_RESET();
schedule();
} while (af_status.s.calibrate_done == 0);
af_cfg.u = nix_af_reg_read(nix_af, NIXX_AF_CFG());
@ -1091,7 +1091,7 @@ int nix_af_shutdown(struct nix_af *nix_af)
/* Wait for reset to complete */
do {
blk_rst.u = nix_af_reg_read(nix_af, NIXX_AF_BLK_RST());
WATCHDOG_RESET();
schedule();
} while (blk_rst.s.busy);
rvu_aq_free(&nix_af->aq);

2
drivers/ram/stm32mp1/stm32mp1_tests.c
View File

@ -169,7 +169,7 @@ static int test_loop_end(u32 *loop, u32 nb_loop, u32 progress)
return 1;
}
printf("loop #%d\n", *loop);
WATCHDOG_RESET();
schedule();
return 0;
}

2
drivers/serial/atmel_usart.c
View File

@ -103,7 +103,7 @@ static int atmel_serial_getc(void)
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
while (!(readl(&usart->csr) & USART3_BIT(RXRDY)))
WATCHDOG_RESET();
schedule();
return readl(&usart->rhr);
}

6
drivers/serial/ns16550.c
View File

@ -296,7 +296,7 @@ void ns16550_putc(struct ns16550 *com_port, char c)
* in puts().
*/
if (c == '\n')
WATCHDOG_RESET();
schedule();
}
#ifndef CONFIG_NS16550_MIN_FUNCTIONS
@ -307,7 +307,7 @@ char ns16550_getc(struct ns16550 *com_port)
extern void usbtty_poll(void);
usbtty_poll();
#endif
WATCHDOG_RESET();
schedule();
}
return serial_in(&com_port->rbr);
}
@ -395,7 +395,7 @@ static int ns16550_serial_putc(struct udevice *dev, const char ch)
* in puts().
*/
if (ch == '\n')
WATCHDOG_RESET();
schedule();
return 0;
}

2
drivers/serial/serial-uclass.c
View File

@ -246,7 +246,7 @@ static int __serial_getc(struct udevice *dev)
do {
err = ops->getc(dev);
if (err == -EAGAIN)
WATCHDOG_RESET();
schedule();
} while (err == -EAGAIN);
return err >= 0 ? err : 0;

2
drivers/serial/serial_bcm283x_mu.c
View File

@ -114,7 +114,7 @@ static int bcm283x_mu_serial_pending(struct udevice *dev, bool input)
lsr = readl(&regs->lsr);
if (input) {
WATCHDOG_RESET();
schedule();
return (lsr & BCM283X_MU_LSR_RX_READY) ? 1 : 0;
} else {
return (lsr & BCM283X_MU_LSR_TX_IDLE) ? 0 : 1;

8
drivers/serial/serial_lpuart.c
View File

@ -169,7 +169,7 @@ static int _lpuart_serial_getc(struct lpuart_serial_plat *plat)
{
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & (US1_RDRF | US1_OR)))
WATCHDOG_RESET();
schedule();
barrier();
@ -182,7 +182,7 @@ static void _lpuart_serial_putc(struct lpuart_serial_plat *plat,
struct lpuart_fsl *base = plat->reg;
while (!(__raw_readb(&base->us1) & US1_TDRE))
WATCHDOG_RESET();
schedule();
__raw_writeb(c, &base->ud);
}
@ -330,7 +330,7 @@ static int _lpuart32_serial_getc(struct lpuart_serial_plat *plat)
lpuart_read32(plat->flags, &base->stat, &stat);
while ((stat & STAT_RDRF) == 0) {
lpuart_write32(plat->flags, &base->stat, STAT_FLAGS);
WATCHDOG_RESET();
schedule();
lpuart_read32(plat->flags, &base->stat, &stat);
}
@ -358,7 +358,7 @@ static void _lpuart32_serial_putc(struct lpuart_serial_plat *plat,
if ((stat & STAT_TDRE))
break;
WATCHDOG_RESET();
schedule();
}
lpuart_write32(plat->flags, &base->data, c);

4
drivers/serial/serial_mpc8xx.c
View File

@ -187,7 +187,7 @@ static int serial_mpc8xx_putc(struct udevice *dev, const char c)
setbits_be16(&rtx->txbd.cbd_sc, BD_SC_READY);
while (in_be16(&rtx->txbd.cbd_sc) & BD_SC_READY)
WATCHDOG_RESET();
schedule();
return 0;
}
@ -204,7 +204,7 @@ static int serial_mpc8xx_getc(struct udevice *dev)
/* Wait for character to show up. */
while (in_be16(&rtx->rxbd.cbd_sc) & BD_SC_EMPTY)
WATCHDOG_RESET();
schedule();
/* the characters are read one by one,
* use the rxindex to know the next char to deliver

2
drivers/serial/serial_mt7620.c
View File

@ -102,7 +102,7 @@ static int mt7620_serial_putc(struct udevice *dev, const char ch)
writel(ch, &plat->regs->thr);
if (ch == '\n')
WATCHDOG_RESET();
schedule();
return 0;
}

4
drivers/serial/serial_mtk.c
View File

@ -141,7 +141,7 @@ static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch)
writel(ch, &priv->regs->thr);
if (ch == '\n')
WATCHDOG_RESET();
schedule();
return 0;
}
@ -295,7 +295,7 @@ DECLARE_GLOBAL_DATA_PTR;
do { \
err = _mtk_serial_getc(&mtk_hsuart##port); \
if (err == -EAGAIN) \
WATCHDOG_RESET(); \
schedule(); \
} while (err == -EAGAIN); \
return err >= 0 ? err : 0; \
} \

6
drivers/serial/serial_mxc.c
View File

@ -200,7 +200,7 @@ static void mxc_serial_setbrg(void)
static int mxc_serial_getc(void)
{
while (readl(&mxc_base->ts) & UTS_RXEMPTY)
WATCHDOG_RESET();
schedule();
return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */
}
@ -214,7 +214,7 @@ static void mxc_serial_putc(const char c)
/* wait for transmitter to be ready */
while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))
WATCHDOG_RESET();
schedule();
}
/* Test whether a character is in the RX buffer */
@ -384,7 +384,7 @@ static inline void _debug_uart_putc(int ch)
struct mxc_uart *base = (struct mxc_uart *)CONFIG_VAL(DEBUG_UART_BASE);
while (!(readl(&base->ts) & UTS_TXEMPTY))
WATCHDOG_RESET();
schedule();
writel(ch, &base->txd);
}

2
drivers/serial/serial_octeon_bootcmd.c
View File

@ -98,7 +98,7 @@ static int octeon_bootcmd_getc(struct udevice *dev)
}
while (!octeon_bootcmd_pending(dev, true)) {
WATCHDOG_RESET();
schedule();
/*
* ToDo:
* The original code calls octeon_board_poll() here. We may

4
drivers/serial/serial_octeon_pcie_console.c
View File

@ -134,7 +134,7 @@ static int octeon_pcie_console_read(struct udevice *dev,
cons_ptr->input_write_index,
cons_ptr->input_read_index))) {
mdelay(10);
WATCHDOG_RESET();
schedule();
}
}
@ -210,7 +210,7 @@ static int octeon_pcie_console_write(struct udevice *dev,
if (flags & OCT_PCI_CON_FLAG_NONBLOCK)
goto done;
WATCHDOG_RESET();
schedule();
mdelay(10); /* Delay if we are spinning */
} else {
bytes_written = -1;

8
drivers/serial/serial_pl01x.c
View File

@ -70,7 +70,7 @@ static int pl01x_getc(struct pl01x_regs *regs)
static int pl01x_tstc(struct pl01x_regs *regs)
{
WATCHDOG_RESET();
schedule();
return !(readl(&regs->fr) & UART_PL01x_FR_RXFE);
}
@ -227,7 +227,7 @@ static int pl01x_serial_getc(void)
int ch = pl01x_getc(base_regs);
if (ch == -EAGAIN) {
WATCHDOG_RESET();
schedule();
continue;
}
@ -247,9 +247,9 @@ static void pl01x_serial_setbrg(void)
* crap in console
*/
while (!(readl(&base_regs->fr) & UART_PL01x_FR_TXFE))
WATCHDOG_RESET();
schedule();
while (readl(&base_regs->fr) & UART_PL01x_FR_BUSY)
WATCHDOG_RESET();
schedule();
pl01x_serial_init_baud(gd->baudrate);
}

2
drivers/serial/serial_sifive.c
View File

@ -225,7 +225,7 @@ static inline void _debug_uart_putc(int ch)
(struct uart_sifive *)CONFIG_VAL(DEBUG_UART_BASE);
while (_sifive_serial_putc(regs, ch) == -EAGAIN)
WATCHDOG_RESET();
schedule();
}
DEBUG_UART_FUNCS

2
drivers/serial/serial_zynq.c
View File

@ -307,7 +307,7 @@ static inline void _debug_uart_putc(int ch)
struct uart_zynq *regs = (struct uart_zynq *)CONFIG_VAL(DEBUG_UART_BASE);
while (_uart_zynq_serial_putc(regs, ch) == -EAGAIN)
WATCHDOG_RESET();
schedule();
}
DEBUG_UART_FUNCS

2
drivers/spi/mtk_snfi_spi.c
View File

@ -202,7 +202,7 @@ static int mtk_snfi_exec_op(struct spi_slave *slave,
int addr_sh;
int ret;
WATCHDOG_RESET();
schedule();
ret = mtk_snfi_mac_reset(priv);
if (ret)

2
drivers/spi/octeon_spi.c
View File

@ -126,7 +126,7 @@ static void octeon_spi_wait_ready(struct udevice *dev)
do {
mpi_sts = readq(base + MPI_STS);
WATCHDOG_RESET();
schedule();
} while (mpi_sts & MPI_STS_BUSY);
debug("%s(%s)\n", __func__, dev->name);

2
drivers/spi/stm32_qspi.c
View File

@ -172,7 +172,7 @@ static int _stm32_qspi_wait_cmd(struct stm32_qspi_priv *priv,
static void _stm32_qspi_read_fifo(u8 *val, void __iomem *addr)
{
*val = readb(addr);
WATCHDOG_RESET();
schedule();
}
static void _stm32_qspi_write_fifo(u8 *val, void __iomem *addr)

4
drivers/timer/mpc83xx_timer.c
View File

@ -176,7 +176,7 @@ void timer_interrupt(struct pt_regs *regs)
#if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
if (CONFIG_SYS_WATCHDOG_FREQ && (priv->timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
WATCHDOG_RESET();
schedule();
#endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
#ifdef CONFIG_LED_STATUS
@ -189,7 +189,7 @@ void wait_ticks(ulong ticks)
ulong end = get_ticks() + ticks;
while (end > get_ticks())
WATCHDOG_RESET();
schedule();
}
static u64 mpc83xx_timer_get_count(struct udevice *dev)

4
drivers/usb/eth/lan7x.h
View File

@ -157,7 +157,7 @@ static inline int lan7x_wait_for_bit(struct usb_device *udev,
}
udelay(1);
WATCHDOG_RESET();
schedule();
}
debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,
@ -199,7 +199,7 @@ static inline int lan7x_mdio_wait_for_bit(struct usb_device *udev,
}
udelay(1);
WATCHDOG_RESET();
schedule();
}
debug("%s: Timeout (reg=0x%x mask=%08x wait_set=%i)\n", prefix, reg,

4
drivers/usb/gadget/f_acm.c
View File

@ -579,7 +579,7 @@ static int acm_stdio_getc(struct stdio_dev *dev)
/* Wait for a character to arrive. */
while (!acm_stdio_tstc(dev))
WATCHDOG_RESET();
schedule();
buf_pop(&f_acm->rx_buf, &c, 1);
@ -639,7 +639,7 @@ static int acm_stdio_start(struct stdio_dev *dev)
if (ctrlc())
return -ECANCELED;
WATCHDOG_RESET();
schedule();
}
return 0;

4
drivers/usb/gadget/f_sdp.c
View File

@ -711,7 +711,7 @@ int sdp_init(int controller_index)
return 1;
}
WATCHDOG_RESET();
schedule();
usb_gadget_handle_interrupts(controller_index);
}
@ -927,7 +927,7 @@ int spl_sdp_handle(int controller_index, struct spl_image_info *spl_image,
if (flag == SDP_EXIT)
return 0;
WATCHDOG_RESET();
schedule();
usb_gadget_handle_interrupts(controller_index);
#ifdef CONFIG_SPL_BUILD

2
drivers/usb/host/ehci-hcd.c
View File

@ -641,7 +641,7 @@ ehci_submit_async(struct usb_device *dev, unsigned long pipe, void *buffer,
token = hc32_to_cpu(vtd->qt_token);
if (!(QT_TOKEN_GET_STATUS(token) & QT_TOKEN_STATUS_ACTIVE))
break;
WATCHDOG_RESET();
schedule();
} while (get_timer(ts) < timeout);
qhtoken = hc32_to_cpu(qh->qh_overlay.qt_token);

2
drivers/usb/musb-new/musb_uboot.c
View File

@ -378,7 +378,7 @@ static struct musb *gadget;
int usb_gadget_handle_interrupts(int index)
{
WATCHDOG_RESET();
schedule();
if (!gadget || !gadget->isr)
return -EINVAL;

4
drivers/video/video_bmp.c
View File

@ -329,7 +329,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
byte_width = width;
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
schedule();
for (j = 0; j < width; j++) {
write_pix8(fb, bpix, eformat, palette, bmap);
bmap++;
@ -342,7 +342,7 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y,
case 16:
if (IS_ENABLED(CONFIG_BMP_16BPP)) {
for (i = 0; i < height; ++i) {
WATCHDOG_RESET();
schedule();
for (j = 0; j < width; j++) {
*fb++ = *bmap++;
*fb++ = *bmap++;

2
env/common.c vendored
View File

@ -115,7 +115,7 @@ char *env_get(const char *name)
if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */
struct env_entry e, *ep;
WATCHDOG_RESET();
schedule();
e.key = name;
e.data = NULL;

3
fs/cramfs/uncompress.c
View File

@ -21,6 +21,7 @@
*/
#include <common.h>
#include <cyclic.h>
#include <malloc.h>
#include <watchdog.h>
#include <u-boot/zlib.h>
@ -62,7 +63,7 @@ int cramfs_uncompress_init (void)
stream.avail_in = 0;
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
stream.outcb = (cb_func)watchdog_reset_func;
stream.outcb = (cb_func)cyclic_run;
#else
stream.outcb = Z_NULL;
#endif /* CONFIG_HW_WATCHDOG */

2
fs/jffs2/jffs2_1pass.c
View File

@ -1523,7 +1523,7 @@ jffs2_1pass_build_lists(struct part_info * part)
/* Set buf_size to maximum length */
buf_size = DEFAULT_EMPTY_SCAN_SIZE;
WATCHDOG_RESET();
schedule();
#ifdef CONFIG_JFFS2_SUMMARY
buf_len = sizeof(*sm);

2
include/linux/compat.h
View File

@ -2,6 +2,7 @@
#define _LINUX_COMPAT_H_
#include <console.h>
#include <cyclic.h>
#include <log.h>
#include <malloc.h>
@ -230,7 +231,6 @@ typedef unsigned long blkcnt_t;
#define try_to_freeze(...) 0
#define set_current_state(...) do { } while (0)
#define kthread_should_stop(...) 0
#define schedule() do { } while (0)
#define setup_timer(timer, func, data) do {} while (0)
#define del_timer_sync(timer) do {} while (0)

2
include/wait_bit.h
View File

@ -63,7 +63,7 @@ static inline int wait_for_bit_##sfx(const void *reg, \
} \
\
udelay(1); \
WATCHDOG_RESET(); \
schedule(); \
} \
\
debug("%s: Timeout (reg=%p mask=%x wait_set=%i)\n", __func__, \

8
include/watchdog.h
View File

@ -88,14 +88,6 @@ int init_func_watchdog_reset(void);
#endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
#endif /* CONFIG_HW_WATCHDOG */
#if !defined(__ASSEMBLY__)
/* Currently only needed for fs/cramfs/uncompress.c */
static inline void watchdog_reset_func(void)
{
WATCHDOG_RESET();
}
#endif
/*
* Prototypes from $(CPU)/cpu.c.
*/

2
lib/bzip2/bzlib.c
View File

@ -844,7 +844,7 @@ int BZ_API(BZ2_bzDecompress) ( bz_stream *strm )
while (True) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
if (s->state == BZ_X_IDLE) return BZ_SEQUENCE_ERROR;
if (s->state == BZ_X_OUTPUT) {

8
lib/bzip2/bzlib_decompress.c
View File

@ -418,7 +418,7 @@ Int32 BZ2_decompress ( DState* s )
while (True) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
if (nextSym == EOB) break;
@ -503,7 +503,7 @@ Int32 BZ2_decompress ( DState* s )
kk = MTFA_SIZE-1;
for (ii = 256 / MTFL_SIZE-1; ii >= 0; ii--) {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
for (jj = MTFL_SIZE-1; jj >= 0; jj--) {
s->mtfa[kk] = s->mtfa[s->mtfbase[ii] + jj];
@ -568,7 +568,7 @@ Int32 BZ2_decompress ( DState* s )
while (i != s->origPtr);
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
s->tPos = s->origPtr;
s->nblock_used = 0;
@ -583,7 +583,7 @@ Int32 BZ2_decompress ( DState* s )
} else {
#if defined(CONFIG_HW_WATCHDOG) || defined(CONFIG_WATCHDOG)
WATCHDOG_RESET();
schedule();
#endif
/*-- compute the T^(-1) vector --*/
for (i = 0; i < nblock; i++) {

2
lib/crc32.c
View File

@ -255,7 +255,7 @@ uint32_t crc32_wd(uint32_t crc, const unsigned char *buf, uInt len,
chunk = chunk_sz;
crc = crc32(crc, curr, chunk);
curr += chunk;
WATCHDOG_RESET ();
schedule();
}
#else
crc = crc32(crc, buf, len);

4
lib/efi_loader/efi_boottime.c
View File

@ -828,7 +828,7 @@ void efi_timer_check(void)
efi_signal_event(evt);
}
efi_process_event_queue();
WATCHDOG_RESET();
schedule();
}
/**
@ -2193,7 +2193,7 @@ static efi_status_t EFIAPI efi_exit_boot_services(efi_handle_t image_handle,
/* Give the payload some time to boot */
efi_set_watchdog(0);
WATCHDOG_RESET();
schedule();
out:
if (IS_ENABLED(CONFIG_EFI_TCG2_PROTOCOL)) {
if (ret != EFI_SUCCESS)

2
lib/gunzip.c
View File

@ -251,7 +251,7 @@ int gzwrite(unsigned char *src, int len,
puts("abort\n");
goto out;
}
WATCHDOG_RESET();
schedule();
} while (s.avail_out == 0);
/* done when inflate() says it's done */
} while (r != Z_STREAM_END);

16
lib/lzma/LzmaDec.c
View File

@ -153,7 +153,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
UInt32 range = p->range;
UInt32 code = p->code;
WATCHDOG_RESET();
schedule();
do
{
@ -177,7 +177,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
state -= (state < 4) ? state : 3;
symbol = 1;
WATCHDOG_RESET();
schedule();
do { GET_BIT(prob + symbol, symbol) } while (symbol < 0x100);
}
@ -188,7 +188,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
state -= (state < 10) ? 3 : 6;
symbol = 1;
WATCHDOG_RESET();
schedule();
do
{
@ -321,7 +321,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
UInt32 mask = 1;
unsigned i = 1;
WATCHDOG_RESET();
schedule();
do
{
@ -335,7 +335,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
{
numDirectBits -= kNumAlignBits;
WATCHDOG_RESET();
schedule();
do
{
@ -409,7 +409,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
const Byte *lim = dest + curLen;
dicPos += curLen;
WATCHDOG_RESET();
schedule();
do
*(dest) = (Byte)*(dest + src);
@ -418,7 +418,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
else
{
WATCHDOG_RESET();
schedule();
do
{
@ -433,7 +433,7 @@ static int MY_FAST_CALL LzmaDec_DecodeReal(CLzmaDec *p, SizeT limit, const Byte
}
while (dicPos < limit && buf < bufLimit);
WATCHDOG_RESET();
schedule();
NORMALIZE;
p->buf = buf;

2
lib/lzma/LzmaTools.c
View File

@ -104,7 +104,7 @@ int lzmaBuffToBuffDecompress(unsigned char *outStream, SizeT *uncompressedSize,
/* Decompress */
outProcessed = min(outSizeFull, *uncompressedSize);
WATCHDOG_RESET();
schedule();
res = LzmaDecode(
outStream, &outProcessed,

2
lib/md5.c
View File

@ -304,7 +304,7 @@ md5_wd(const unsigned char *input, unsigned int len, unsigned char output[16],
chunk = chunk_sz;
MD5Update(&context, curr, chunk);
curr += chunk;
WATCHDOG_RESET ();
schedule();
}
#else
MD5Update(&context, input, len);

2
lib/sha1.c
View File

@ -344,7 +344,7 @@ void sha1_csum_wd(const unsigned char *input, unsigned int ilen,
chunk = chunk_sz;
sha1_update (&ctx, curr, chunk);
curr += chunk;
WATCHDOG_RESET ();
schedule();
}
#else
sha1_update (&ctx, input, ilen);

2
lib/sha256.c
View File

@ -293,7 +293,7 @@ void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
chunk = chunk_sz;
sha256_update(&ctx, curr, chunk);
curr += chunk;
WATCHDOG_RESET();
schedule();
}
#else
sha256_update(&ctx, input, ilen);

4
lib/sha512.c
View File

@ -309,7 +309,7 @@ void sha384_csum_wd(const unsigned char *input, unsigned int ilen,
chunk = chunk_sz;
sha384_update(&ctx, curr, chunk);
curr += chunk;
WATCHDOG_RESET();
schedule();
}
#else
sha384_update(&ctx, input, ilen);
@ -372,7 +372,7 @@ void sha512_csum_wd(const unsigned char *input, unsigned int ilen,
chunk = chunk_sz;
sha512_update(&ctx, curr, chunk);
curr += chunk;
WATCHDOG_RESET();
schedule();
}
#else
sha512_update(&ctx, input, ilen);

2
lib/time.c
View File

@ -198,7 +198,7 @@ void udelay(unsigned long usec)
ulong kv;
do {
WATCHDOG_RESET();
schedule();
kv = usec > CONFIG_WD_PERIOD ? CONFIG_WD_PERIOD : usec;
__udelay(kv);
usec -= kv;

8
lib/zlib/inflate.c
View File

@ -25,7 +25,7 @@ int ZEXPORT inflateReset(z_streamp strm)
state->hold = 0;
state->bits = 0;
state->lencode = state->distcode = state->next = state->codes;
WATCHDOG_RESET();
schedule();
Tracev((stderr, "inflate: reset\n"));
return Z_OK;
}
@ -543,7 +543,7 @@ int ZEXPORT inflate(z_streamp strm, int flush)
strm->adler = state->check = adler32(0L, Z_NULL, 0);
state->mode = TYPE;
case TYPE:
WATCHDOG_RESET();
schedule();
if (flush == Z_BLOCK) goto inf_leave;
case TYPEDO:
if (state->last) {
@ -721,7 +721,7 @@ int ZEXPORT inflate(z_streamp strm, int flush)
Tracev((stderr, "inflate: codes ok\n"));
state->mode = LEN;
case LEN:
WATCHDOG_RESET();
schedule();
if (have >= 6 && left >= 258) {
RESTORE();
inflate_fast(strm, out);
@ -933,7 +933,7 @@ int ZEXPORT inflateEnd(z_streamp strm)
return Z_STREAM_ERROR;
state = (struct inflate_state FAR *)strm->state;
if (state->window != Z_NULL) {
WATCHDOG_RESET();
schedule();
ZFREE(strm, state->window);
}
ZFREE(strm, strm->state);

2
net/net.c
View File

@ -559,7 +559,7 @@ restart:
* someone sets `net_state' to a state that terminates.
*/
for (;;) {
WATCHDOG_RESET();
schedule();
if (arp_timeout_check() > 0)
time_start = get_timer(0);

2
post/cpu/mpc83xx/ecc.c
View File

@ -73,7 +73,7 @@ int ecc_post_test(int flags)
for (addr = (u64*)CONFIG_SYS_POST_ECC_START_ADDR, errbit=0;
addr < (u64*)CONFIG_SYS_POST_ECC_STOP_ADDR; addr++, errbit++ ) {
WATCHDOG_RESET();
schedule();
ecc_clear(ddr);

36
post/drivers/memory.c
View File

@ -279,7 +279,7 @@ static int memory_post_test1(unsigned long start,
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = val;
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
@ -292,7 +292,7 @@ static int memory_post_test1(unsigned long start,
break;
}
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
return ret;
@ -308,7 +308,7 @@ static int memory_post_test2(unsigned long start, unsigned long size)
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = 1 << (i % 32);
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
@ -321,7 +321,7 @@ static int memory_post_test2(unsigned long start, unsigned long size)
break;
}
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
return ret;
@ -337,7 +337,7 @@ static int memory_post_test3(unsigned long start, unsigned long size)
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = i;
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
@ -350,7 +350,7 @@ static int memory_post_test3(unsigned long start, unsigned long size)
break;
}
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
return ret;
@ -366,7 +366,7 @@ static int memory_post_test4(unsigned long start, unsigned long size)
for (i = 0; i < size / sizeof (ulong); i++) {
mem[i] = ~i;
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
for (i = 0; i < size / sizeof (ulong) && !ret; i++) {
@ -379,7 +379,7 @@ static int memory_post_test4(unsigned long start, unsigned long size)
break;
}
if (i % 1024 == 0)
WATCHDOG_RESET();
schedule();
}
return ret;
@ -390,15 +390,15 @@ static int memory_post_test_lines(unsigned long start, unsigned long size)
int ret = 0;
ret = memory_post_dataline((unsigned long long *)start);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_addrline((ulong *)start, (ulong *)start,
size);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_addrline((ulong *)(start+size-8),
(ulong *)start, size);
WATCHDOG_RESET();
schedule();
return ret;
}
@ -408,25 +408,25 @@ static int memory_post_test_patterns(unsigned long start, unsigned long size)
int ret = 0;
ret = memory_post_test1(start, size, 0x00000000);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test1(start, size, 0xffffffff);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test1(start, size, 0x55555555);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test1(start, size, 0xaaaaaaaa);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test2(start, size);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test3(start, size);
WATCHDOG_RESET();
schedule();
if (!ret)
ret = memory_post_test4(start, size);
WATCHDOG_RESET();
schedule();
return ret;
}

16
post/lib_powerpc/cpu.c
View File

@ -61,7 +61,7 @@ int cpu_post_test (int flags)
int ic = icache_status();
int ret = 0;
WATCHDOG_RESET();
schedule();
if (ic)
icache_disable();
@ -73,7 +73,7 @@ int cpu_post_test (int flags)
ret = cpu_post_test_two ();
if (ret == 0)
ret = cpu_post_test_twox ();
WATCHDOG_RESET();
schedule();
if (ret == 0)
ret = cpu_post_test_three ();
if (ret == 0)
@ -82,7 +82,7 @@ int cpu_post_test (int flags)
ret = cpu_post_test_threei ();
if (ret == 0)
ret = cpu_post_test_andi ();
WATCHDOG_RESET();
schedule();
if (ret == 0)
ret = cpu_post_test_srawi ();
if (ret == 0)
@ -91,7 +91,7 @@ int cpu_post_test (int flags)
ret = cpu_post_test_rlwinm ();
if (ret == 0)
ret = cpu_post_test_rlwimi ();
WATCHDOG_RESET();
schedule();
if (ret == 0)
ret = cpu_post_test_store ();
if (ret == 0)
@ -100,20 +100,20 @@ int cpu_post_test (int flags)
ret = cpu_post_test_cr ();
if (ret == 0)
ret = cpu_post_test_b ();
WATCHDOG_RESET();
schedule();
if (ret == 0)
ret = cpu_post_test_multi ();
WATCHDOG_RESET();
schedule();
if (ret == 0)
ret = cpu_post_test_string ();
if (ret == 0)
ret = cpu_post_test_complex ();
WATCHDOG_RESET();
schedule();
if (ic)
icache_enable();
WATCHDOG_RESET();
schedule();
return ret;
}

4
post/lib_powerpc/fpu/fpu.c
View File

@ -43,7 +43,7 @@ int fpu_post_test (int flags)
int ret = 0;
WATCHDOG_RESET ();
schedule();
if (!fpu)
fpu_enable ();
@ -66,7 +66,7 @@ int fpu_post_test (int flags)
if (!fpu)
fpu_disable ();
WATCHDOG_RESET ();
schedule();
return ret;
}

Some files were not shown because too many files have changed in this diff Show More