arm: mvebu: a38x: Detect CONFIG_SYS_TCLK from SAR register

Bit 15 in SAR register specifies if TCLK is running at 200 MHz or 250 MHz.
Use this information instead of manual configuration in every board file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Pali Rohár
2021-07-31 14:22:52 +02:00
committed by Stefan Roese
parent 293a8de6fa
commit 29795302b9
8 changed files with 8 additions and 16 deletions

View File

@@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

View File

@@ -20,8 +20,6 @@
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
#define CONFIG_LOADADDR 1000000
/*

View File

@@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 200000000 /* 200MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

View File

@@ -10,8 +10,6 @@
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* I2C */
#define CONFIG_SYS_I2C_LEGACY
#define CONFIG_SYS_I2C_MVTWSI

View File

@@ -17,7 +17,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

View File

@@ -16,7 +16,6 @@
* for DDR ECC byte filling in the SPL before loading the main
* U-Boot into it.
*/
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/* USB/EHCI configuration */
#define CONFIG_EHCI_IS_TDI

View File

@@ -12,8 +12,6 @@
#define CONFIG_DISPLAY_BOARDINFO_LATE
#define CONFIG_SYS_TCLK 250000000 /* 250MHz */
/*
* NS16550 Configuration
*/