phy: Add Amlogic Meson USB2 & USB3 Generic PHY drivers
The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs and an USB3 PHY. This patch adds drivers for these for the standard generic PHY interface and supports the power-on/off calls and set the Host mode by default. They are based on the excellent work from Martin Blumenstingl merged in linux. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
This commit is contained in:
Neil Armstrong
Marek Vasut
parent
7c839ea70c
commit
2960e27e38
@ -110,4 +110,12 @@ config STI_USB_PHY
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used by USB2 and USB3 Host controllers available on
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STiH407 SoC families.
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config MESON_GXL_USB_PHY
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bool "Amlogic Meson GXL USB PHYs"
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depends on PHY && ARCH_MESON && MESON_GXL
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imply REGMAP
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help
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This is the generic phy driver for the Amlogic Meson GXL
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USB2 and USB3 PHYS.
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endmenu
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@ -14,3 +14,4 @@ obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o
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obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
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obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
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obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o
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obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o
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238
drivers/phy/meson-gxl-usb2.c
Normal file
238
drivers/phy/meson-gxl-usb2.c
Normal file
@ -0,0 +1,238 @@
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/*
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* Meson GXL and GXM USB2 PHY driver
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*
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* Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <power/regulator.h>
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#include <clk.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* bits [31:27] are read-only */
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#define U2P_R0 0x0
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#define U2P_R0_BYPASS_SEL BIT(0)
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#define U2P_R0_BYPASS_DM_EN BIT(1)
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#define U2P_R0_BYPASS_DP_EN BIT(2)
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#define U2P_R0_TXBITSTUFF_ENH BIT(3)
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#define U2P_R0_TXBITSTUFF_EN BIT(4)
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#define U2P_R0_DM_PULLDOWN BIT(5)
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#define U2P_R0_DP_PULLDOWN BIT(6)
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#define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
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#define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
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#define U2P_R0_ADP_PRB_EN BIT(9)
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#define U2P_R0_ADP_DISCHARGE BIT(10)
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#define U2P_R0_ADP_CHARGE BIT(11)
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#define U2P_R0_DRV_VBUS BIT(12)
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#define U2P_R0_ID_PULLUP BIT(13)
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#define U2P_R0_LOOPBACK_EN_B BIT(14)
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#define U2P_R0_OTG_DISABLE BIT(15)
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#define U2P_R0_COMMON_ONN BIT(16)
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#define U2P_R0_FSEL_MASK GENMASK(19, 17)
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#define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
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#define U2P_R0_POWER_ON_RESET BIT(22)
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#define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
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#define U2P_R0_ID_SET_ID_DQ BIT(25)
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#define U2P_R0_ATE_RESET BIT(26)
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#define U2P_R0_FSV_MINUS BIT(27)
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#define U2P_R0_FSV_PLUS BIT(28)
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#define U2P_R0_BYPASS_DM_DATA BIT(29)
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#define U2P_R0_BYPASS_DP_DATA BIT(30)
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#define U2P_R1 0x4
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#define U2P_R1_BURN_IN_TEST BIT(0)
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#define U2P_R1_ACA_ENABLE BIT(1)
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#define U2P_R1_DCD_ENABLE BIT(2)
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#define U2P_R1_VDAT_SRC_EN_B BIT(3)
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#define U2P_R1_VDAT_DET_EN_B BIT(4)
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#define U2P_R1_CHARGES_SEL BIT(5)
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#define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
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#define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
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#define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
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#define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
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#define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
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#define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
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#define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
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#define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
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#define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
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#define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
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/* bits [31:14] are read-only */
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#define U2P_R2 0x8
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#define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
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#define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
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#define U2P_R2_TESTDATA_OUT_SEL BIT(12)
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#define U2P_R2_TESTCLK BIT(13)
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#define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
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#define U2P_R2_ACA_PIN_RANGE_C BIT(18)
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#define U2P_R2_ACA_PIN_RANGE_B BIT(19)
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#define U2P_R2_ACA_PIN_RANGE_A BIT(20)
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#define U2P_R2_ACA_PIN_GND BIT(21)
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#define U2P_R2_ACA_PIN_FLOAT BIT(22)
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#define U2P_R2_CHARGE_DETECT BIT(23)
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#define U2P_R2_DEVICE_SESSION_VALID BIT(24)
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#define U2P_R2_ADP_PROBE BIT(25)
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#define U2P_R2_ADP_SENSE BIT(26)
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#define U2P_R2_SESSION_END BIT(27)
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#define U2P_R2_VBUS_VALID BIT(28)
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#define U2P_R2_B_VALID BIT(29)
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#define U2P_R2_A_VALID BIT(30)
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#define U2P_R2_ID_DIG BIT(31)
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#define U2P_R3 0xc
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#define RESET_COMPLETE_TIME 500
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struct phy_meson_gxl_usb2_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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struct udevice *phy_supply;
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#endif
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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};
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static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
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{
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* reset the PHY and wait until settings are stabilized */
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val |= U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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udelay(RESET_COMPLETE_TIME);
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val &= ~U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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udelay(RESET_COMPLETE_TIME);
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}
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static void
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phy_meson_gxl_usb2_set_host_mode(struct phy_meson_gxl_usb2_priv *priv)
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{
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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val |= U2P_R0_DM_PULLDOWN;
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val |= U2P_R0_DP_PULLDOWN;
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val &= ~U2P_R0_ID_PULLUP;
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regmap_write(priv->regmap, U2P_R0, val);
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phy_meson_gxl_usb2_reset(priv);
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}
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static int phy_meson_gxl_usb2_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* power on the PHY by taking it out of reset mode */
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val &= ~U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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phy_meson_gxl_usb2_set_host_mode(priv);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->phy_supply) {
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int ret = regulator_set_enable(priv->phy_supply, true);
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if (ret)
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return ret;
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}
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#endif
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return 0;
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}
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static int phy_meson_gxl_usb2_power_off(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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uint val;
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regmap_read(priv->regmap, U2P_R0, &val);
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/* power off the PHY by putting it into reset mode */
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val |= U2P_R0_POWER_ON_RESET;
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regmap_write(priv->regmap, U2P_R0, val);
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (priv->phy_supply) {
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int ret = regulator_set_enable(priv->phy_supply, false);
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if (ret) {
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pr_err("Error disabling PHY supply\n");
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return ret;
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}
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}
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#endif
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return 0;
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}
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struct phy_ops meson_gxl_usb2_phy_ops = {
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.power_on = phy_meson_gxl_usb2_power_on,
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.power_off = phy_meson_gxl_usb2_power_off,
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};
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int meson_gxl_usb2_phy_probe(struct udevice *dev)
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{
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struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev, &priv->regmap);
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if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
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if (ret && ret != -ENOENT) {
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pr_err("Failed to get PHY regulator\n");
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
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{ .compatible = "amlogic,meson-gxl-usb2-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
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.name = "meson_gxl_usb2_phy",
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.id = UCLASS_PHY,
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.of_match = meson_gxl_usb2_phy_ids,
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.probe = meson_gxl_usb2_phy_probe,
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.ops = &meson_gxl_usb2_phy_ops,
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.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
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};
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201
drivers/phy/meson-gxl-usb3.c
Normal file
201
drivers/phy/meson-gxl-usb3.c
Normal file
@ -0,0 +1,201 @@
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/*
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* Meson GXL USB3 PHY driver
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*
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* Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <bitfield.h>
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#include <dm.h>
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#include <errno.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <clk.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define USB_R0 0x00
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#define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
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#define USB_R0_P30_PHY_RESET BIT(6)
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#define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
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#define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
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#define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
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#define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
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#define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
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#define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
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#define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
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#define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
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#define USB_R0_U2D_ACT BIT(31)
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#define USB_R1 0x04
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#define USB_R1_U3H_BIGENDIAN_GS BIT(0)
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#define USB_R1_U3H_PME_ENABLE BIT(1)
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#define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
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#define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
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#define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
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#define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
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#define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
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#define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
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#define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
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#define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
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#define USB_R2 0x08
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#define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
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#define USB_R2_P30_CR_READ BIT(16)
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#define USB_R2_P30_CR_WRITE BIT(17)
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#define USB_R2_P30_CR_CAP_ADDR BIT(18)
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#define USB_R2_P30_CR_CAP_DATA BIT(19)
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#define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
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#define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
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#define USB_R3 0x0c
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#define USB_R3_P30_SSC_ENABLE BIT(0)
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#define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
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#define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
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#define USB_R3_P30_REF_SSP_EN BIT(13)
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#define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
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#define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
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#define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
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#define USB_R4 0x10
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#define USB_R4_P21_PORT_RESET_0 BIT(0)
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#define USB_R4_P21_SLEEP_M0 BIT(1)
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#define USB_R4_MEM_PD_MASK GENMASK(3, 2)
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#define USB_R4_P21_ONLY BIT(4)
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#define USB_R5 0x14
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#define USB_R5_ID_DIG_SYNC BIT(0)
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#define USB_R5_ID_DIG_REG BIT(1)
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#define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
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#define USB_R5_ID_DIG_EN_0 BIT(4)
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#define USB_R5_ID_DIG_EN_1 BIT(5)
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#define USB_R5_ID_DIG_CURR BIT(6)
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#define USB_R5_ID_DIG_IRQ BIT(7)
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#define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
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#define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
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/* read-only register */
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#define USB_R6 0x18
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#define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
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#define USB_R6_P30_CR_ACK BIT(16)
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struct phy_meson_gxl_usb3_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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};
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static int
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phy_meson_gxl_usb3_set_host_mode(struct phy_meson_gxl_usb3_priv *priv)
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{
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uint val;
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regmap_read(priv->regmap, USB_R0, &val);
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val &= ~USB_R0_U2D_ACT;
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regmap_write(priv->regmap, USB_R0, val);
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regmap_read(priv->regmap, USB_R4, &val);
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val &= ~USB_R4_P21_SLEEP_M0;
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regmap_write(priv->regmap, USB_R4, val);
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return 0;
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}
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static int phy_meson_gxl_usb3_power_on(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
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uint val;
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||||
|
||||
regmap_read(priv->regmap, USB_R5, &val);
|
||||
val |= USB_R5_ID_DIG_EN_0;
|
||||
val |= USB_R5_ID_DIG_EN_1;
|
||||
val &= ~USB_R5_ID_DIG_TH_MASK;
|
||||
val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
|
||||
regmap_write(priv->regmap, USB_R5, val);
|
||||
|
||||
return phy_meson_gxl_usb3_set_host_mode(priv);
|
||||
}
|
||||
|
||||
static int phy_meson_gxl_usb3_power_off(struct phy *phy)
|
||||
{
|
||||
struct udevice *dev = phy->dev;
|
||||
struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
|
||||
uint val;
|
||||
|
||||
regmap_read(priv->regmap, USB_R5, &val);
|
||||
val &= ~USB_R5_ID_DIG_EN_0;
|
||||
val &= ~USB_R5_ID_DIG_EN_1;
|
||||
regmap_write(priv->regmap, USB_R5, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int phy_meson_gxl_usb3_init(struct phy *phy)
|
||||
{
|
||||
struct udevice *dev = phy->dev;
|
||||
struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
|
||||
uint val;
|
||||
|
||||
regmap_read(priv->regmap, USB_R1, &val);
|
||||
val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
|
||||
val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
|
||||
regmap_write(priv->regmap, USB_R1, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
struct phy_ops meson_gxl_usb3_phy_ops = {
|
||||
.init = phy_meson_gxl_usb3_init,
|
||||
.power_on = phy_meson_gxl_usb3_power_on,
|
||||
.power_off = phy_meson_gxl_usb3_power_off,
|
||||
};
|
||||
|
||||
int meson_gxl_usb3_phy_probe(struct udevice *dev)
|
||||
{
|
||||
struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
|
||||
int ret;
|
||||
|
||||
ret = regmap_init_mem(dev, &priv->regmap);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
#if CONFIG_IS_ENABLED(CLK)
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
|
||||
pr_err("failed to enable PHY clock\n");
|
||||
clk_free(&priv->clk);
|
||||
return ret;
|
||||
}
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
|
||||
{ .compatible = "amlogic,meson-gxl-usb3-phy" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
|
||||
.name = "meson_gxl_usb3_phy",
|
||||
.id = UCLASS_PHY,
|
||||
.of_match = meson_gxl_usb3_phy_ids,
|
||||
.probe = meson_gxl_usb3_phy_probe,
|
||||
.ops = &meson_gxl_usb3_phy_ops,
|
||||
.priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user