powerpc/corenet_ds: Slave module for boot from SRIO
For the powerpc processors with SRIO interface, boot location can be configured
from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash
for u-boot image. The image can be fetched from another processor's memory
space by SRIO link connected between them.
The processor boots from SRIO is slave, the processor boots from normal flash
memory space and can help slave to boot from its memory space is master.
They are different environments and requirements:
master:
1. NOR flash for its own u-boot image, ucode and ENV space.
2. Slave's u-boot image in master NOR flash.
3. Normally boot from local NOR flash.
4. Configure SRIO switch system if needed.
slave:
1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
2. Boot location should be set to SRIO1 or SRIO2 by RCW.
3. RCW should configure the SerDes, SRIO interfaces correctly.
4. Slave must be powered on after master's boot.
5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode
locally.
For the slave module, need to finish these processes:
1. Set the boot location to SRIO1 or SRIO2 by RCW.
2. Set a specific TLB entry for the boot process.
3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot.
4. Slave's u-boot image should be generated specifically by
make xxxx_SRIOBOOT_SLAVE_config.
This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
This commit is contained in:
Liu Gang
Andy Fleming
parent
5ffa88eca7
commit
292dc6c501
6
README
6
README
@ -3462,6 +3462,12 @@ within that device.
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Specifies that QE/FMAN firmware is located on the primary SPI
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device. CONFIG_SYS_FMAN_FW_ADDR is the byte offset on that device.
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- CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
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Specifies that QE/FMAN firmware is located in the remote (master)
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memory space. CONFIG_SYS_FMAN_FW_ADDR is a virtual address which
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can be mapped from slave TLB->slave LAW->slave SRIO outbound window
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->master inbound window->master LAW->the ucode address in master's
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NOR flash.
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Building the Software:
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======================
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@ -48,6 +48,15 @@ struct law_entry law_table[] = {
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#ifdef CONFIG_SYS_NAND_BASE_PHYS
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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#endif
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#ifdef CONFIG_SRIOBOOT_SLAVE
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#if defined(CONFIG_SRIOBOOT_SLAVE_PORT0)
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SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M, LAW_TRGT_IF_RIO_1),
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#elif defined(CONFIG_SRIOBOOT_SLAVE_PORT1)
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SET_LAW(CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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LAW_SIZE_1M, LAW_TRGT_IF_RIO_2),
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#endif
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#endif
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -66,6 +66,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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/*
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* SRIOBOOT-SLAVE. When slave boot, the address of the
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* space is at 0xfff00000, it covered the 0xfffff000.
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*/
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SET_TLB_ENTRY(1, CONFIG_SYS_SRIOBOOT_SLAVE_ADDR,
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CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
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0, 0, BOOKE_PAGESZ_1M, 1),
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#else
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SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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@ -752,6 +752,7 @@ P3041DS_SDCARD powerpc mpc85xx corenet_ds freescale
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P3041DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P3041DS:SECURE_BOOT
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P3041DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P3041DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P3041DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_MASTER
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P3041DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P3041DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P3060QDS powerpc mpc85xx p3060qds freescale
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P3060QDS_NAND powerpc mpc85xx p3060qds freescale - P3060QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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P3060QDS_SECURE_BOOT powerpc mpc85xx p3060qds freescale - P3060QDS:SECURE_BOOT
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@ -760,12 +761,14 @@ P4080DS_SDCARD powerpc mpc85xx corenet_ds freescale
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P4080DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P4080DS:SECURE_BOOT
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P4080DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P4080DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P4080DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_MASTER
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P4080DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P4080DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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P5020DS powerpc mpc85xx corenet_ds freescale
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P5020DS_NAND powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SDCARD powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SECURE_BOOT powerpc mpc85xx corenet_ds freescale - P5020DS:SECURE_BOOT
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P5020DS_SPIFLASH powerpc mpc85xx corenet_ds freescale - P5020DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
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P5020DS_SRIOBOOT_MASTER powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_MASTER
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P5020DS_SRIOBOOT_SLAVE powerpc mpc85xx corenet_ds freescale - P5020DS:SRIOBOOT_SLAVE,SYS_TEXT_BASE=0xFFF80000
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stxgp3 powerpc mpc85xx stxgp3 stx
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stxssa powerpc mpc85xx stxssa stx - stxssa
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stxssa_4M powerpc mpc85xx stxssa stx - stxssa:STXSSA_4M
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@ -408,6 +408,8 @@ int fm_init_common(int index, struct ccsr_fman *reg)
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/* flush cache after read */
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flush_cache((ulong)addr, cnt * 512);
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}
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#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
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void *addr = (void *)CONFIG_SYS_QE_FMAN_FW_ADDR;
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#endif
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/* Upload the Fman microcode if it's present */
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@ -33,6 +33,15 @@
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#endif
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#ifdef CONFIG_SRIOBOOT_SLAVE
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/* Set 1M boot space */
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
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#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \
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(0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR)
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#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
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#define CONFIG_SYS_NO_FLASH
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE
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#define CONFIG_E500 /* BOOKE e500 family */
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@ -392,6 +401,15 @@
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#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull
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#endif
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/*
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* SRIOBOOT - SLAVE
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*/
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#ifdef CONFIG_SRIOBOOT_SLAVE
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/* slave port for srioboot */
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#define CONFIG_SRIOBOOT_SLAVE_PORT0
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/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */
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#endif
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/*
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* eSPI - Enhanced SPI
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*/
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@ -512,6 +530,16 @@
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#elif defined(CONFIG_NAND)
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#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
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#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE)
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#elif defined(CONFIG_SRIOBOOT_SLAVE)
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/*
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* Slave has no ucode locally, it can fetch this from remote. When implementing
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* in two corenet boards, slave's ucode could be stored in master's memory
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* space, the address can be mapped from slave TLB->slave LAW->
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* slave SRIO outbound window->master inbound window->master LAW->
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* the ucode address in master's NOR flash.
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*/
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#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
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#define CONFIG_SYS_QE_FMAN_FW_ADDR NULL
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#else
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#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
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#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000
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