Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next

- New SoC platform support: rk3568;
- rockchip pcie Code compile issue fix;
- Board fix for rk3399 Khadas Edge;
- Add Rockchip NFC driver;

drivers/clk/rockchip/Makefile

@@ -14,4 +14,5 @@ obj-$(CONFIG_ROCKCHIP_RK3308) += clk_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
 obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
 obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o

drivers/mtd/nand/raw/Kconfig

@@ -333,6 +333,22 @@ config CORTINA_NAND
 	  The controller supports a maximum 8k page size and supports
 	  a maximum 40-bit error correction per sector of 1024 bytes.
 
+config ROCKCHIP_NAND
+	bool "Support for NAND controller on Rockchip SoCs"
+	depends on ARCH_ROCKCHIP
+	select SYS_NAND_SELF_INIT
+	select DM_MTD
+	imply CMD_NAND
+	help
+	  Enables support for NAND Flash chips on Rockchip SoCs platform.
+	  This controller is found on Rockchip SoCs.
+	  There are four different versions of NAND FLASH Controllers,
+	  including:
+	    NFC v600: RK2928, RK3066, RK3188
+	    NFC v622: RK3036, RK3128
+	    NFC v800: RK3308, RV1108
+	    NFC v900: PX30, RK3326
+
 comment "Generic NAND options"
 
 config SYS_NAND_BLOCK_SIZE

drivers/mtd/nand/raw/Makefile

@@ -70,6 +70,7 @@ obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
 obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
 obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
 obj-$(CONFIG_CORTINA_NAND) += cortina_nand.o
+obj-$(CONFIG_ROCKCHIP_NAND) += rockchip_nfc.o
 
 else  # minimal SPL drivers
 

drivers/pci/pcie_dw_rockchip.c

@@ -61,13 +61,13 @@ struct rk_pcie {
 #define PCIE_CLIENT_DBF_EN		0xffff0003
 
 /* Parameters for the waiting for #perst signal */
-#define PERST_WAIT_MS			1000
+#define MACRO_US			1000
 
 static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 {
 	if ((uintptr_t)addr & (size - 1)) {
 		*val = 0;
-		return PCIBIOS_UNSUPPORTED;
+		return -EOPNOTSUPP;
 	}
 
 	if (size == 4) {
@@ -87,7 +87,7 @@ static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
 static int rk_pcie_write(void __iomem *addr, int size, u32 val)
 {
 	if ((uintptr_t)addr & (size - 1))
-		return PCIBIOS_UNSUPPORTED;
+		return -EOPNOTSUPP;
 
 	if (size == 4)
 		writel(val, addr);
@@ -158,8 +158,6 @@ static inline void rk_pcie_writel_apb(struct rk_pcie *rk_pcie, u32 reg,
  */
 static void rk_pcie_configure(struct rk_pcie *pci, u32 cap_speed)
 {
-	u32 val;
-
 	dw_pcie_dbi_write_enable(&pci->dw, true);
 
 	clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
@@ -251,7 +249,7 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		 * some wired devices need much more, such as 600ms.
 		 * Add a enough delay to cover all cases.
 		 */
-		msleep(PERST_WAIT_MS);
+		udelay(MACRO_US * 1000);
 		dm_gpio_set_value(&priv->rst_gpio, 1);
 	}
 
@@ -273,12 +271,12 @@ static int rk_pcie_link_up(struct rk_pcie *priv, u32 cap_speed)
 		dev_info(priv->dw.dev, "PCIe Linking... LTSSM is 0x%x\n",
 			 rk_pcie_readl_apb(priv, PCIE_CLIENT_LTSSM_STATUS));
 		rk_pcie_debug_dump(priv);
-		msleep(1000);
+		udelay(MACRO_US * 1000);
 	}
 
 	dev_err(priv->dw.dev, "PCIe-%d Link Fail\n", dev_seq(priv->dw.dev));
 	/* Link maybe in Gen switch recovery but we need to wait more 1s */
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 	return -EIO;
 }
 
@@ -298,7 +296,7 @@ static int rockchip_pcie_init_port(struct udevice *dev)
 		}
 	}
 
-	msleep(1000);
+	udelay(MACRO_US * 1000);
 
 	ret = generic_phy_init(&priv->phy);
 	if (ret) {

drivers/ram/rockchip/Makefile

@@ -12,4 +12,5 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
 obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
 obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
 obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
 obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o

drivers/ram/rockchip/sdram_rk3568.c

@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/grf_rk3568.h>
+#include <asm/arch-rockchip/sdram.h>
+
+struct dram_info {
+	struct ram_info info;
+	struct rk3568_pmugrf *pmugrf;
+};
+
+static int rk3568_dmc_probe(struct udevice *dev)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+
+	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.size =
+		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
+
+	return 0;
+}
+
+static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+	struct dram_info *priv = dev_get_priv(dev);
+
+	*info = priv->info;
+
+	return 0;
+}
+
+static struct ram_ops rk3568_dmc_ops = {
+	.get_info = rk3568_dmc_get_info,
+};
+
+static const struct udevice_id rk3568_dmc_ids[] = {
+	{ .compatible = "rockchip,rk3568-dmc" },
+	{ }
+};
+
+U_BOOT_DRIVER(dmc_rk3568) = {
+	.name = "rockchip_rk3568_dmc",
+	.id = UCLASS_RAM,
+	.of_match = rk3568_dmc_ids,
+	.ops = &rk3568_dmc_ops,
+	.probe = rk3568_dmc_probe,
+	.priv_auto = sizeof(struct dram_info),
+};