powerpc/85xx: Add SERDES support for P1010/P1014
Add the ability to determine if a given IP block connected on SERDES is configured. This is useful for things like PCIe and SRIO since they are only ever connected on SERDES. Updated MPC85xx_PORDEVSR_IO_SEL & MPC85xx_PORDEVSR_IO_SEL_SHIFT Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -87,9 +87,11 @@ COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o
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COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
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COBJS-$(CONFIG_MPC8568) += mpc8568_serdes.o
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COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
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COBJS-$(CONFIG_MPC8569) += mpc8569_serdes.o
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COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
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COBJS-$(CONFIG_MPC8572) += mpc8572_serdes.o
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COBJS-$(CONFIG_P1010) += p1010_serdes.o
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COBJS-$(CONFIG_P1011) += p1021_serdes.o
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COBJS-$(CONFIG_P1011) += p1021_serdes.o
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COBJS-$(CONFIG_P1012) += p1021_serdes.o
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COBJS-$(CONFIG_P1012) += p1021_serdes.o
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COBJS-$(CONFIG_P1013) += p1022_serdes.o
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COBJS-$(CONFIG_P1013) += p1022_serdes.o
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COBJS-$(CONFIG_P1014) += p1010_serdes.o
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COBJS-$(CONFIG_P1020) += p1021_serdes.o
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COBJS-$(CONFIG_P1020) += p1021_serdes.o
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COBJS-$(CONFIG_P1021) += p1021_serdes.o
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COBJS-$(CONFIG_P1021) += p1021_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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COBJS-$(CONFIG_P1022) += p1022_serdes.o
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75
arch/powerpc/cpu/mpc85xx/p1010_serdes.c
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75
arch/powerpc/cpu/mpc85xx/p1010_serdes.c
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@ -0,0 +1,75 @@
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/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Author: Prabhakar Kushwaha <prabhakar@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#define SRDS1_MAX_LANES 4
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#define SRDS2_MAX_LANES 2
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static u32 serdes1_prtcl_map, serdes2_prtcl_map;
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static const u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x00] = {NONE, NONE, NONE, NONE},
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[0x01] = {PCIE1, PCIE2, SGMII_TSEC2, SGMII_TSEC3},
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[0x02] = {PCIE1, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
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[0x03] = {NONE, SGMII_TSEC1, SGMII_TSEC2, SGMII_TSEC3},
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};
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static const u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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[0x00] = {NONE, NONE},
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[0x01] = {SATA1, SATA2},
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[0x02] = {SATA1, SATA2},
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[0x03] = {PCIE1, PCIE2},
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret = (1 << device) & serdes1_prtcl_map;
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if (ret)
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return ret;
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return (1 << device) & serdes2_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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int lane;
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debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
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if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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if (srds_cfg > ARRAY_SIZE(serdes2_cfg_tbl)) {
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printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
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return;
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}
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for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds_cfg][lane];
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serdes2_prtcl_map |= (1 << lane_prtcl);
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}
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}
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@ -1874,8 +1874,13 @@ typedef struct ccsr_gur {
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#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
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#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
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#else
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#else
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#if defined(CONFIG_P1010)
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#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
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#else
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#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
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#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
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#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
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#endif /* if defined(CONFIG_P1010) */
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#endif
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#endif
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#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
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#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
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#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
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#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
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