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Merge git://git.denx.de/u-boot-mpc85xx

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This commit is contained in:
Tom Rini 2014-12-08 16:35:07 -05:00
commit 272a1acf1e
115 changed files with 6835 additions and 144 deletions
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4
README
View File

@ -409,6 +409,10 @@ The following options need to be configured:
Enables a workaround for IFC erratum A003399. It is only
requred during NOR boot.
CONFIG_A008044_WORKAROUND
Enables a workaround for T1040/T1042 erratum A008044. It is only
requred during NAND boot and valid for Rev 1.0 SoC revision
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600

10
arch/powerpc/cpu/mpc85xx/Kconfig
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@ -110,6 +110,14 @@ config TARGET_P2041RDB
config TARGET_QEMU_PPCE500
bool "Support qemu-ppce500"
config TARGET_T102XQDS
bool "Support T102xQDS"
select SUPPORT_SPL
config TARGET_T102XRDB
bool "Support T102xRDB"
select SUPPORT_SPL
config TARGET_T1040QDS
bool "Support T1040QDS"
@ -183,6 +191,8 @@ source "board/freescale/p2020come/Kconfig"
source "board/freescale/p2020ds/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"

4
arch/powerpc/cpu/mpc85xx/Makefile
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@ -51,6 +51,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_ids.o
obj-$(CONFIG_PPC_T1042) += t1040_ids.o
obj-$(CONFIG_PPC_T1020) += t1040_ids.o
obj-$(CONFIG_PPC_T1022) += t1040_ids.o
obj-$(CONFIG_PPC_T1023) += t1024_ids.o
obj-$(CONFIG_PPC_T1024) += t1024_ids.o
obj-$(CONFIG_PPC_T2080) += t2080_ids.o
obj-$(CONFIG_PPC_T2081) += t2080_ids.o
@ -97,6 +99,8 @@ obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
obj-$(CONFIG_PPC_T1042) += t1040_serdes.o
obj-$(CONFIG_PPC_T1020) += t1040_serdes.o
obj-$(CONFIG_PPC_T1022) += t1040_serdes.o
obj-$(CONFIG_PPC_T1023) += t1024_serdes.o
obj-$(CONFIG_PPC_T1024) += t1024_serdes.o
obj-$(CONFIG_PPC_T2080) += t2080_serdes.o
obj-$(CONFIG_PPC_T2081) += t2080_serdes.o

4
arch/powerpc/cpu/mpc85xx/b4860_ids.c
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@ -59,8 +59,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
#ifndef CONFIG_PPC_B4420
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),

19
arch/powerpc/cpu/mpc85xx/b4860_serdes.c
View File

@ -18,6 +18,8 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{0x01, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x07, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, NONE, NONE} },
{0x0F, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
{0x17, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x18, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1B, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1D, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x1E, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x21, {NONE, NONE, AURORA, AURORA,
@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
{0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x99, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x9A, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{}

11
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -271,7 +271,8 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
puts("Work-around for Erratum USB14 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
puts("Work-around for Erratum A007186 enabled\n");
if (has_erratum_a007186())
puts("Work-around for Erratum A007186 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
@ -313,6 +314,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
puts("Work-around for Erratum A-005434 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008044) && \
defined(CONFIG_A008044_WORKAROUND)
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A-008044 enabled\n");
#endif
#if defined(CONFIG_SYS_FSL_B4860QDS_XFI_ERR) && defined(CONFIG_B4860QDS)
puts("Work-around for Erratum XFI on B4860QDS enabled\n");
#endif
return 0;
}

3
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
View File

@ -11,6 +11,7 @@
#include <asm/processor.h>
#include <asm/fsl_law.h>
#include <asm/errno.h>
#include <asm/fsl_errata.h>
#include "fsl_corenet2_serdes.h"
#ifdef CONFIG_SYS_FSL_SRDS_1
@ -203,7 +204,7 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
if (sel == 0x01 || sel == 0x02) {
if (has_erratum_a007186() && (sel == 0x01 || sel == 0x02)) {
for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
debug("A007186: pll_num=%x pllcr0=%x\n",

4
arch/powerpc/cpu/mpc85xx/p2041_ids.c
View File

@ -50,8 +50,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),

4
arch/powerpc/cpu/mpc85xx/p3041_ids.c
View File

@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),

4
arch/powerpc/cpu/mpc85xx/p4080_ids.c
View File

@ -40,8 +40,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 196),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 197),
SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000),

4
arch/powerpc/cpu/mpc85xx/p5020_ids.c
View File

@ -51,8 +51,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 197),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 198),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),

4
arch/powerpc/cpu/mpc85xx/p5040_ids.c
View File

@ -42,8 +42,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 196),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 197),
SET_DMA_LIODN(1, 193),
SET_DMA_LIODN(2, 194),
SET_DMA_LIODN(1, "fsl,eloplus-dma", 193),
SET_DMA_LIODN(2, "fsl,eloplus-dma", 194),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);

35
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -37,6 +37,7 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
const u8 core_cplx_PLL[16] = {
[ 0] = 0, /* CC1 PPL / 1 */
@ -122,11 +123,27 @@ void get_sys_info(sys_info_t *sys_info)
/* T4240/T4160 Rev2.0 MEM_PLL_RAT uses a value which is half of
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
*/
#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
defined(CONFIG_PPC_T4080) || defined(CONFIG_PPC_T2080)
svr = get_svr();
switch (SVR_SOC_VER(svr)) {
case SVR_T4240:
case SVR_T4160:
case SVR_T4120:
case SVR_T4080:
if (SVR_MAJ(svr) >= 2)
mem_pll_rat *= 2;
break;
case SVR_T2080:
case SVR_T2081:
if ((SVR_MAJ(svr) > 1) || (SVR_MIN(svr) >= 1))
mem_pll_rat *= 2;
break;
default:
break;
}
#endif
if (mem_pll_rat > 2)
sys_info->freq_ddrbus *= mem_pll_rat;
@ -168,6 +185,9 @@ void get_sys_info(sys_info_t *sys_info)
defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
#define PME_CLK_SEL 0xe0000000
#define PME_CLK_SHIFT 29
@ -175,8 +195,12 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);
#endif
#endif
#ifdef CONFIG_SYS_DPAA_PME
#ifndef CONFIG_PME_PLAT_CLK_DIV
@ -213,7 +237,10 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_SYS_DPAA_QBMAN
sys_info->freq_qman = sys_info->freq_systembus / 2;
#ifndef CONFIG_QBMAN_CLK_DIV
#define CONFIG_QBMAN_CLK_DIV 2
#endif
sys_info->freq_qman = sys_info->freq_systembus / CONFIG_QBMAN_CLK_DIV;
#endif
#ifdef CONFIG_SYS_DPAA_FMAN

82
arch/powerpc/cpu/mpc85xx/t1024_ids.c Normal file
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@ -0,0 +1,82 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#ifdef CONFIG_SYS_DPAA_QBMAN
struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
/* dqrr liodn, frame data liodn, liodn off, sdest */
SET_QP_INFO(1, 27, 1, 0),
SET_QP_INFO(2, 28, 1, 0),
SET_QP_INFO(3, 29, 1, 1),
SET_QP_INFO(4, 30, 1, 1),
SET_QP_INFO(5, 31, 1, 2),
SET_QP_INFO(6, 32, 1, 2),
SET_QP_INFO(7, 33, 1, 3),
SET_QP_INFO(8, 34, 1, 3),
SET_QP_INFO(9, 35, 1, 0),
SET_QP_INFO(10, 36, 1, 0),
};
#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(62),
SET_BMAN_LIODN(63),
#endif
SET_SDHC_LIODN(1, 552),
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
SET_USB_LIODN(2, "fsl-usb2-dr", 554),
SET_SATA_LIODN(1, 555),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
SET_TDM_LIODN(560),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
#ifdef CONFIG_SYS_DPAA_FMAN
struct liodn_id_table fman1_liodn_tbl[] = {
SET_FMAN_RX_1G_LIODN(1, 0, 88),
SET_FMAN_RX_1G_LIODN(1, 1, 89),
SET_FMAN_RX_1G_LIODN(1, 2, 90),
SET_FMAN_RX_1G_LIODN(1, 3, 91),
SET_FMAN_RX_10G_LIODN(1, 0, 94),
};
int fman1_liodn_tbl_sz = ARRAY_SIZE(fman1_liodn_tbl);
#endif
struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_JR_LIODN_ENTRY(0, 454, 458),
SET_SEC_JR_LIODN_ENTRY(1, 455, 459),
SET_SEC_JR_LIODN_ENTRY(2, 456, 460),
SET_SEC_JR_LIODN_ENTRY(3, 457, 461),
SET_SEC_RTIC_LIODN_ENTRY(a, 453),
SET_SEC_RTIC_LIODN_ENTRY(b, 549),
SET_SEC_RTIC_LIODN_ENTRY(c, 550),
SET_SEC_RTIC_LIODN_ENTRY(d, 551),
SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
struct liodn_id_table liodn_bases[] = {
[FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(462, 558),
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#endif
};

52
arch/powerpc/cpu/mpc85xx/t1024_serdes.c Normal file
View File

@ -0,0 +1,52 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_serdes.h>
#include <asm/processor.h>
#include <asm/io.h>
static u8 serdes_cfg_tbl[][4] = {
[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
[0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC1},
[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC1},
[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
};
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
{
return serdes_cfg_tbl[cfg][lane];
}
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
{
int i;
if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
for (i = 0; i < 4; i++) {
if (serdes_cfg_tbl[prtcl][i] != NONE)
return 1;
}
return 0;
}

30
arch/powerpc/cpu/mpc85xx/t1040_ids.c
View File

@ -24,12 +24,6 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_1(1, 307),
SET_SRIO_LIODN_1(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
SET_QMAN_LIODN(62),
@ -38,12 +32,21 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 552),
SET_PME_LIODN(117),
SET_USB_LIODN(1, "fsl-usb2-mph", 553),
SET_USB_LIODN(2, "fsl-usb2-dr", 554),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 148),
SET_SATA_LIODN(1, 555),
SET_SATA_LIODN(2, 556),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 148),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 228),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
@ -74,6 +77,12 @@ struct liodn_id_table sec_liodn_tbl[] = {
SET_SEC_RTIC_LIODN_ENTRY(d, 551),
SET_SEC_DECO_LIODN_ENTRY(0, 541, 610),
SET_SEC_DECO_LIODN_ENTRY(1, 542, 611),
SET_SEC_DECO_LIODN_ENTRY(2, 543, 612),
SET_SEC_DECO_LIODN_ENTRY(3, 544, 613),
SET_SEC_DECO_LIODN_ENTRY(4, 545, 614),
SET_SEC_DECO_LIODN_ENTRY(5, 546, 615),
SET_SEC_DECO_LIODN_ENTRY(6, 547, 616),
SET_SEC_DECO_LIODN_ENTRY(7, 548, 617),
};
int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl);
@ -82,4 +91,7 @@ struct liodn_id_table liodn_bases[] = {
#ifdef CONFIG_SYS_DPAA_FMAN
[FSL_HW_PORTAL_FMAN1] = SET_LIODN_BASE_1(973),
#endif
#ifdef CONFIG_SYS_DPAA_PME
[FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(770, 846),
#endif
};

6
arch/powerpc/cpu/mpc85xx/t2080_ids.c
View File

@ -63,9 +63,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
SET_DMA_LIODN(3, 226),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
SET_DMA_LIODN(3, "fsl,elo3-dma", 226),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),

1
arch/powerpc/cpu/mpc85xx/t2080_serdes.c
View File

@ -169,6 +169,7 @@ static const struct serdes_config serdes2_cfg_tbl[] = {
{0x01, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2E, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
{0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },

4
arch/powerpc/cpu/mpc85xx/t4240_ids.c
View File

@ -93,8 +93,8 @@ struct liodn_id_table liodn_tbl[] = {
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 308),
SET_PCI_LIODN_BASE(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 388),
SET_DMA_LIODN(1, 147),
SET_DMA_LIODN(2, 227),
SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),

4
arch/powerpc/cpu/mpc8xxx/cpu.c
View File

@ -76,6 +76,10 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T1020, T1020, 0),
CPU_TYPE_ENTRY(T1021, T1021, 0),
CPU_TYPE_ENTRY(T1022, T1022, 0),
CPU_TYPE_ENTRY(T1024, T1024, 0),
CPU_TYPE_ENTRY(T1023, T1023, 0),
CPU_TYPE_ENTRY(T1014, T1014, 0),
CPU_TYPE_ENTRY(T1013, T1013, 0),
CPU_TYPE_ENTRY(T2080, T2080, 0),
CPU_TYPE_ENTRY(T2081, T2081, 0),
CPU_TYPE_ENTRY(BSC9130, 9130, 1),

47
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -769,6 +769,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FSL_ERRATUM_A008044
#define CONFIG_SYS_FMAN_V3
#define CONFIG_FM_PLAT_CLK_DIV 1
#define CONFIG_SYS_FM1_CLK CONFIG_FM_PLAT_CLK_DIV
@ -786,6 +787,52 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) ||\
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
#define CONFIG_SYS_FMAN_V3
#ifdef CONFIG_SYS_FSL_DDR4
#define CONFIG_SYS_FSL_DDRC_GEN4
#endif
#if defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023)
#define CONFIG_MAX_CPUS 2
#elif defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define CONFIG_MAX_CPUS 1
#endif
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_SDHC_CLOCK 0
#define CONFIG_SYS_FSL_NUM_LAWS 16
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SEC_COMPAT 5
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define CONFIG_NUM_DDR_CONTROLLERS 1
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 0
#define CONFIG_QBMAN_CLK_DIV 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x30000
#define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
#define CONFIG_SYS_FSL_TBCLK_DIV 16
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
#define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define CONFIG_E6500
#define CONFIG_SYS_PPC64 /* 64-bit core */

24
arch/powerpc/include/asm/fsl_errata.h
View File

@ -27,3 +27,27 @@ static inline bool has_erratum_a006379(void)
}
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
static inline bool has_erratum_a007186(void)
{
u32 svr = get_svr();
u32 soc = SVR_SOC_VER(svr);
switch (soc) {
case SVR_T4240:
return IS_SVR_REV(svr, 2, 0);
case SVR_T4160:
return IS_SVR_REV(svr, 2, 0);
case SVR_B4860:
return IS_SVR_REV(svr, 2, 0);
case SVR_B4420:
return IS_SVR_REV(svr, 2, 0);
case SVR_T2081:
case SVR_T2080:
return IS_SVR_REV(svr, 1, 0);
}
return false;
}
#endif

4
arch/powerpc/include/asm/fsl_liodn.h
View File

@ -91,8 +91,8 @@ extern void fdt_fixup_liodn(void *blob);
CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
/* reg nodes for DMA start @ 0x300 */
#define SET_DMA_LIODN(dmaNum, liodn) \
SET_GUTS_LIODN("fsl,eloplus-dma", liodn, dma##dmaNum##liodnr,\
#define SET_DMA_LIODN(dmaNum, compat, liodn) \
SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
#define SET_SDHC_LIODN(sdhcNum, liodn) \

4
arch/powerpc/include/asm/fsl_secure_boot.h
View File

@ -22,7 +22,9 @@
defined(CONFIG_T2080QDS) || \
defined(CONFIG_T2080RDB) || \
defined(CONFIG_T1040QDS) || \
defined(CONFIG_T104xRDB)
defined(CONFIG_T104xRDB) || \
defined(CONFIG_PPC_T1023) || \
defined(CONFIG_PPC_T1024)
#define CONFIG_SYS_CPC_REINIT_F
#undef CONFIG_SYS_INIT_L3_ADDR
#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000

22
arch/powerpc/include/asm/immap_85xx.h
View File

@ -1626,10 +1626,15 @@ typedef struct ccsr_gur {
#define FSL_CORENET_DEVDISR2_DTSEC1_6 0x04000000
#define FSL_CORENET_DEVDISR2_DTSEC1_9 0x00800000
#define FSL_CORENET_DEVDISR2_DTSEC1_10 0x00400000
#ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
#define FSL_CORENET_DEVDISR2_10GEC1_1 0x80000000
#define FSL_CORENET_DEVDISR2_10GEC1_2 0x40000000
#else
#define FSL_CORENET_DEVDISR2_10GEC1_1 0x00800000
#define FSL_CORENET_DEVDISR2_10GEC1_2 0x00400000
#define FSL_CORENET_DEVDISR2_10GEC1_3 0x80000000
#define FSL_CORENET_DEVDISR2_10GEC1_4 0x40000000
#endif
#define FSL_CORENET_DEVDISR2_DTSEC2_1 0x00080000
#define FSL_CORENET_DEVDISR2_DTSEC2_2 0x00040000
#define FSL_CORENET_DEVDISR2_DTSEC2_3 0x00020000
@ -1787,6 +1792,21 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T1024) || defined(CONFIG_PPC_T1023) || \
defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
#define FSL_CORENET_RCWSR13_EC1 0x30000000 /* bits 418..419 */
#define FSL_CORENET_RCWSR13_EC1_RGMII 0x00000000
#define FSL_CORENET_RCWSR13_EC1_GPIO 0x10000000
#define FSL_CORENET_RCWSR13_EC2 0x0c000000
#define FSL_CORENET_RCWSR13_EC2_RGMII 0x08000000
#define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET 0x28
#define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET 0xd00
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff000000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 24
@ -2971,6 +2991,8 @@ struct ccsr_sfp_regs {
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
#define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR \
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
#define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \

4
arch/powerpc/include/asm/processor.h
View File

@ -1133,6 +1133,10 @@
#define SVR_T1020 0x852100
#define SVR_T1021 0x852101
#define SVR_T1022 0x852102
#define SVR_T1024 0x854000
#define SVR_T1023 0x854100
#define SVR_T1014 0x854400
#define SVR_T1013 0x854500
#define SVR_T2080 0x853000
#define SVR_T2081 0x853100

95
board/freescale/b4860qds/b4860qds.c
View File

@ -19,6 +19,7 @@
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
@ -333,6 +334,8 @@ int configure_vsc3316_3308(void)
unsigned int num_vsc16_con, num_vsc08_con;
u32 serdes1_prtcl, serdes2_prtcl;
int ret;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@ -385,15 +388,18 @@ int configure_vsc3316_3308(void)
}
break;
case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@ -487,6 +493,9 @@ int configure_vsc3316_3308(void)
return -1;
}
num_vsc08_con = NUM_CON_VSC3308;
/* Configure VSC3308 crossbar switch */
ret = select_i2c_ch_pca(I2C_CH_VSC3308);
switch (serdes2_prtcl) {
#ifdef CONFIG_PPC_B4420
case 0x9d:
@ -494,14 +503,11 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
case 0xb2:
case 0x48:
case 0x49:
case 0x4E:
case 0x8D:
case 0x79:
case 0x7A:
num_vsc08_con = NUM_CON_VSC3308;
/* Configure VSC3308 crossbar switch */
ret = select_i2c_ch_pca(I2C_CH_VSC3308);
if (!ret) {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
@ -515,6 +521,71 @@ int configure_vsc3316_3308(void)
return ret;
}
break;
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
if (!ret) {
/*
* Extract hwconfig from environment since environment
* is not setup properly yet
*/
getenv_f("hwconfig", buffer, sizeof(buffer));
buf = buffer;
if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
"sfp_amc", "sfp", buf)) {
#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
/* change default VSC3308 for XFI erratum */
ret = vsc3308_config_adjust(VSC3308_TX_ADDRESS,
vsc08_tx_sfp, num_vsc08_con);
if (ret)
return ret;
ret = vsc3308_config_adjust(VSC3308_RX_ADDRESS,
vsc08_rx_sfp, num_vsc08_con);
if (ret)
return ret;
#else
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_sfp, num_vsc08_con);
if (ret)
return ret;
ret = vsc3308_config(VSC3308_RX_ADDRESS,
vsc08_rx_sfp, num_vsc08_con);
if (ret)
return ret;
#endif
} else {
ret = vsc3308_config(VSC3308_TX_ADDRESS,
vsc08_tx_amc, num_vsc08_con);
if (ret)
return ret;
ret = vsc3308_config(VSC3308_RX_ADDRESS,
vsc08_rx_amc, num_vsc08_con);
if (ret)
return ret;
}
} else {
return ret;
}
break;
default:
printf("WARNING:VSC crossbars programming not supported for: %x"
" SerDes2 Protocol.\n", serdes2_prtcl);
@ -730,19 +801,23 @@ int config_serdes1_refclks(void)
* to 122.88MHz
*/
switch (serdes1_prtcl) {
case 0x29:
case 0x2A:
case 0x2C:
case 0x2D:
case 0x2E:
case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@ -860,6 +935,8 @@ int config_serdes2_refclks(void)
#endif
case 0x9E:
case 0x9A:
/* fallthrough */
case 0xb1:
case 0xb2:
debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
serdes2_prtcl);
@ -915,6 +992,14 @@ int board_early_init_r(void)
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
u32 svr = SVR_SOC_VER(get_svr());
/* Create law for MAPLE only for personalities having MAPLE */
if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
(svr == SVR_B4420) || (svr == SVR_B4220)) {
set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
LAW_TRGT_IF_MAPLE);
}
/*
* Remap Boot flash + PROMJET region to caching-inhibited

127
board/freescale/b4860qds/eth_b4860qds.c
View File

@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
/*
* Configuration:
* SERDES: 2
@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
debug("Setting phy addresses for FM1_DTSEC5: %x and"
"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
debug("Setting phy addresses for FM1_DTSEC3: %x and"
"FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
debug("Setting phy addresses on SGMII Riser card for"
"FM1_DTSEC ports: \n");
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
debug("Setting phy addresses on SGMII Riser card for"
"FM1_DTSEC ports: \n");
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@ -255,29 +258,37 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
case 0x8d:
case 0xb1:
case 0xb2:
debug("Setting phy addresses on SGMII Riser card for"
"FM1_DTSEC ports: \n");
case 0x8c:
case 0x8d:
debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
/*
* XFI does not need a PHY to work, but to make U-boot
* happy, assign a fake PHY address for a XFI port.
*/
fm_info_set_phy_address(FM1_10GEC1, 0);
fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC1: %x\n",
debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
debug("Setting phy addresses on B4860 QDS AMC2PEX-2S for FM1_10GEC2: %x\n",
debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
@ -329,17 +340,20 @@ int board_eth_init(bd_t *bis)
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
miiphy_get_dev_by_name
(DEFAULT_FM_TGEC_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: 10GSEC%u set to unknown interface %i\n",
printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
cpu_eth_init(bis);
#endif
@ -351,21 +365,82 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{
int phy;
char alias[32];
struct fixed_link f_link;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, alias);
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* check if it's XFI interface for 10g */
switch (prtcl2) {
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
break;
case 0x98: /* XAUI interface */
sprintf(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
sprintf(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x9e: /* XAUI interface */
case 0x9a:
case 0x93:
case 0x91:
sprintf(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x97: /* XAUI interface */
case 0xc3:
sprintf(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
default:
break;
}
}
}
/*
* Set status to disabled for unused ethernet node
*/
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);

3
board/freescale/b4860qds/law.c
View File

@ -17,9 +17,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),

1
board/freescale/common/Makefile
View File

@ -23,6 +23,7 @@ obj-$(CONFIG_FMAN_ENET) += fman.o
obj-$(CONFIG_FSL_PIXIS) += pixis.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_FSL_NGPIXIS) += ngpixis.o
obj-$(CONFIG_VID) += vid.o
endif
obj-$(CONFIG_FSL_QIXIS) += qixis.o
obj-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o

491
board/freescale/common/vid.c Normal file
View File

@ -0,0 +1,491 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/immap_85xx.h>
#include "vid.h"
DECLARE_GLOBAL_DATA_PTR;
int __weak i2c_multiplexer_select_vid_channel(u8 channel)
{
return 0;
}
/*
* Compensate for a board specific voltage drop between regulator and SoC
* return a value in mV
*/
int __weak board_vdd_drop_compensation(void)
{
return 0;
}
/*
* Get the i2c address configuration for the IR regulator chip
*
* There are some variance in the RDB HW regarding the I2C address configuration
* for the IR regulator chip, which is likely a problem of external resistor
* accuracy. So we just check each address in a hopefully non-intrusive mode
* and use the first one that seems to work
*
* The IR chip can show up under the following addresses:
* 0x08 (Verified on T1040RDB-PA,T4240RDB-PB,X-T4240RDB-16GPA)
* 0x09 (Verified on T1040RDB-PA)
* 0x38 (Verified on T2080QDS, T2081QDS)
*/
static int find_ir_chip_on_i2c(void)
{
int i2caddress;
int ret;
u8 byte;
int i;
const int ir_i2c_addr[] = {0x38, 0x08, 0x09};
/* Check all the address */
for (i = 0; i < (sizeof(ir_i2c_addr)/sizeof(ir_i2c_addr[0])); i++) {
i2caddress = ir_i2c_addr[i];
ret = i2c_read(i2caddress,
IR36021_MFR_ID_OFFSET, 1, (void *)&byte,
sizeof(byte));
if ((ret >= 0) && (byte == IR36021_MFR_ID))
return i2caddress;
}
return -1;
}
/* Maximum loop count waiting for new voltage to take effect */
#define MAX_LOOP_WAIT_NEW_VOL 100
/* Maximum loop count waiting for the voltage to be stable */
#define MAX_LOOP_WAIT_VOL_STABLE 100
/*
* read_voltage from sensor on I2C bus
* We use average of 4 readings, waiting for WAIT_FOR_ADC before
* another reading
*/
#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
/* If an INA220 chip is available, we can use it to read back the voltage
* as it may have a higher accuracy than the IR chip for the same purpose
*/
#ifdef CONFIG_VOL_MONITOR_INA220
#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
#define ADC_MIN_ACCURACY 4
#else
#define WAIT_FOR_ADC 138 /* wait for 138 microseconds for ADC */
#define ADC_MIN_ACCURACY 4
#endif
#ifdef CONFIG_VOL_MONITOR_INA220
static int read_voltage_from_INA220(int i2caddress)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf[2];
for (i = 0; i < NUM_READINGS; i++) {
ret = i2c_read(I2C_VOL_MONITOR_ADDR,
I2C_VOL_MONITOR_BUS_V_OFFSET, 1,
(void *)&buf, 2);
if (ret) {
printf("VID: failed to read core voltage\n");
return ret;
}
vol_mon = (buf[0] << 8) | buf[1];
if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
printf("VID: Core voltage sensor error\n");
return -1;
}
debug("VID: bus voltage reads 0x%04x\n", vol_mon);
/* LSB = 4mv */
voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
udelay(WAIT_FOR_ADC);
}
/* calculate the average */
voltage_read /= NUM_READINGS;
return voltage_read;
}
#endif
/* read voltage from IR */
#ifdef CONFIG_VOL_MONITOR_IR36021_READ
static int read_voltage_from_IR(int i2caddress)
{
int i, ret, voltage_read = 0;
u16 vol_mon;
u8 buf;
for (i = 0; i < NUM_READINGS; i++) {
ret = i2c_read(i2caddress,
IR36021_LOOP1_VOUT_OFFSET,
1, (void *)&buf, 1);
if (ret) {
printf("VID: failed to read vcpu\n");
return ret;
}
vol_mon = buf;
if (!vol_mon) {
printf("VID: Core voltage sensor error\n");
return -1;
}
debug("VID: bus voltage reads 0x%02x\n", vol_mon);
/* Resolution is 1/128V. We scale up here to get 1/128mV
* and divide at the end
*/
voltage_read += vol_mon * 1000;
udelay(WAIT_FOR_ADC);
}
/* Scale down to the real mV as IR resolution is 1/128V, rounding up */
voltage_read = DIV_ROUND_UP(voltage_read, 128);
/* calculate the average */
voltage_read /= NUM_READINGS;
/* Compensate for a board specific voltage drop between regulator and
* SoC before converting into an IR VID value
*/
voltage_read -= board_vdd_drop_compensation();
return voltage_read;
}
#endif
static int read_voltage(int i2caddress)
{
int voltage_read;
#ifdef CONFIG_VOL_MONITOR_INA220
voltage_read = read_voltage_from_INA220(i2caddress);
#elif defined CONFIG_VOL_MONITOR_IR36021_READ
voltage_read = read_voltage_from_IR(i2caddress);
#else
return -1;
#endif
return voltage_read;
}
/*
* We need to calculate how long before the voltage stops to drop
* or increase. It returns with the loop count. Each loop takes
* several readings (WAIT_FOR_ADC)
*/
static int wait_for_new_voltage(int vdd, int i2caddress)
{
int timeout, vdd_current;
vdd_current = read_voltage(i2caddress);
/* wait until voltage starts to reach the target. Voltage slew
* rates by typical regulators will always lead to stable readings
* within each fairly long ADC interval in comparison to the
* intended voltage delta change until the target voltage is
* reached. The fairly small voltage delta change to any target
* VID voltage also means that this function will always complete
* within few iterations. If the timeout was ever reached, it would
* point to a serious failure in the regulator system.
*/
for (timeout = 0;
abs(vdd - vdd_current) > (IR_VDD_STEP_UP + IR_VDD_STEP_DOWN) &&
timeout < MAX_LOOP_WAIT_NEW_VOL; timeout++) {
vdd_current = read_voltage(i2caddress);
}
if (timeout >= MAX_LOOP_WAIT_NEW_VOL) {
printf("VID: Voltage adjustment timeout\n");
return -1;
}
return timeout;
}
/*
* this function keeps reading the voltage until it is stable or until the
* timeout expires
*/
static int wait_for_voltage_stable(int i2caddress)
{
int timeout, vdd_current, vdd;
vdd = read_voltage(i2caddress);
udelay(NUM_READINGS * WAIT_FOR_ADC);
/* wait until voltage is stable */
vdd_current = read_voltage(i2caddress);
/* The maximum timeout is
* MAX_LOOP_WAIT_VOL_STABLE * NUM_READINGS * WAIT_FOR_ADC
*/
for (timeout = MAX_LOOP_WAIT_VOL_STABLE;
abs(vdd - vdd_current) > ADC_MIN_ACCURACY &&
timeout > 0; timeout--) {
vdd = vdd_current;
udelay(NUM_READINGS * WAIT_FOR_ADC);
vdd_current = read_voltage(i2caddress);
}
if (timeout == 0)
return -1;
return vdd_current;
}
#ifdef CONFIG_VOL_MONITOR_IR36021_SET
/* Set the voltage to the IR chip */
static int set_voltage_to_IR(int i2caddress, int vdd)
{
int wait, vdd_last;
int ret;
u8 vid;
/* Compensate for a board specific voltage drop between regulator and
* SoC before converting into an IR VID value
*/
vdd += board_vdd_drop_compensation();
vid = DIV_ROUND_UP(vdd - 245, 5);
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
if (ret) {
printf("VID: failed to write VID\n");
return -1;
}
wait = wait_for_new_voltage(vdd, i2caddress);
if (wait < 0)
return -1;
debug("VID: Waited %d us\n", wait * NUM_READINGS * WAIT_FOR_ADC);
vdd_last = wait_for_voltage_stable(i2caddress);
if (vdd_last < 0)
return -1;
debug("VID: Current voltage is %d mV\n", vdd_last);
return vdd_last;
}
#endif
static int set_voltage(int i2caddress, int vdd)
{
int vdd_last = -1;
#ifdef CONFIG_VOL_MONITOR_IR36021_SET
vdd_last = set_voltage_to_IR(i2caddress, vdd);
#else
#error Specific voltage monitor must be defined
#endif
return vdd_last;
}
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 fusesr;
u8 vid;
int vdd_target, vdd_current, vdd_last;
int ret, i2caddress;
unsigned long vdd_string_override;
char *vdd_string;
static const uint16_t vdd[32] = {
0, /* unused */
9875, /* 0.9875V */
9750,
9625,
9500,
9375,
9250,
9125,
9000,
8875,
8750,
8625,
8500,
8375,
8250,
8125,
10000, /* 1.0000V */
10125,
10250,
10375,
10500,
10625,
10750,
10875,
11000,
0, /* reserved */
};
struct vdd_drive {
u8 vid;
unsigned voltage;
};
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
debug("VID: I2C failed to switch channel\n");
ret = -1;
goto exit;
}
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
ret = -1;
goto exit;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
/* get the voltage ID from fuse status register */
fusesr = in_be32(&gur->dcfg_fusesr);
/*
* VID is used according to the table below
* ---------------------------------------
* | DA_V |
* |-------------------------------------|
* | 5b00000 | 5b00001-5b11110 | 5b11111 |
* ---------------+---------+-----------------+---------|
* | D | 5b00000 | NO VID | VID = DA_V | NO VID |
* | A |----------+---------+-----------------+---------|
* | _ | 5b00001 |VID = | VID = |VID = |
* | V | ~ | DA_V_ALT| DA_V_ALT | DA_A_VLT|
* | _ | 5b11110 | | | |
* | A |----------+---------+-----------------+---------|
* | L | 5b11111 | No VID | VID = DA_V | NO VID |
* | T | | | | |
* ------------------------------------------------------
*/
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
}
vdd_target = vdd[vid];
/* check override variable for overriding VDD */
vdd_string = getenv(CONFIG_VID_FLS_ENV);
if (vdd_override == 0 && vdd_string &&
!strict_strtoul(vdd_string, 10, &vdd_string_override))
vdd_override = vdd_string_override;
if (vdd_override >= VDD_MV_MIN && vdd_override <= VDD_MV_MAX) {
vdd_target = vdd_override * 10; /* convert to 1/10 mV */
debug("VDD override is %lu\n", vdd_override);
} else if (vdd_override != 0) {
printf("Invalid value.\n");
}
if (vdd_target == 0) {
debug("VID: VID not used\n");
ret = 0;
goto exit;
} else {
/* divide and round up by 10 to get a value in mV */
vdd_target = DIV_ROUND_UP(vdd_target, 10);
debug("VID: vid = %d mV\n", vdd_target);
}
/*
* Read voltage monitor to check real voltage.
*/
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
ret = -1;
goto exit;
}
vdd_current = vdd_last;
debug("VID: Core voltage is currently at %d mV\n", vdd_last);
/*
* Adjust voltage to at or one step above target.
* As measurements are less precise than setting the values
* we may run through dummy steps that cancel each other
* when stepping up and then down.
*/
while (vdd_last > 0 &&
vdd_last < vdd_target) {
vdd_current += IR_VDD_STEP_UP;
vdd_last = set_voltage(i2caddress, vdd_current);
}
while (vdd_last > 0 &&
vdd_last > vdd_target + (IR_VDD_STEP_DOWN - 1)) {
vdd_current -= IR_VDD_STEP_DOWN;
vdd_last = set_voltage(i2caddress, vdd_current);
}
if (vdd_last > 0)
printf("VID: Core voltage after adjustment is at %d mV\n",
vdd_last);
else
ret = -1;
exit:
if (re_enable)
enable_interrupts();
return ret;
}
static int print_vdd(void)
{
int vdd_last, ret, i2caddress;
ret = i2c_multiplexer_select_vid_channel(I2C_MUX_CH_VOL_MONITOR);
if (ret) {
debug("VID : I2c failed to switch channel\n");
return -1;
}
ret = find_ir_chip_on_i2c();
if (ret < 0) {
printf("VID: Could not find voltage regulator on I2C.\n");
return -1;
} else {
i2caddress = ret;
debug("VID: IR Chip found on I2C address 0x%02x\n", i2caddress);
}
/*
* Read voltage monitor to check real voltage.
*/
vdd_last = read_voltage(i2caddress);
if (vdd_last < 0) {
printf("VID: Couldn't read sensor abort VID adjustment\n");
return -1;
}
printf("VID: Core voltage is at %d mV\n", vdd_last);
return 0;
}
static int do_vdd_override(cmd_tbl_t *cmdtp,
int flag, int argc,
char * const argv[])
{
ulong override;
if (argc < 2)
return CMD_RET_USAGE;
if (!strict_strtoul(argv[1], 10, &override))
adjust_vdd(override); /* the value is checked by callee */
else
return CMD_RET_USAGE;
return 0;
}
static int do_vdd_read(cmd_tbl_t *cmdtp,
int flag, int argc,
char * const argv[])
{
if (argc < 1)
return CMD_RET_USAGE;
print_vdd();
return 0;
}
U_BOOT_CMD(
vdd_override, 2, 0, do_vdd_override,
"override VDD",
" - override with the voltage specified in mV, eg. 1050"
);
U_BOOT_CMD(
vdd_read, 1, 0, do_vdd_read,
"read VDD",
" - Read the voltage specified in mV"
)

20
board/freescale/common/vid.h Normal file
View File

@ -0,0 +1,20 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __VID_H_
#define __VID_H_
#define IR36021_LOOP1_MANUAL_ID_OFFSET 0x6A
#define IR36021_LOOP1_VOUT_OFFSET 0x9A
#define IR36021_MFR_ID_OFFSET 0x92
#define IR36021_MFR_ID 0x43
/* step the IR regulator in 5mV increments */
#define IR_VDD_STEP_DOWN 5
#define IR_VDD_STEP_UP 5
int adjust_vdd(ulong vdd_override);
#endif /* __VID_H_ */

108
board/freescale/common/vsc3316_3308.c
View File

@ -13,7 +13,12 @@
#define INPUT_STATE_REG 0x13
#define GLOBAL_INPUT_ISE1 0x51
#define GLOBAL_INPUT_ISE2 0x52
#define GLOBAL_INPUT_GAIN 0x53
#define GLOBAL_INPUT_LOS 0x55
#define GLOBAL_OUTPUT_PE1 0x56
#define GLOBAL_OUTPUT_PE2 0x57
#define GLOBAL_OUTPUT_LEVEL 0x58
#define GLOBAL_OUTPUT_TERMINATION 0x5A
#define GLOBAL_CORE_CNTRL 0x5D
#define OUTPUT_MODE_PAGE 0x23
#define CORE_CONTROL_PAGE 0x25
@ -92,6 +97,109 @@ int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
return 0;
}
#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con)
{
unsigned int i;
u8 rev_id = 0;
int ret;
debug("VSC:Initializing VSC3308 at I2C address 0x%x for Tx\n",
vsc_addr);
ret = i2c_read(vsc_addr, REVISION_ID_REG, 1, &rev_id, 1);
if (ret < 0) {
printf("VSC:0x%x could not read REV_ID from device.\n",
vsc_addr);
return ret;
}
if (rev_id != 0xab) {
printf("VSC: device at address 0x%x is not VSC3316/3308.\n",
vsc_addr);
return -ENODEV;
}
ret = vsc_if_enable(vsc_addr);
if (ret) {
printf("VSC:0x%x could not configured for 2-wire I/F.\n",
vsc_addr);
return ret;
}
/* config connections - page 0x00 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, CONNECTION_CONFIG_PAGE);
/* Configure Global Input ISE */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE1, 0);
i2c_reg_write(vsc_addr, GLOBAL_INPUT_ISE2, 0);
/* Configure Tx/Rx Global Output PE1 */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE1, 0);
/* Configure Tx/Rx Global Output PE2 */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_PE2, 0);
/* Configure Tx/Rx Global Input GAIN */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_GAIN, 0x3F);
/* Setting Global Input LOS threshold value */
i2c_reg_write(vsc_addr, GLOBAL_INPUT_LOS, 0xE0);
/* Setting Global output termination */
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_TERMINATION, 0);
/* Configure Tx/Rx Global Output level */
if (vsc_addr == VSC3308_TX_ADDRESS)
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 4);
else
i2c_reg_write(vsc_addr, GLOBAL_OUTPUT_LEVEL, 2);
/* Making crosspoint connections, by connecting required
* input to output */
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], con_arr[i][0]);
/* input state - page 0x13 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, INPUT_STATE_REG);
/* Turning off all the required input of the switch */
for (i = 0; i < num_con; i++)
i2c_reg_write(vsc_addr, con_arr[i][0], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
i2c_reg_write(vsc_addr, 2, 0);
i2c_reg_write(vsc_addr, 3, 0);
} else {
i2c_reg_write(vsc_addr, 0, 0);
i2c_reg_write(vsc_addr, 1, 0);
}
/* config output mode - page 0x23 */
i2c_reg_write(vsc_addr, CURRENT_PAGE_REGISTER, OUTPUT_MODE_PAGE);
/* Turn off the Output driver correspond to required output*/
for (i = 0; i < num_con ; i++)
i2c_reg_write(vsc_addr, con_arr[i][1], 1);
/* only turn on specific Tx/Rx requested by the XFI erratum */
if (vsc_addr == VSC3308_TX_ADDRESS) {
i2c_reg_write(vsc_addr, 0, 0);
i2c_reg_write(vsc_addr, 1, 0);
} else {
i2c_reg_write(vsc_addr, 3, 0);
i2c_reg_write(vsc_addr, 4, 0);
}
/* configure global core control register, Turn on Global core power */
i2c_reg_write(vsc_addr, GLOBAL_CORE_CNTRL, 0);
vsc_wp_config(vsc_addr);
return 0;
}
#endif
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con)
{

4
board/freescale/common/vsc3316_3308.h
View File

@ -14,6 +14,10 @@
int vsc_if_enable(unsigned int vsc_addr);
int vsc3316_config(unsigned int vsc_addr, int8_t con_arr[][2],
unsigned int num_con);
#ifdef CONFIG_SYS_FSL_B4860QDS_XFI_ERR
int vsc3308_config_adjust(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
#endif
int vsc3308_config(unsigned int vsc_addr, const int8_t con_arr[][2],
unsigned int num_con);
void vsc_wp_config(unsigned int vsc_addr);

7
board/freescale/corenet_ds/eth_hydra.c
View File

@ -62,7 +62,7 @@
#ifdef CONFIG_FMAN_ENET
#define BRDCFG1_EMI1_SEL_MASK 0x70
#define BRDCFG1_EMI1_SEL_MASK 0x78
#define BRDCFG1_EMI1_SEL_SLOT1 0x10
#define BRDCFG1_EMI1_SEL_SLOT2 0x20
#define BRDCFG1_EMI1_SEL_SLOT5 0x30
@ -202,6 +202,8 @@ static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
if (!path)
path = alias;
do_fixup_by_path(fdt, path, "reg",
&mux, sizeof(mux), 1);
do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
&mux, sizeof(mux), 1);
}
@ -250,11 +252,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
return;
}
if (mux == BRDCFG1_EMI1_SEL_RGMII) {
if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
/* RGMII */
/* The RGMII PHY is identified by the MAC connected to it */
sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
fdt_set_phy_handle(fdt, compat, addr, phy);
return;
}
/* If it's not RGMII or XGMII, it must be SGMII */

12
board/freescale/t102xqds/Kconfig Normal file
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@ -0,0 +1,12 @@
if TARGET_T102XQDS
config SYS_BOARD
default "t102xqds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "T102xQDS"
endif

12
board/freescale/t102xqds/MAINTAINERS Normal file
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@ -0,0 +1,12 @@
T102XQDS BOARD
M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Maintained
F: board/freescale/t102xqds/
F: include/configs/T102xQDS.h
F: configs/T1024QDS_defconfig
F: configs/T1024QDS_NAND_defconfig
F: configs/T1024QDS_SDCARD_defconfig
F: configs/T1024QDS_SPIFLASH_defconfig
F: configs/T1024QDS_D4_defconfig
F: configs/T1024QDS_SECURE_BOOT_defconfig
F: configs/T1024QDS_D4_SECURE_BOOT_defconfig

17
board/freescale/t102xqds/Makefile Normal file
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@ -0,0 +1,17 @@
#
# Copyright 2014 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += t102xqds.o
obj-y += eth_t102xqds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_FSL_DIU_FB) += ../t1040qds/diu.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

328
board/freescale/t102xqds/README Normal file
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@ -0,0 +1,328 @@
T1024 SoC Overview
------------------
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
combines two or one 64-bit Power Architecture e5500 core respectively with high
performance datapath acceleration logic, and network peripheral bus interfaces
required for networking and telecommunications. This processor can be used in
applications such as enterprise WLAN access points, routers, switches, firewall
and other packet processing intensive small enterprise and branch office appliances,
and general-purpose embedded computing. Its high level of integration offers
significant performance benefits and greatly helps to simplify board design.
The T1024 SoC includes the following function and features:
- two e5500 cores, each with a private 256 KB L2 cache
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- Three levels of instructions: User, supervisor, and hypervisor
- Independent boot and reset
- Secure boot capability
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- CoreNet coherency manager supporting coherent and noncoherent transactions
with prioritization and bandwidth allocation amongst CoreNet endpoints
- 150 Gbps coherent read bandwidth
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Cryptography Acceleration (SEC 5.x)
- IEEE 1588 support
- Hardware buffer management for buffer allocation and deallocation
- MACSEC on DPAA-based Ethernet ports
- Ethernet interfaces
- Four 1 Gbps Ethernet controllers
- Parallel Ethernet interfaces
- Two RGMII interfaces
- High speed peripheral interfaces
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- One SATA controller supporting 1.5 and 3.0 Gb/s operation
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- 10GbE XFI or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD interface (DIU) with 12 bit dual data rate
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
T1023 Personality
------------------
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
unavailable deep sleep. Rest of the blocks are almost same as T1024.
Differences between T1024 and T1023
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
T1024QDS board Overview
-----------------------
- SERDES Connections
4 lanes supporting the following:
- PCI Express: supports Gen 1 and Gen 2
- SGMII 1G and SGMII 2.5G
- QSGMII
- XFI
- SATA 2.0
- High-speed multiplexers route the SerDes traffic to appropriate slots or connectors.
- Aurora debug with dedicated connectors.
- DDR Controller
- Supports up to 1600 MTPS data-rate.
- Supports one DDR4 or DDR3L module using DDR4 to DDR3L adapter card.
- Supports Single-, dual- or quad-rank DIMMs
- DDR power supplies 1.35V (DDR3L)/1.20V (DDR4) to all devices with automatic tracking of VTT.
- IFC/Local Bus
- NAND Flash: 8-bit, async, up to 2GB
- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
- NOR devices support 8 virtual banks
- Socketed to allow alternate devices
- GASIC: Simple (minimal) target within QIXIS FPGA
- PromJET rapid memory download support
- IFC Debug/Development card
- Ethernet
- Two on-board RGMII 10M/100M/1G ethernet ports.
- One QSGMII interface
- Four SGMII interface supporting 1Gbps
- Three SGMII interfaces supporting 2.5Gbps
- one 10Gbps XFI or 10Base-KR interface
- QIXIS System Logic FPGA
- Manages system power and reset sequencing.
- Manages the configurations of DUT, board, and clock for dynamic shmoo.
- Collects V-I-T data in background for code/power profiling.
- Supports legacy TMT test features (POSt, IRS, SYSCLK-synchronous assertion).
- General fault monitoring and logging.
- Powered from ATX 'standby' power supply that allows continuous operation while rest of the system is off.
- Clocks
- System and DDR clock (SYSCLK, DDRCLK).
- Switch selectable to one of 16 common settings in the interval of 64 MHz-166 MHz.
- Software programmable in 1 MHz increments from 1-200 MHz.
- SERDES clocks
- Provides clocks to SerDes blocks and slots.
- 100 MHz, 125 MHz and 156.25 MHz options.
- Spread-spectrum option for 100 MHz.
- Power Supplies
- Dedicated PMBus regulator for VDD and VDDC.
- Adjustable from 0.7V to 1.3V at 35A
- VDD can be disabled independanty from VDDC for “deep sleep”.
- DDR3L/DDR4 power supply for GVDD: 1.35 or 1.20V at up to 22A.
- VTT/MVREF automatically track operating voltage.
- Dedicated 2.5V VPP supply.
- Dedicated regulators/filters for AVDD supplies.
- Dedicated regulators for other supplies, for example OVDD, CVDD, DVDD, LVDD, POVDD, and EVDD.
- Video
- DIU supports video up to 1280x1024x32 bpp.
- Chrontel CH7201 for HDMI connection.
- TI DS90C387R for direct LCD connection.
- Raw (not encoded) video connector for testing or other encoders.
- USB
- Supports two USB 2.0 ports with integrated PHYs.
- Two type A ports with 5V@1.5A per port.
- Second port can be converted to OTG mini-AB.
- SDHC
For T1024QDS, the SDHC port connects directly to an adapter card slot that has the following features:
- upport for optional clock feedback paths.
- Support for optional high-speed voltage translation direction controls.
- Support for SD slots for: SD, SDHC (1x, 4x, 8x) and MMC.
- Support for eMMC memory devices.
- SPI
-On-board support of 3 different devices and sizes.
- Other IO
- Two Serial ports
- ProfiBus port
- Four I2C ports
Memory map on T1024QDS
----------------------
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
128MB NOR Flash memory Map
--------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
SerDes clock vs DIP-switch settings
-----------------------------------
SRDS_PRTCL_S1 SD1_REF_CLK1 SD1_REF_CLK2 SW4[1:4]
0x6F 100MHz 125MHz 1101
0xD6 100MHz 100MHz 1111
0x99 156.25MHz 100MHz 1011
T1024 Clock frequency
----------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
Bin3: 1000MHz 1600MT/s 400MHz 500MHz
Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T1024QDS_defconfig (For DDR3L, by default)
or make T1024QDS_D4_defconfig (For DDR4)
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
via software: run command 'qixis_reset altbank' in u-boot.
via DIP-switch: set SW6[1:4] = '0100'
To change boot source to vbank0:
via software: run command 'qixis_reset' in u-boot.
via DIP-Switch: set SW6[1:4] = '0000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T1024QDS_NAND_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T1024QDS_SPIFLASH_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 f0000
=> sf write 1000000 0 $filesize
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
a. build PBL image for SD boot
$ make T1024QDS_SDCARD_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x800
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
DIU/QE-TDM/SDXC settings
-------------------
a) For TDM Riser: set pin_mux=tdm in hwconfig
b) For UCC(ProfiBus): set pin_mux=ucc in hwconfig
c) For HDMI(DVI): set pin_mux=hdmi in hwconfig
d) For LCD(DFP): set pin_mux=lcd in hwconfig
e) For SDXC: set adaptor=sdxc in hwconfig
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (30KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T1024QDS
-------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB
0x100000 0x15FFFF u-boot env 8KB
0x160000 0x17FFFF FMAN Ucode 128KB
0x180000 0x19FFFF QE Firmware 128KB
SD Card memory Map on T1024QDS
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0256 FMAN Ucode 128KB
0x920 0256 QE Firmware 128KB
SPI Flash memory Map on T1024QDS
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
0x130000 0x14FFFF QE Firmware 128KB
For more details, please refer to T1024QDS Reference Manual and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.

170
board/freescale/t102xqds/ddr.c Normal file
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@ -0,0 +1,170 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* datarate_mhz_high values need to be in ascending order
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
#if defined(CONFIG_SYS_FSL_DDR4)
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E09,},
{1, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 2200, 0, 4, 7, 0x08090A0D, 0x0F0F100C,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
#else
#error DDR type not defined
#endif
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
struct cpu_type *cpu = gd->arch.cpu;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust according to the board ddr freqency and n_banks
* specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found\n");
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* rtt and rtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
#ifdef CONFIG_SYS_FSL_DDR4
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
#else
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
* set DDR bus width to 32bit for T1023
*/
if (cpu->soc_ver == SVR_T1023)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}

442
board/freescale/t102xqds/eth_t102xqds.c Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t102xqds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT4 5
#define EMI1_SLOT5 6
#define EMI2 7
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
"T1024QDS_MDIO_RGMII1",
"T1024QDS_MDIO_RGMII2",
"T1024QDS_MDIO_SLOT1",
"T1024QDS_MDIO_SLOT2",
"T1024QDS_MDIO_SLOT3",
"T1024QDS_MDIO_SLOT4",
"T1024QDS_MDIO_SLOT5",
"T1024QDS_MDIO_10GC",
"NULL",
};
/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
static u8 lane_to_slot[] = {2, 3, 4, 5};
static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name;
if (muxval > EMI2)
return NULL;
name = t1024qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
struct t1024qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static void t1024qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if (muxval < 7) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct t1024qds_mdio *priv = bus->priv;
t1024qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct t1024qds_mdio *priv = bus->priv;
t1024qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int t1024qds_mdio_reset(struct mii_dev *bus)
{
struct t1024qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int t1024qds_mdio_init(char *realbusname, u8 muxval)
{
struct t1024qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate t1024qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate t1024qds private data\n");
free(bus);
return -1;
}
bus->read = t1024qds_mdio_read;
bus->write = t1024qds_mdio_write;
bus->reset = t1024qds_mdio_reset;
sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
struct fixed_link f_link;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
fdt_setprop(fdt, offset, "phy-connection-type",
"rgmii", 5);
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
if (port == FM1_DTSEC1) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_vsc8234_phy_s5");
} else if (port == FM1_DTSEC2) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_vsc8234_phy_s4");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
if (port == FM1_DTSEC3) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_aqr105_phy_s3");
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (port) {
case FM1_DTSEC1:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
break;
case FM1_DTSEC2:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
break;
case FM1_DTSEC3:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
break;
case FM1_DTSEC4:
fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
break;
default:
break;
}
fdt_delprop(fdt, offset, "phy-connection-type");
fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
fdt_status_okay_by_alias(fdt, "emi1_slot2");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* XFI interface */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
}
}
void fdt_fixup_board_enet(void *fdt)
{
}
/*
* This function reads RCW to check if Serdes1{A:D} is configured
* to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
*/
static void initialize_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_s1) {
case 0x46:
case 0x47:
lane_to_slot[1] = 2;
break;
default:
break;
}
}
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
initialize_lane_to_slot();
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0xd5:
case 0xd6:
/* QSGMII in Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, 0x8);
fm_info_set_phy_address(FM1_DTSEC2, 0x9);
fm_info_set_phy_address(FM1_DTSEC3, 0xa);
fm_info_set_phy_address(FM1_DTSEC4, 0xb);
break;
case 0x95:
case 0x99:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
* a MAC has no PHY address, we give a PHY address to XFI
* MAC, and should not use a real XAUI PHY address, since
* MDIO can access it successfully, and then MDIO thinks the
* XAUI card is used for the XFI MAC, which will cause error.
*/
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6f:
/* SGMII in Slot3, Slot4, Slot5 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x7f:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x47:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x77:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
break;
case 0x5a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6a:
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x5b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x6b:
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
break;
default:
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
}
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 5:
mdio_mux[i] = EMI1_SLOT5;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII2;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII1;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
lane = serdes_get_first_lane(FSL_SRDS_1,
XFI_FM1_MAC1 + idx);
if (lane < 0)
break;
mdio_mux[i] = EMI2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

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board/freescale/t102xqds/law.c Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifndef CONFIG_SYS_NO_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef QIXIS_BASE_PHYS
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

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board/freescale/t102xqds/pci.c Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

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/* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
#include "../common/qixis.h"
#include "t102xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_PPC_T1040) && defined(CONFIG_SPL_NAND_BOOT)
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
u32 porsr1, pinctl;
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

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board/freescale/t102xqds/t1024_pbi.cfg Normal file
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#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
09000cd4 fffc0000
09000cd8 81000011
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
091380c0 000FFFFF

10
board/freescale/t102xqds/t1024_rcw.cfg Normal file
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# single-source clock:Sys_Clock = DDR_Refclock = Diff_Sysclk = 100 MHz
# Core/DDR/Platform/FMan = 1400MHz/1600MT/s/400MHz/700MHz
# PBL preamble and RCW header for T1024QDS
aa55aa55 010e0100
# Serdes protocol 0x6F
0810000e 00000000 00000000 00000000
37800001 00000012 e8104000 21000000
00000000 00000000 00000000 00030810
00000000 036c5a00 00000000 00000006

408
board/freescale/t102xqds/t102xqds.c Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/cache.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include <hwconfig.h>
#include <asm/mpc85xx_gpio.h>
#include "../common/qixis.h"
#include "t102xqds.h"
#include "t102xqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
char buf[64];
struct cpu_type *cpu = gd->arch.cpu;
static const char *const freq[] = {"100", "125", "156.25", "100.0"};
int clock;
u8 sw = QIXIS_READ(arch);
printf("Board: %sQDS, ", cpu->name);
printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFC Card\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
printf("FPGA: v%d (%s), build %d",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
/* the timestamp string contains "\n" at the end */
printf(" on %s", qixis_read_time(buf));
puts("SERDES Reference: ");
sw = QIXIS_READ(brdcfg[2]);
clock = (sw >> 6) & 3;
printf("Clock1=%sMHz ", freq[clock]);
clock = (sw >> 4) & 3;
printf("Clock2=%sMHz\n", freq[clock]);
return 0;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
static int board_mux_lane_to_slot(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_prtcl_s1;
u8 brdcfg9;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
brdcfg9 = QIXIS_READ(brdcfg[9]);
QIXIS_WRITE(brdcfg[9], brdcfg9 | BRDCFG9_XFI_TX_DISABLE);
switch (srds_prtcl_s1) {
case 0:
/* SerDes1 is not enabled */
break;
case 0xd5:
case 0x5b:
case 0x6b:
case 0x77:
case 0x6f:
case 0x7f:
QIXIS_WRITE(brdcfg[12], 0x8c);
break;
case 0x40:
QIXIS_WRITE(brdcfg[12], 0xfc);
break;
case 0xd6:
case 0x5a:
case 0x6a:
case 0x56:
QIXIS_WRITE(brdcfg[12], 0x88);
break;
case 0x47:
QIXIS_WRITE(brdcfg[12], 0xcc);
break;
case 0x46:
QIXIS_WRITE(brdcfg[12], 0xc8);
break;
case 0x95:
case 0x99:
brdcfg9 &= ~BRDCFG9_XFI_TX_DISABLE;
QIXIS_WRITE(brdcfg[9], brdcfg9);
QIXIS_WRITE(brdcfg[12], 0x8c);
break;
case 0x116:
QIXIS_WRITE(brdcfg[12], 0x00);
break;
case 0x115:
case 0x119:
case 0x129:
case 0x12b:
/* Aurora, PCIe, SGMII, SATA */
QIXIS_WRITE(brdcfg[12], 0x04);
break;
default:
printf("WARNING: unsupported for SerDes Protocol %d\n",
srds_prtcl_s1);
return -1;
}
return 0;
}
#ifdef CONFIG_PPC_T1024
static void board_mux_setup(void)
{
u8 brdcfg15;
brdcfg15 = QIXIS_READ(brdcfg[15]);
brdcfg15 &= ~BRDCFG15_DIUSEL_MASK;
if (hwconfig_arg_cmp("pin_mux", "tdm")) {
/* Route QE_TDM multiplexed signals to TDM Riser slot */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_TDM);
QIXIS_WRITE(brdcfg[13], BRDCFG13_TDM_INTERFACE << 2);
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_TDM);
} else if (hwconfig_arg_cmp("pin_mux", "ucc")) {
/* to UCC (ProfiBus) interface */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_UCC);
} else if (hwconfig_arg_cmp("pin_mux", "hdmi")) {
/* to DVI (HDMI) encoder */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_DIUSEL_HDMI);
} else if (hwconfig_arg_cmp("pin_mux", "lcd")) {
/* to DFP (LCD) encoder */
QIXIS_WRITE(brdcfg[15], brdcfg15 | BRDCFG15_LCDFM |
BRDCFG15_LCDPD | BRDCFG15_DIUSEL_LCD);
}
if (hwconfig_arg_cmp("adaptor", "sdxc"))
/* Route SPI_CS multiplexed signals to SD slot */
QIXIS_WRITE(brdcfg[5], (QIXIS_READ(brdcfg[5]) &
~BRDCFG5_SPIRTE_MASK) | BRDCFG5_SPIRTE_SDHC);
}
#endif
void board_retimer_ds125df111_init(void)
{
u8 reg;
/* Retimer DS125DF111 is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
reg |= 0x24;
i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
reg &= 0x8f;
i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
/* Select active PFD MUX input as re-timed data (001) */
i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
reg = 0xb2;
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash + PROMJET region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_mux_lane_to_slot();
board_retimer_ds125df111_init();
/* Increase IO drive strength to address FCS error on RGMII */
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR, 0xbfdb7800);
return 0;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0F) {
case QIXIS_SYSCLK_64:
return 64000000;
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
#define NUM_SRDS_PLL 2
int misc_init_r(void)
{
#ifdef CONFIG_PPC_T1024
board_mux_setup();
#endif
return 0;
}
void fdt_fixup_spi_mux(void *blob)
{
int nodeoff = 0;
if (hwconfig_arg_cmp("pin_mux", "tdm")) {
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"eon,en25s64")) >= 0) {
fdt_del_node(blob, nodeoff);
}
} else {
/* remove tdm node */
while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
"maxim,ds26522")) >= 0) {
fdt_del_node(blob, nodeoff);
}
}
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_spi_mux(blob);
return 0;
}
void qixis_dump_switch(void)
{
int i, nr_of_cfgsw;
QIXIS_WRITE(cms[0], 0x00);
nr_of_cfgsw = QIXIS_READ(cms[1]);
puts("DIP switch settings dump:\n");
for (i = 1; i <= nr_of_cfgsw; i++) {
QIXIS_WRITE(cms[0], i);
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
}
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
QIXIS_WRITE(pwr_ctl[1], (QIXIS_READ(pwr_ctl[1]) & ~0x2));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif

14
board/freescale/t102xqds/t102xqds.h Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __T102x_QDS_H__
#define __T102x_QDS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
int select_i2c_ch_pca9547(u8 ch);
#endif

64
board/freescale/t102xqds/t102xqds_qixis.h Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __T1024QDS_QIXIS_H__
#define __T1024QDS_QIXIS_H__
/* Definitions of QIXIS Registers for T1024/T1023 QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
#define BRDCFG5_IMX_MASK 0xC0
#define BRDCFG5_IMX_DIU 0x80
#define BRDCFG5_SPIRTE_MASK 0x07
#define BRDCFG5_SPIRTE_TDM 0x01
#define BRDCFG5_SPIRTE_SDHC 0x02
#define BRDCFG9_XFI_TX_DISABLE 0x10
/* BRDCFG13[0:5] TDM configuration and setup */
#define BRDCFG13_TDM_MASK 0xfc
#define BRDCFG13_TDM_INTERFACE 0x37
#define BRDCFG13_HDLC_LOOPBACK 0x29
#define BRDCFG13_TDM_LOOPBACK 0x31
/* BRDCFG15[3] controls LCD Panel Powerdown */
#define BRDCFG15_LCDFM 0x20
#define BRDCFG15_LCDPD 0x10
#define BRDCFG15_LCDPD_MASK 0x10
#define BRDCFG15_LCDPD_ENABLED 0x00
/* BRDCFG15[6:7] controls DIU MUX selction*/
#define BRDCFG15_DIUSEL_MASK 0x03
#define BRDCFG15_DIUSEL_HDMI 0x00
#define BRDCFG15_DIUSEL_LCD 0x01
#define BRDCFG15_DIUSEL_UCC 0x02
#define BRDCFG15_DIUSEL_TDM 0x03
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
#define QIXIS_SYSCLK_150 0x5
#define QIXIS_SYSCLK_160 0x6
#define QIXIS_SYSCLK_166 0x7
#define QIXIS_SYSCLK_64 0x8
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
#endif

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board/freescale/t102xqds/tlb.c Normal file
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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef QIXIS_BASE
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_4K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so if needed more, will use entry 16 later.
*/
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

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board/freescale/t102xrdb/Kconfig Normal file
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if TARGET_T102XRDB
config SYS_BOARD
default "t102xrdb"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "T102xRDB"
endif

10
board/freescale/t102xrdb/MAINTAINERS Normal file
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T102XRDB BOARD
M: Shengzhou Liu <Shengzhou.Liu@freescale.com>
S: Maintained
F: board/freescale/t102xrdb/
F: include/configs/T102xRDB.h
F: configs/T1024RDB_defconfig
F: configs/T1024RDB_NAND_defconfig
F: configs/T1024RDB_SDCARD_defconfig
F: configs/T1024RDB_SPIFLASH_defconfig
F: configs/T1024RDB_SECURE_BOOT_defconfig

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#
# Copyright 2014 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += t102xrdb.o
obj-y += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

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T1024 SoC Overview
------------------
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
combines two or one 64-bit Power Architecture e5500 core respectively with high
performance datapath acceleration logic, and network peripheral bus interfaces
required for networking and telecommunications. This processor can be used in
applications such as enterprise WLAN access points, routers, switches, firewall
and other packet processing intensive small enterprise and branch office appliances,
and general-purpose embedded computing. Its high level of integration offers
significant performance benefits and greatly helps to simplify board design.
The T1024 SoC includes the following function and features:
- two e5500 cores, each with a private 256 KB L2 cache
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- Three levels of instructions: User, supervisor, and hypervisor
- Independent boot and reset
- Secure boot capability
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- CoreNet coherency manager supporting coherent and noncoherent transactions
with prioritization and bandwidth allocation amongst CoreNet endpoints
- 150 Gbps coherent read bandwidth
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Cryptography Acceleration (SEC 5.x)
- IEEE 1588 support
- Hardware buffer management for buffer allocation and deallocation
- MACSEC on DPAA-based Ethernet ports
- Ethernet interfaces
- Four 1 Gbps Ethernet controllers
- Parallel Ethernet interfaces
- Two RGMII interfaces
- High speed peripheral interfaces
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- One SATA controller supporting 1.5 and 3.0 Gb/s operation
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- 10GbE XFI or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD interface (DIU) with 12 bit dual data rate
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
T1023 Personality
------------------
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
unavailable deep sleep. Rest of the blocks are almost same as T1024.
Differences between T1024 and T1023
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
T1024RDB board Overview
-----------------------
- Ethernet
- Two on-board 10M/100M/1G bps RGMII ethernet ports
- One on-board 10G bps Base-T port.
- DDR Memory
- Supports 64-bit 4GB DDR3L DIMM
- PCIe
- One on-board PCIe slot.
- Two on-board PCIe Mini-PCIe connectors.
- IFC/Local Bus
- NOR: 128MB 16-bit NOR Flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- one SD connector supporting 1.8V/3.3V via J53.
- SPI
- On-board 64MB SPI flash
- Other
- Two Serial ports
- Four I2C ports
Memory map on T1024RDB
----------------------
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
128MB NOR Flash memory Map
--------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
T1024 Clock frequency
---------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
Bin3: 1000MHz 1600MT/s 400MHz 500MHz
Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T1024RDB_defconfig
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
via software: run command 'cpld reset altbank' in u-boot.
via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
via software: run command 'cpld reset' in u-boot.
via DIP-Switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T1024RDB_NAND_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10001000', SW2[1] = '1', SW3[4] = '1' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T1024RDB_SPIFLASH_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 f0000
=> sf write 1000000 0 $filesize
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
a. build PBL image for SD boot
$ make T1024RDB_SDCARD_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x800
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (30KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T1024RDB
-------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot 1MB(2 block)
0x100000 0x17FFFF u-boot env 512KB(1 block)
0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
0x200000 0x27FFFF QE Firmware 512KB(1 block)
SD Card memory Map on T1024RDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0256 FMAN Ucode 128KB
0x920 0256 QE Firmware 128KB
SPI Flash memory Map on T1024RDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
0x130000 0x14FFFF QE Firmware 128KB
For more details, please refer to T1024RDB Reference Manual and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.

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/**
* Copyright 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
* Freescale T1024RDB board-specific CPLD controlling supports.
*
* The following macros need to be defined:
*/
#include <common.h>
#include <command.h>
#include <asm/io.h>
#include "cpld.h"
u8 cpld_read(unsigned int reg)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
return in_8(p + reg);
}
void cpld_write(unsigned int reg, u8 value)
{
void *p = (void *)CONFIG_SYS_CPLD_BASE;
out_8(p + reg, value);
}
/**
* Set the boot bank to the alternate bank
*/
void cpld_set_altbank(void)
{
u8 reg = CPLD_READ(flash_csr);
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
CPLD_WRITE(flash_csr, reg);
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
/**
* Set the boot bank to the default bank
*/
void cpld_set_defbank(void)
{
u8 reg = CPLD_READ(flash_csr);
reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
CPLD_WRITE(flash_csr, reg);
CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
}
static void cpld_dump_regs(void)
{
printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
printf("int_status = 0x%02x\n", CPLD_READ(int_status));
printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
putc('\n');
}
int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int rc = 0;
if (argc <= 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "reset") == 0) {
if (strcmp(argv[2], "altbank") == 0)
cpld_set_altbank();
else
cpld_set_defbank();
} else if (strcmp(argv[1], "dump") == 0) {
cpld_dump_regs();
} else {
rc = cmd_usage(cmdtp);
}
return rc;
}
U_BOOT_CMD(
cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
"Reset the board or alternate bank",
"reset - hard reset to default bank\n"
"cpld reset altbank - reset to alternate bank\n"
"cpld dump - display the CPLD registers\n"
);

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/**
* Copyright 2014 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*
*/
struct cpld_data {
u8 cpld_ver; /* 0x00 - CPLD Major Revision Register */
u8 cpld_ver_sub; /* 0x01 - CPLD Minor Revision Register */
u8 hw_ver; /* 0x02 - Hardware Revision Register */
u8 sw_ver; /* 0x03 - Software Revision register */
u8 res0[12]; /* 0x04 - 0x0F - not used */
u8 reset_ctl1; /* 0x10 - Reset control Register1 */
u8 reset_ctl2; /* 0x11 - Reset control Register2 */
u8 int_status; /* 0x12 - Interrupt status Register */
u8 flash_csr; /* 0x13 - Flash control and status register */
u8 fan_ctl_status; /* 0x14 - Fan control and status register */
u8 led_ctl_status; /* 0x15 - LED control and status register */
u8 sfp_ctl_status; /* 0x16 - SFP control and status register */
u8 misc_ctl_status; /* 0x17 - Miscellanies ctrl & status register*/
u8 boot_override; /* 0x18 - Boot override register */
u8 boot_config1; /* 0x19 - Boot config override register*/
u8 boot_config2; /* 0x1A - Boot config override register*/
} cpld_data_t;
/* Pointer to the CPLD register set */
u8 cpld_read(unsigned int reg);
void cpld_write(unsigned int reg, u8 value);
#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg))
#define CPLD_WRITE(reg, value)\
cpld_write(offsetof(struct cpld_data, reg), value)
/* CPLD on IFC */
#define CPLD_LBMAP_MASK 0x3F
#define CPLD_BANK_SEL_MASK 0x07
#define CPLD_BANK_OVERRIDE 0x40
#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK 0 */
#define CPLD_LBMAP_RESET 0xFF
#define CPLD_LBMAP_SHIFT 0x03
#define CPLD_BOOT_SEL 0x80

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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
};
/*
* datarate_mhz_high values need to be in ascending order
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{2, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{1, 833, 0, 4, 6, 0x06060607, 0x08080807,},
{1, 1350, 0, 4, 7, 0x0708080A, 0x0A0B0C09,},
{1, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
struct cpu_type *cpu = gd->arch.cpu;
if (ctrl_num > 1) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust according to the board ddr freqency and n_banks
* specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks &&
(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found\n");
printf("for data rate %lu MT/s\n", ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
debug("\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, ",
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2);
debug("wrlvl_ctrl_3 0x%x\n", pbsp->wrlvl_ctl_3);
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* rtt and rtt_wr override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_OFF);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_OFF);
/* T1023 supports max DDR bus 32bit width, T1024 supports DDR 64bit,
* force DDR bus width to 32bit for T1023
*/
if (cpu->soc_ver == SVR_T1023)
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#ifdef CONFIG_FORCE_DDR_DATA_BUS_WIDTH_32
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
#else
/* DDR has been initialised by first stage boot loader */
dram_size = fsl_ddr_sdram_size();
#endif
return dram_size;
}

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/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <malloc.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <miiphy.h>
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
int board_eth_init(bd_t *bis)
{
#if defined(CONFIG_FMAN_ENET)
int i, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
case 0x95:
/* 10G XFI with Aquantia PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_RGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}
void fdt_fixup_board_enet(void *fdt)
{
}

32
board/freescale/t102xrdb/law.c Normal file
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@ -0,0 +1,32 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
#ifndef CONFIG_SYS_NO_FLASH
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
#ifdef CONFIG_SYS_CPLD_BASE_PHYS
SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

23
board/freescale/t102xrdb/pci.c Normal file
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@ -0,0 +1,23 @@
/*
* Copyright 2007-2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

107
board/freescale/t102xrdb/spl.c Normal file
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@ -0,0 +1,107 @@
/* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <malloc.h>
#include <ns16550.h>
#include <nand.h>
#include <i2c.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <spi_flash.h>
DECLARE_GLOBAL_DATA_PTR;
phys_size_t get_effective_memsize(void)
{
return CONFIG_SYS_L3_SIZE;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */
memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t));
/* Update GD pointer */
gd = (gd_t *)(CONFIG_SPL_GD_ADDR);
console_init_f();
/* initialize selected port with appropriate baud rate */
sys_clk = get_board_sys_clk();
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
ccb_clk / 16 / CONFIG_BAUDRATE);
#if defined(CONFIG_SPL_MMC_BOOT)
puts("\nSD boot...\n");
#elif defined(CONFIG_SPL_SPI_BOOT)
puts("\nSPI boot...\n");
#elif defined(CONFIG_SPL_NAND_BOOT)
puts("\nNAND boot...\n");
#endif
relocate_code(CONFIG_SPL_RELOC_STACK, (gd_t *)CONFIG_SPL_GD_ADDR, 0x0);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
bd_t *bd;
bd = (bd_t *)(gd + sizeof(gd_t));
memset(bd, 0, sizeof(bd_t));
gd->bd = bd;
bd->bi_memstart = CONFIG_SYS_INIT_L3_ADDR;
bd->bi_memsize = CONFIG_SYS_L3_SIZE;
probecpu();
get_clocks();
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
CONFIG_SPL_RELOC_MALLOC_SIZE);
#ifdef CONFIG_SPL_NAND_BOOT
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_MMC_BOOT
mmc_initialize(bd);
mmc_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
#ifdef CONFIG_SPL_SPI_BOOT
spi_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
(uchar *)CONFIG_ENV_ADDR);
#endif
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
gd->env_valid = 1;
i2c_init_all();
gd->ram_size = initdram(0);
#ifdef CONFIG_SPL_MMC_BOOT
mmc_boot();
#elif defined(CONFIG_SPL_SPI_BOOT)
spi_boot();
#elif defined(CONFIG_SPL_NAND_BOOT)
nand_boot();
#endif
}

26
board/freescale/t102xrdb/t1024_pbi.cfg Normal file
View File

@ -0,0 +1,26 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 256KB SRAM
09010100 00000000
09010104 fffc0007
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000cd0 00000000
09000cd4 fffc0000
09000cd8 81000011
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#Flush PBL data
091380c0 000FFFFF

8
board/freescale/t102xrdb/t1024_rcw.cfg Normal file
View File

@ -0,0 +1,8 @@
#PBL preamble and RCW header for T1024RDB
aa55aa55 010e0100
#SerDes Protocol: 0x95
#Core/DDR: 1400Mhz/1600MT/s with single source clock
0810000c 00000000 00000000 00000000
4a800003 80000012 ec027000 21000000
00000000 00000000 00000000 00030810
00000000 0b005a08 00000000 00000006

144
board/freescale/t102xrdb/t102xrdb.c Normal file
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@ -0,0 +1,144 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_portals.h>
#include <asm/fsl_liodn.h>
#include <asm/mpc85xx_gpio.h>
#include <fm_eth.h>
#include "t102xrdb.h"
#include "cpld.h"
DECLARE_GLOBAL_DATA_PTR;
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
printf("Board: %sRDB, ", cpu->name);
printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
#else
u8 reg;
reg = CPLD_READ(flash_csr);
if (reg & CPLD_BOOT_SEL) {
puts("NAND\n");
} else {
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
#endif
puts("SERDES Reference Clocks:\n");
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
return 0;
}
int board_early_init_r(void)
{
#ifdef CONFIG_SYS_FLASH_BASE
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
/*
* Remap Boot flash region to caching-inhibited
* so that flash can be erased properly.
*/
/* Flush d-cache and invalidate i-cache of any FLASH data */
flush_dcache();
invalidate_icache();
if (flash_esel == -1) {
/* very unlikely unless something is messed up */
puts("Error: Could not find TLB for FLASH BASE\n");
flash_esel = 2; /* give our best effort to continue */
} else {
/* invalidate existing TLB entry for flash + promjet */
disable_tlb(flash_esel);
}
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, flash_esel, BOOKE_PAGESZ_256M, 1);
#endif
set_liodns();
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
return 0;
}
unsigned long get_board_sys_clk(void)
{
return CONFIG_SYS_CLK_FREQ;
}
unsigned long get_board_ddr_clk(void)
{
return CONFIG_DDR_CLK_FREQ;
}
int misc_init_r(void)
{
return 0;
}
int ft_board_setup(void *blob, bd_t *bd)
{
phys_addr_t base;
phys_size_t size;
ft_cpu_setup(blob, bd);
base = getenv_bootm_low();
size = getenv_bootm_size();
fdt_fixup_memory(blob, (u64)base, (u64)size);
#ifdef CONFIG_PCI
pci_of_setup(blob, bd);
#endif
fdt_fixup_liodn(blob);
fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
return 0;
}
#ifdef CONFIG_DEEP_SLEEP
void board_mem_sleep_setup(void)
{
/* does not provide HW signals for power management */
CPLD_WRITE(misc_ctl_status, (CPLD_READ(misc_ctl_status) & ~0x40));
/* Disable MCKE isolation */
gpio_set_value(2, 0);
udelay(1);
}
#endif

13
board/freescale/t102xrdb/t102xrdb.h Normal file
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@ -0,0 +1,13 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __T1024_RDB_H__
#define __T1024_RDB_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#endif

117
board/freescale/t102xrdb/tlb.c Normal file
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@ -0,0 +1,117 @@
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/mmu.h>
struct fsl_e_tlb_entry tlb_table[] = {
/* TLB 0 - for temp stack in cache */
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
/* TLB 1 */
/* *I*** - Covers boot page */
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
/*
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
*/
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_256K, 1),
#else
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_4K, 1),
#endif
/* *I*G* - CCSRBAR */
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_16M, 1),
/* *I*G* - Flash, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_256M, 1),
#ifndef CONFIG_SPL_BUILD
/* *I*G* - PCI */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 3, BOOKE_PAGESZ_1G, 1),
/* *I*G* - PCI I/O */
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 4, BOOKE_PAGESZ_256K, 1),
/* Bman/Qman */
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 5, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_16M, 1),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_16M, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_16M, 1),
#endif
#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_4M, 1),
#endif
#ifdef CONFIG_SYS_NAND_BASE
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
#endif
#ifdef CONFIG_SYS_CPLD_BASE
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 11, BOOKE_PAGESZ_256K, 1),
#endif
#if defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SPL_BUILD)
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 12, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 13, BOOKE_PAGESZ_1G, 1)
#endif
/* entry 14 and 15 has been used hard coded, they will be disabled
* in cpu_init_f, so if needed more, will use entry 16 later.
*/
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);

26
board/freescale/t104xrdb/spl.c
View File

@ -34,20 +34,26 @@ unsigned long get_board_ddr_clk(void)
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, uart_clk;
#ifdef CONFIG_SPL_NAND_BOOT
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
u32 porsr1, pinctl;
u32 svr = get_svr();
#endif
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
#ifdef CONFIG_SPL_NAND_BOOT
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible during
* NAND boot because IFC signals > IFC_AD7 are not enabled.
* This workaround changes RCW source to make all signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK)) | 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000), pinctl);
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND)
if (IS_SVR_REV(svr, 1, 0)) {
/*
* There is T1040 SoC issue where NOR, FPGA are inaccessible
* during NAND boot because IFC signals > IFC_AD7 are not
* enabled. This workaround changes RCW source to make all
* signals enabled.
*/
porsr1 = in_be32(&gur->porsr1);
pinctl = ((porsr1 & ~(FSL_CORENET_CCSR_PORSR1_RCW_MASK))
| 0x24800000);
out_be32((unsigned int *)(CONFIG_SYS_DCSRBAR + 0x20000),
pinctl);
}
#endif
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */

15
board/freescale/t208xqds/ddr.h
View File

@ -28,17 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
{2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{2, 1200, 0, 5, 7, 0x0708090a, 0x0b0c0d09},
{2, 1400, 0, 5, 7, 0x08090a0c, 0x0d0e0f0a},
{2, 1700, 0, 5, 8, 0x090a0b0c, 0x0e10110c},
{2, 1900, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{2, 2140, 0, 5, 8, 0x090b0c0f, 0x1012130d},
{1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
{1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
{1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
{1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
{1, 1700, 0, 4, 8, 0x080a0a0c, 0x0c0d0e0a},
{1, 1900, 0, 5, 8, 0x090a0c0d, 0x0e0f110c},
{1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};

16
board/freescale/t208xqds/t2080_rcw.cfg
View File

@ -1,8 +1,16 @@
#PBL preamble and RCW header
aa55aa55 010e0100
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/2133MT/s
12100017 15000000 00000000 00000000
66150002 00008400 e8104000 c1000000
#For T2080 v1.0
#SerDes=0x66_0x16, Core=1533MHz, DDR=2133MT/s
#12100017 15000000 00000000 00000000
#66150002 00008400 e8104000 c1000000
#00000000 00000000 00000000 000307fc
#00000000 00000000 00000000 00000004
#For T2080 v1.1
#SerDes=0x66_0x15, Core=1800MHz, DDR=1867MT/s
0c070012 0e000000 00000000 00000000
66150002 00000000 e8104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004

13
board/freescale/t208xqds/t208xqds.c
View File

@ -20,6 +20,7 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/vid.h"
#include "t208xqds.h"
#include "t208xqds_qixis.h"
@ -86,6 +87,11 @@ int select_i2c_ch_pca9547(u8 ch)
return 0;
}
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
}
int brd_mux_lane_to_slot(void)
{
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@ -358,6 +364,13 @@ int board_early_init_r(void)
/* Disable remote I2C connection to qixis fpga */
QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
/*
* Adjust core voltage according to voltage ID
* This function changes I2C mux to channel 2.
*/
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
brd_mux_lane_to_slot();
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

20
board/freescale/t208xrdb/t2080_rcw.cfg
View File

@ -1,8 +1,16 @@
#PBL preamble and RCW header for T2080RDB
#PBL preamble and RCW header
aa55aa55 010e0100
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/1600MT/s
120c0017 15000000 00000000 00000000
66150002 00008400 ec104000 c1000000
00000000 00000000 00000000 000307fc
#For T2080 v1.0
#SerDes=0x66_0x16, Core=1533MHz, DDR=1600MT/s
#120c0017 15000000 00000000 00000000
#66150002 00008400 ec104000 c1000000
#00000000 00000000 00000000 000307fc
#00000000 00000000 00000000 00000004
#For T2080 v1.1
#SerDes=0x66_0x15, Core:1800MHz, DDR:1600MT/s
1206001b 15000000 00000000 00000000
66150002 00000000 e8104000 c1000000
00800000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004

2
board/keymile/km82xx/km82xx.c
View File

@ -300,11 +300,9 @@ phys_size_t initdram(int board_type)
out_8(&memctl->memc_psrt, CONFIG_SYS_PSRT);
out_be16(&memctl->memc_mptpr, CONFIG_SYS_MPTPR);
#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
psize = probe_sdram(memctl);
#endif /* CONFIG_SYS_RAMBOOT */
icache_enable();

4
board/muas3001/muas3001.c
View File

@ -243,14 +243,11 @@ phys_size_t initdram (int board_type)
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
long psize;
#ifndef CONFIG_SYS_RAMBOOT
long sizelittle, sizebig;
#endif
memctl->memc_psrt = CONFIG_SYS_PSRT;
memctl->memc_mptpr = CONFIG_SYS_MPTPR;
#ifndef CONFIG_SYS_RAMBOOT
/* 60x SDRAM setup:
*/
sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
@ -263,7 +260,6 @@ phys_size_t initdram (int board_type)
psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
(uchar *) CONFIG_SYS_SDRAM_BASE);
}
#endif /* CONFIG_SYS_RAMBOOT */
icache_enable ();

20
common/Makefile
View File

@ -8,22 +8,12 @@
# core
ifndef CONFIG_SPL_BUILD
obj-y += main.o
obj-y += command.o
obj-y += exports.o
obj-y += hash.o
ifdef CONFIG_SYS_HUSH_PARSER
obj-y += cli_hush.o
endif
# We always have this since drivers/ddr/fs/interactive.c needs it
obj-y += cli_simple.o
obj-y += cli.o
obj-y += cli_readline.o
obj-y += s_record.o
obj-y += xyzModem.o
obj-y += cmd_disk.o
# This option is not just y/n - it can have a numeric value
ifdef CONFIG_BOOTDELAY
obj-y += autoboot.o
@ -272,4 +262,14 @@ endif
obj-$(CONFIG_CMD_BLOB) += cmd_blob.o
# We always have this since drivers/ddr/fs/interactive.c needs it
obj-y += cli_simple.o
obj-y += cli.o
obj-y += cli_readline.o
obj-y += command.o
obj-y += s_record.o
obj-y += xyzModem.o
obj-y += cmd_disk.o
CFLAGS_env_embedded.o := -Wa,--no-warn -DENV_CRC=$(shell tools/envcrc 2>/dev/null)

4
configs/T1024QDS_D4_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SYS_FSL_DDR4,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y

5
configs/T1024QDS_NAND_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XQDS=y

5
configs/T1024QDS_SDCARD_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XQDS=y

4
configs/T1024QDS_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XQDS=y

5
configs/T1024QDS_SPIFLASH_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XQDS=y

5
configs/T1024RDB_NAND_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XRDB=y

5
configs/T1024RDB_SDCARD_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XRDB=y

4
configs/T1024RDB_SECURE_BOOT_defconfig Normal file
View File

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y

5
configs/T1024RDB_SPIFLASH_defconfig Normal file
View File

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+S:CONFIG_PPC=y
+S:CONFIG_MPC85xx=y
+S:CONFIG_TARGET_T102XRDB=y

4
configs/T1024RDB_defconfig Normal file
View File

@ -0,0 +1,4 @@
CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y

10
doc/README.fsl-dpaa Normal file
View File

@ -0,0 +1,10 @@
This file documents Freescale DPAA-specific options.
FMan (Frame Manager)
- CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
on SoCs earlier(e.g. T4240, T2080), the notation between 10GEC and MAC as below:
10GEC1->MAC9, 10GEC2->MAC10, 10GEC3->MAC1, 10GEC4->MAC2
on SoCs later(e.g. T1024, etc), the notation between 10GEC and MAC as below:
10GEC1->MAC1, 10GEC2->MAC2
so we introduce CONFIG_FSL_FM_10GEC_REGULAR_NOTATION to identify the new SoCs on
which 10GEC enumeration is consistent with MAC enumeration.

31
drivers/ddr/fsl/ctrl_regs.c
View File

@ -253,22 +253,30 @@ static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
/* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
#if !defined(CONFIG_SYS_FSL_DDR1)
/*
* Check DIMM configuration, return 2 if quad-rank or two dual-rank
* Return 1 if other two slots configuration. Return 0 if single slot.
*/
static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
{
#if CONFIG_DIMM_SLOTS_PER_CTLR == 1
if (dimm_params[0].n_ranks == 4)
return 1;
return 2;
#endif
#if CONFIG_DIMM_SLOTS_PER_CTLR == 2
if ((dimm_params[0].n_ranks == 2) &&
(dimm_params[1].n_ranks == 2))
return 1;
return 2;
#ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
if (dimm_params[0].n_ranks == 4)
return 1;
return 2;
#endif
if ((dimm_params[0].n_ranks != 0) &&
(dimm_params[2].n_ranks != 0))
return 1;
#endif
return 0;
}
@ -316,6 +324,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
#elif defined(CONFIG_SYS_FSL_DDR3)
unsigned int data_rate = get_ddr_freq(0);
int txp;
int odt_overlap;
/*
* (tXARD and tXARDS). Empirical?
* The DDR3 spec has not tXARD,
@ -331,13 +340,23 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
/* set the turnaround time */
/*
* for single quad-rank DIMM and two dual-rank DIMMs
* for single quad-rank DIMM and two-slot DIMMs
* to avoid ODT overlap
*/
if (avoid_odt_overlap(dimm_params)) {
odt_overlap = avoid_odt_overlap(dimm_params);
switch (odt_overlap) {
case 2:
twwt_mclk = 2;
trrt_mclk = 1;
break;
case 1:
twwt_mclk = 1;
trrt_mclk = 0;
break;
default:
break;
}
/* for faster clock, need more time for data setup */
trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
@ -383,7 +402,7 @@ static void set_timing_cfg_0(fsl_ddr_cfg_regs_t *ddr,
);
debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
}
#endif /* defined(CONFIG_SYS_FSL_DDR2) */
#endif /* !defined(CONFIG_SYS_FSL_DDR1) */
/* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
static void set_timing_cfg_3(fsl_ddr_cfg_regs_t *ddr,

22
drivers/ddr/fsl/ddr4_dimm_params.c
View File

@ -126,6 +126,12 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
{
unsigned int retval;
int i;
const u8 udimm_rc_e_dq[18] = {
0x0c, 0x2c, 0x15, 0x35, 0x15, 0x35, 0x0b, 0x2c, 0x15,
0x35, 0x0b, 0x35, 0x0b, 0x2c, 0x0b, 0x35, 0x15, 0x36
};
int spd_error = 0;
u8 *ptr;
if (spd->mem_type) {
if (spd->mem_type != SPD_MEMTYPE_DDR4) {
@ -179,6 +185,22 @@ ddr_compute_dimm_parameters(const generic_spd_eeprom_t *spd,
/* Unbuffered DIMMs */
if (spd->mod_section.unbuffered.addr_mapping & 0x1)
pdimm->mirrored_dimm = 1;
if ((spd->mod_section.unbuffered.mod_height & 0xe0) == 0 &&
(spd->mod_section.unbuffered.ref_raw_card == 0x04)) {
/* Fix SPD error found on DIMMs with raw card E0 */
for (i = 0; i < 18; i++) {
if (spd->mapping[i] == udimm_rc_e_dq[i])
continue;
spd_error = 1;
debug("SPD byte %d: 0x%x, should be 0x%x\n",
60 + i, spd->mapping[i],
udimm_rc_e_dq[i]);
ptr = (u8 *)&spd->mapping[i];
*ptr = udimm_rc_e_dq[i];
}
if (spd_error)
puts("SPD DQ mapping error fixed\n");
}
break;
default:

2
drivers/net/fm/Makefile
View File

@ -28,6 +28,8 @@ obj-$(CONFIG_PPC_T1040) += t1040.o
obj-$(CONFIG_PPC_T1042) += t1040.o
obj-$(CONFIG_PPC_T1020) += t1040.o
obj-$(CONFIG_PPC_T1022) += t1040.o
obj-$(CONFIG_PPC_T1023) += t1024.o
obj-$(CONFIG_PPC_T1024) += t1024.o
obj-$(CONFIG_PPC_T2080) += t2080.o
obj-$(CONFIG_PPC_T2081) += t2080.o
obj-$(CONFIG_PPC_T4240) += t4240.o

64
drivers/net/fm/b4860.c
View File

@ -10,6 +10,7 @@
#include <asm/io.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
@ -46,15 +47,76 @@ void fman_enable_port(enum fm_port port)
phy_interface_t fman_port_enet_if(enum fm_port port)
{
#if defined(CONFIG_B4860QDS)
u32 serdes2_prtcl;
char buffer[HWCONFIG_BUFFER_SIZE];
char *buf = NULL;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
/*B4860 has two 10Gig Mac*/
if ((port == FM1_10GEC1 || port == FM1_10GEC2) &&
((is_serdes_configured(XAUI_FM1_MAC9)) ||
(is_serdes_configured(XAUI_FM1_MAC10))))
#if !defined(CONFIG_B4860QDS)
(is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10)) ||
#endif
(is_serdes_configured(XAUI_FM1_MAC10))
))
return PHY_INTERFACE_MODE_XGMII;
#if defined(CONFIG_B4860QDS)
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
if (serdes2_prtcl) {
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (serdes2_prtcl) {
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
/*
* Extract hwconfig from environment since environment
* is not setup yet
*/
getenv_f("hwconfig", buffer, sizeof(buffer));
buf = buffer;
/* check if XFI interface enable in hwconfig for 10g */
if (hwconfig_subarg_cmp_f("fsl_b4860_serdes2",
"sfp_amc", "sfp", buf)) {
if ((port == FM1_10GEC1 ||
port == FM1_10GEC2) &&
((is_serdes_configured(XFI_FM1_MAC9)) ||
(is_serdes_configured(XFI_FM1_MAC10))))
return PHY_INTERFACE_MODE_XGMII;
else if ((port == FM1_DTSEC1) ||
(port == FM1_DTSEC2) ||
(port == FM1_DTSEC3) ||
(port == FM1_DTSEC4))
return PHY_INTERFACE_MODE_NONE;
}
}
}
#endif
/* Fix me need to handle RGMII here first */
switch (port) {

7
drivers/net/fm/eth.c
View File

@ -565,9 +565,11 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
num = fm_eth->num;
#ifdef CONFIG_SYS_FMAN_V3
#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
if (fm_eth->type == FM_ETH_10G_E) {
/* 10GEC1/10GEC2 use mEMAC9/mEMAC10
* 10GEC3/10GEC4 use mEMAC1/mEMAC2
/* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
* 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
* 10GEC1 uses mEMAC1 on T1024.
* so it needs to change the num.
*/
if (fm_eth->num >= 2)
@ -575,6 +577,7 @@ static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
else
num += 8;
}
#endif
base = &reg->memac[num].fm_memac;
phyregs = &reg->memac[num].fm_memac_mdio;
#else

2
drivers/net/fm/init.c
View File

@ -254,8 +254,10 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop)
*/
if (((info->port == FM1_DTSEC9) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC10) && (PORT_IS_ENABLED(FM1_10GEC2))) ||
((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC1))) ||
((info->port == FM1_DTSEC1) && (PORT_IS_ENABLED(FM1_10GEC3))) ||
((info->port == FM1_DTSEC2) && (PORT_IS_ENABLED(FM1_10GEC4))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||
((info->port == FM1_10GEC1) && (PORT_IS_ENABLED(FM1_DTSEC9))) ||
((info->port == FM1_10GEC2) && (PORT_IS_ENABLED(FM1_DTSEC10))) ||
((info->port == FM1_10GEC3) && (PORT_IS_ENABLED(FM1_DTSEC1))) ||

88
drivers/net/fm/t1024.c Normal file
View File

@ -0,0 +1,88 @@
/* Copyright 2014 Freescale Semiconductor, Inc.
*
* Shengzhou Liu <Shengzhou.Liu@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <phy.h>
#include <fm_eth.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_serdes.h>
u32 port_to_devdisr[] = {
[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
};
static int is_device_disabled(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2;
}
void fman_disable_port(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
}
phy_interface_t fman_port_enet_if(enum fm_port port)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port))
return PHY_INTERFACE_MODE_NONE;
if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
return PHY_INTERFACE_MODE_XGMII;
if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
FSL_CORENET_RCWSR13_EC2_RGMII) &&
(!is_serdes_configured(QSGMII_FM1_A)))
return PHY_INTERFACE_MODE_RGMII;
if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_RGMII) &&
(!is_serdes_configured(QSGMII_FM1_A)))
return PHY_INTERFACE_MODE_RGMII;
/* handle SGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII;
else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
+ port - FM1_DTSEC1))
return PHY_INTERFACE_MODE_SGMII_2500;
break;
default:
break;
}
/* handle QSGMII */
switch (port) {
case FM1_DTSEC1:
case FM1_DTSEC2:
case FM1_DTSEC3:
case FM1_DTSEC4:
/* check lane A on SerDes1 */
if (is_serdes_configured(QSGMII_FM1_A))
return PHY_INTERFACE_MODE_QSGMII;
break;
default:
break;
}
return PHY_INTERFACE_MODE_NONE;
}

4
drivers/net/fm/t1040.c
View File

@ -25,8 +25,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
if ((port == FM1_DTSEC4) &&
@ -38,8 +36,6 @@ phy_interface_t fman_port_enet_if(enum fm_port port)
else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII)
return PHY_INTERFACE_MODE_MII;
else
return PHY_INTERFACE_MODE_NONE;
}
if (port == FM1_DTSEC5) {

1
drivers/net/phy/Makefile
View File

@ -13,6 +13,7 @@ obj-$(CONFIG_PHYLIB) += phy.o
obj-$(CONFIG_PHYLIB_10G) += generic_10g.o
obj-$(CONFIG_PHY_ATHEROS) += atheros.o
obj-$(CONFIG_PHY_BROADCOM) += broadcom.o
obj-$(CONFIG_PHY_CORTINA) += cortina.o
obj-$(CONFIG_PHY_DAVICOM) += davicom.o
obj-$(CONFIG_PHY_ET1011C) += et1011c.o
obj-$(CONFIG_PHY_LXT) += lxt.o

333
drivers/net/phy/cortina.c Normal file
View File

@ -0,0 +1,333 @@
/*
* Cortina CS4315/CS4340 10G PHY drivers
*
* SPDX-License-Identifier: GPL-2.0+
*
* Copyright 2014 Freescale Semiconductor, Inc.
*
*/
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <linux/ctype.h>
#include <linux/string.h>
#include <linux/err.h>
#include <phy.h>
#include <cortina.h>
#ifdef CONFIG_SYS_CORTINA_FW_IN_NAND
#include <nand.h>
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
#include <spi_flash.h>
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
#include <mmc.h>
#endif
#ifndef CONFIG_PHYLIB_10G
#error The Cortina PHY needs 10G support
#endif
struct cortina_reg_config cortina_reg_cfg[] = {
/* CS4315_enable_sr_mode */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
{VILLA_MSEQ_OPTIONS, 0xf},
{VILLA_MSEQ_PC, 0x0},
{VILLA_MSEQ_BANKSELECT, 0x4},
{VILLA_LINE_SDS_COMMON_SRX0_RX_CPA, 0x55},
{VILLA_LINE_SDS_COMMON_SRX0_RX_LOOP_FILTER, 0x30},
{VILLA_DSP_SDS_SERDES_SRX_DFE0_SELECT, 0x1},
{VILLA_DSP_SDS_DSP_COEF_DFE0_SELECT, 0x2},
{VILLA_LINE_SDS_COMMON_SRX0_RX_CPB, 0x2003},
{VILLA_DSP_SDS_SERDES_SRX_FFE_DELAY_CTRL, 0xF047},
{VILLA_MSEQ_ENABLE_MSB, 0x0000},
{VILLA_MSEQ_SPARE21_LSB, 0x6},
{VILLA_MSEQ_RESET_COUNT_LSB, 0x0},
{VILLA_MSEQ_SPARE12_MSB, 0x0000},
/*
* to invert the receiver path, uncomment the next line
* write (VILLA_MSEQ_SPARE12_MSB, 0x4000)
*
* SPARE2_LSB is used to configure the device while in sr mode to
* enable power savings and to use the optical module LOS signal.
* in power savings mode, the internal prbs checker can not be used.
* if the optical module LOS signal is used as an input to the micro
* code, then the micro code will wait until the optical module
* LOS = 0 before turning on the adaptive equalizer.
* Setting SPARE2_LSB bit 0 to 1 places the devie in power savings mode
* while setting bit 0 to 0 disables power savings mode.
* Setting SPARE2_LSB bit 2 to 0 configures the device to use the
* optical module LOS signal while setting bit 2 to 1 configures the
* device so that it will ignore the optical module LOS SPARE2_LSB = 0
*/
/* enable power savings, ignore optical module LOS */
{VILLA_MSEQ_SPARE2_LSB, 0x5},
{VILLA_MSEQ_SPARE7_LSB, 0x1e},
{VILLA_MSEQ_BANKSELECT, 0x4},
{VILLA_MSEQ_SPARE9_LSB, 0x2},
{VILLA_MSEQ_SPARE3_LSB, 0x0F53},
{VILLA_MSEQ_SPARE3_MSB, 0x2006},
{VILLA_MSEQ_SPARE8_LSB, 0x3FF7},
{VILLA_MSEQ_SPARE8_MSB, 0x0A46},
{VILLA_MSEQ_COEF8_FFE0_LSB, 0xD500},
{VILLA_MSEQ_COEF8_FFE1_LSB, 0x0200},
{VILLA_MSEQ_COEF8_FFE2_LSB, 0xBA00},
{VILLA_MSEQ_COEF8_FFE3_LSB, 0x0100},
{VILLA_MSEQ_COEF8_FFE4_LSB, 0x0300},
{VILLA_MSEQ_COEF8_FFE5_LSB, 0x0300},
{VILLA_MSEQ_COEF8_DFE0_LSB, 0x0700},
{VILLA_MSEQ_COEF8_DFE0N_LSB, 0x0E00},
{VILLA_MSEQ_COEF8_DFE1_LSB, 0x0B00},
{VILLA_DSP_SDS_DSP_COEF_LARGE_LEAK, 0x2},
{VILLA_DSP_SDS_SERDES_SRX_DAC_ENABLEB_LSB, 0xD000},
{VILLA_MSEQ_POWER_DOWN_LSB, 0xFFFF},
{VILLA_MSEQ_POWER_DOWN_MSB, 0x0},
{VILLA_MSEQ_CAL_RX_SLICER, 0x80},
{VILLA_DSP_SDS_SERDES_SRX_DAC_BIAS_SELECT1_MSB, 0x3f},
{VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
{VILLA_MSEQ_OPTIONS, 0x7},
/* set up min value for ffe1 */
{VILLA_MSEQ_COEF_INIT_SEL, 0x2},
{VILLA_DSP_SDS_DSP_PRECODEDINITFFE21, 0x41},
/* CS4315_sr_rx_pre_eq_set_4in */
{VILLA_GLOBAL_MSEQCLKCTRL, 0x8004},
{VILLA_MSEQ_OPTIONS, 0xf},
{VILLA_MSEQ_BANKSELECT, 0x4},
{VILLA_MSEQ_PC, 0x0},
/* for lengths from 3.5 to 4.5inches */
{VILLA_MSEQ_SERDES_PARAM_LSB, 0x0306},
{VILLA_MSEQ_SPARE25_LSB, 0x0306},
{VILLA_MSEQ_SPARE21_LSB, 0x2},
{VILLA_MSEQ_SPARE23_LSB, 0x2},
{VILLA_MSEQ_CAL_RX_DFE_EQ, 0x0},
{VILLA_GLOBAL_MSEQCLKCTRL, 0x4},
{VILLA_MSEQ_OPTIONS, 0x7},
/* CS4315_rx_drive_4inch */
/* for length 4inches */
{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
{VILLA_HOST_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
/* CS4315_tx_drive_4inch */
/* for length 4inches */
{VILLA_GLOBAL_VILLA2_COMPATIBLE, 0x0000},
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLA, 0x3023},
{VILLA_LINE_SDS_COMMON_STX0_TX_OUTPUT_CTRLB, 0xc01E},
};
void cs4340_upload_firmware(struct phy_device *phydev)
{
char line_temp[0x50] = {0};
char reg_addr[0x50] = {0};
char reg_data[0x50] = {0};
int i, line_cnt = 0, column_cnt = 0;
struct cortina_reg_config fw_temp;
char *addr = NULL;
#if defined(CONFIG_SYS_CORTINA_FW_IN_NOR) || \
defined(CONFIG_SYS_CORTINA_FW_IN_REMOTE)
addr = (char *)CONFIG_CORTINA_FW_ADDR;
#elif defined(CONFIG_SYS_CORTINA_FW_IN_NAND)
int ret;
size_t fw_length = CONFIG_CORTINA_FW_LENGTH;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ret = nand_read(&nand_info[0], (loff_t)CONFIG_CORTINA_FW_ADDR,
&fw_length, (u_char *)addr);
if (ret == -EUCLEAN) {
printf("NAND read of Cortina firmware at 0x%x failed %d\n",
CONFIG_CORTINA_FW_ADDR, ret);
}
#elif defined(CONFIG_SYS_CORTINA_FW_IN_SPIFLASH)
int ret;
struct spi_flash *ucode_flash;
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
if (!ucode_flash) {
puts("SF: probe for Cortina ucode failed\n");
} else {
ret = spi_flash_read(ucode_flash, CONFIG_CORTINA_FW_ADDR,
CONFIG_CORTINA_FW_LENGTH, addr);
if (ret)
puts("SF: read for Cortina ucode failed\n");
spi_flash_free(ucode_flash);
}
#elif defined(CONFIG_SYS_CORTINA_FW_IN_MMC)
int dev = CONFIG_SYS_MMC_ENV_DEV;
u32 cnt = CONFIG_CORTINA_FW_LENGTH / 512;
u32 blk = CONFIG_CORTINA_FW_ADDR / 512;
struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
if (!mmc) {
puts("Failed to find MMC device for Cortina ucode\n");
} else {
addr = malloc(CONFIG_CORTINA_FW_LENGTH);
printf("MMC read: dev # %u, block # %u, count %u ...\n",
dev, blk, cnt);
mmc_init(mmc);
(void)mmc->block_dev.block_read(dev, blk, cnt, addr);
/* flush cache after read */
flush_cache((ulong)addr, cnt * 512);
}
#endif
while (*addr != 'Q') {
i = 0;
while (*addr != 0x0a) {
line_temp[i++] = *addr++;
if (0x50 < i) {
printf("Not found Cortina PHY ucode at 0x%x\n",
CONFIG_CORTINA_FW_ADDR);
return;
}
}
addr++; /* skip '\n' */
line_cnt++;
column_cnt = i;
line_temp[column_cnt] = '\0';
if (CONFIG_CORTINA_FW_LENGTH < line_cnt)
return;
for (i = 0; i < column_cnt; i++) {
if (isspace(line_temp[i++]))
break;
}
memcpy(reg_addr, line_temp, i);
memcpy(reg_data, &line_temp[i], column_cnt - i);
strim(reg_addr);
strim(reg_data);
fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff;
fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) &
0xffff;
phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value);
}
}
int cs4340_phy_init(struct phy_device *phydev)
{
int timeout = 100; /* 100ms */
int reg_value;
/* step1: BIST test */
phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004);
phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000);
phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001);
while (--timeout) {
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS);
if (reg_value & mseq_edc_bist_done) {
if (0 == (reg_value & mseq_edc_bist_fail))
break;
}
udelay(1000);
}
if (!timeout) {
printf("%s BIST mseq_edc_bist_done timeout!\n", __func__);
return -1;
}
/* setp2: upload ucode */
cs4340_upload_firmware(phydev);
reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS);
if (reg_value) {
debug("%s checksum status failed.\n", __func__);
return -1;
}
return 0;
}
int cs4340_config(struct phy_device *phydev)
{
cs4340_phy_init(phydev);
return 0;
}
int cs4340_startup(struct phy_device *phydev)
{
phydev->link = 1;
/* For now just lie and say it's 10G all the time */
phydev->speed = SPEED_10000;
phydev->duplex = DUPLEX_FULL;
return 0;
}
struct phy_driver cs4340_driver = {
.name = "Cortina CS4315/CS4340",
.uid = PHY_UID_CS4340,
.mask = 0xfffffff0,
.features = PHY_10G_FEATURES,
.mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS |
MDIO_DEVS_PHYXS | MDIO_DEVS_AN |
MDIO_DEVS_VEND1 | MDIO_DEVS_VEND2),
.config = &cs4340_config,
.startup = &cs4340_startup,
.shutdown = &gen10g_shutdown,
};
int phy_cortina_init(void)
{
phy_register(&cs4340_driver);
return 0;
}
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id)
{
int phy_reg;
bool is_cortina_phy = false;
switch (addr) {
#ifdef CORTINA_PHY_ADDR1
case CORTINA_PHY_ADDR1:
#endif
#ifdef CORTINA_PHY_ADDR2
case CORTINA_PHY_ADDR2:
#endif
#ifdef CORTINA_PHY_ADDR3
case CORTINA_PHY_ADDR3:
#endif
#ifdef CORTINA_PHY_ADDR4
case CORTINA_PHY_ADDR4:
#endif
is_cortina_phy = true;
break;
default:
break;
}
/* Cortina PHY has non-standard offset of PHY ID registers */
if (is_cortina_phy)
phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_LSB);
else
phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
if (phy_reg < 0)
return -EIO;
*phy_id = (phy_reg & 0xffff) << 16;
if (is_cortina_phy)
phy_reg = bus->read(bus, addr, 0, VILLA_GLOBAL_CHIP_ID_MSB);
else
phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
if (phy_reg < 0)
return -EIO;
*phy_id |= (phy_reg & 0xffff);
return 0;
}

3
drivers/net/phy/phy.c
View File

@ -448,6 +448,9 @@ int phy_init(void)
#ifdef CONFIG_PHY_BROADCOM
phy_broadcom_init();
#endif
#ifdef CONFIG_PHY_CORTINA
phy_cortina_init();
#endif
#ifdef CONFIG_PHY_DAVICOM
phy_davicom_init();
#endif

13
drivers/net/phy/vitesse.c
View File

@ -1,8 +1,8 @@
/*
* Vitesse PHY drivers
*
* Copyright 2010-2012 Freescale Semiconductor, Inc.
* Author: Andy Fleming
* Copyright 2010-2014 Freescale Semiconductor, Inc.
* Original Author: Andy Fleming
* Add vsc8662 phy support - Priyanka Jain
* SPDX-License-Identifier: GPL-2.0+
*/
@ -50,6 +50,7 @@
#define MIIM_VSC8574_18G_CMDSTAT 0x8000
/* Vitesse VSC8514 control register */
#define MIIM_VSC8514_MAC_SERDES_CON 0x10
#define MIIM_VSC8514_GENERAL18 0x12
#define MIIM_VSC8514_GENERAL19 0x13
#define MIIM_VSC8514_GENERAL23 0x17
@ -246,6 +247,14 @@ static int vsc8514_config(struct phy_device *phydev)
val = (val & 0xf8ff);
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_GENERAL23, val);
/* Enable Serdes Auto-negotiation */
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS,
PHY_EXT_PAGE_ACCESS_EXTENDED3);
val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON);
val = val | MIIM_VSC8574_MAC_SERDES_ANEG;
phy_write(phydev, MDIO_DEVAD_NONE, MIIM_VSC8514_MAC_SERDES_CON, val);
phy_write(phydev, MDIO_DEVAD_NONE, PHY_EXT_PAGE_ACCESS, 0);
genphy_config_aneg(phydev);
return 0;

6
include/configs/B4860QDS.h
View File

@ -713,8 +713,8 @@ unsigned long get_board_ddr_clk(void);
#endif /* CONFIG_PCI */
#ifdef CONFIG_FMAN_ENET
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x10
#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR 0x11
#define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
#define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
/*B4860 QDS AMC2PEX-2S default PHY_ADDR */
#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7 /*SLOT 1*/
@ -731,6 +731,8 @@ unsigned long get_board_ddr_clk(void);
#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
#endif
#define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
/*
* Environment
*/

2
include/configs/C29XPCIE.h
View File

@ -12,6 +12,8 @@
#define __CONFIG_H
#define CONFIG_PHYS_64BIT
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#ifdef CONFIG_C29XPCIE
#define CONFIG_PPC_C29X

2
include/configs/P1010RDB.h
View File

@ -14,6 +14,8 @@
#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_P1010
#define CONFIG_E500 /* BOOKE e500 family */

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