powerpc: T4240: Remove macro CONFIG_PPC_T4240
Use CONFIG_ARCH_T4240 from Kconfig instead. Signed-off-by: York Sun <york.sun@nxp.com>
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652a7bbd87
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26bc57da0a
@ -274,11 +274,13 @@ config TARGET_T4160RDB
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config TARGET_T4240QDS
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bool "Support T4240QDS"
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select ARCH_T4240
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select SUPPORT_SPL
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select PHYS_64BIT
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config TARGET_T4240RDB
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bool "Support T4240RDB"
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select ARCH_T4240
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select SUPPORT_SPL
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select PHYS_64BIT
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@ -424,6 +426,9 @@ config ARCH_T2081
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config ARCH_T4160
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bool
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config ARCH_T4240
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bool
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source "board/freescale/b4860qds/Kconfig"
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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@ -44,7 +44,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_ids.o
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obj-$(CONFIG_ARCH_P4080) += p4080_ids.o
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obj-$(CONFIG_ARCH_P5020) += p5020_ids.o
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obj-$(CONFIG_ARCH_P5040) += p5040_ids.o
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obj-$(CONFIG_PPC_T4240) += t4240_ids.o
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obj-$(CONFIG_ARCH_T4240) += t4240_ids.o
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obj-$(CONFIG_ARCH_T4160) += t4240_ids.o
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obj-$(CONFIG_PPC_T4080) += t4240_ids.o
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obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
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@ -86,7 +86,7 @@ obj-$(CONFIG_ARCH_P3041) += p3041_serdes.o
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obj-$(CONFIG_ARCH_P4080) += p4080_serdes.o
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obj-$(CONFIG_ARCH_P5020) += p5020_serdes.o
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obj-$(CONFIG_ARCH_P5040) += p5040_serdes.o
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obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
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obj-$(CONFIG_ARCH_T4240) += t4240_serdes.o
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obj-$(CONFIG_ARCH_T4160) += t4240_serdes.o
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obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
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obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
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@ -511,7 +511,7 @@ static void fdt_fixup_usb(void *fdt)
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#define fdt_fixup_usb(x)
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#endif
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#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_PPC_T4240) || \
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#if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
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defined(CONFIG_ARCH_T4160) || defined(CONFIG_PPC_T4080)
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void fdt_fixup_dma3(void *blob)
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{
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@ -529,7 +529,7 @@ void fdt_fixup_dma3(void *blob)
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case 0x29:
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case 0x2d:
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case 0x2e:
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#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
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#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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defined(CONFIG_PPC_T4080)
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u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
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@ -130,7 +130,7 @@ void get_sys_info(sys_info_t *sys_info)
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* it uses 6.
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* T2080 rev 1.1 and later also use half mem_pll comparing with rev 1.0
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*/
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#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
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#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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defined(CONFIG_PPC_T4080) || defined(CONFIG_ARCH_T2080) || \
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defined(CONFIG_ARCH_T2081)
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svr = get_svr();
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@ -15,7 +15,7 @@ struct serdes_config {
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u8 lanes[SRDS_MAX_LANES];
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};
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#ifdef CONFIG_PPC_T4240
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#ifdef CONFIG_ARCH_T4240
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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@ -545,7 +545,7 @@
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#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
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#define CONFIG_ESDHC_HC_BLK_ADDR
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#elif defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
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#elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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defined(CONFIG_PPC_T4080)
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#define CONFIG_E6500
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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@ -553,7 +553,7 @@
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
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#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
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#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
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#ifdef CONFIG_PPC_T4240
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#ifdef CONFIG_ARCH_T4240
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#define CONFIG_MAX_CPUS 12
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#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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@ -1759,7 +1759,7 @@ typedef struct ccsr_gur {
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/* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
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#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT 8
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#define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK 0x3f
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#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
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#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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defined(CONFIG_PPC_T4080)
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xfc000000
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#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 26
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@ -1875,7 +1875,7 @@ defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
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#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII 0x00100000
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#define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE 0x00180000
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#endif
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#if defined(CONFIG_PPC_T4240) || defined(CONFIG_ARCH_T4160) || \
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#if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160) || \
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defined(CONFIG_PPC_T4080)
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#define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */
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#define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000
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@ -12,7 +12,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
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CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND"
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
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@ -12,7 +12,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
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CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
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@ -6,7 +6,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SECURE_BOOT"
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CONFIG_SYS_EXTRA_OPTIONS="SECURE_BOOT"
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CONFIG_BOOTDELAY=10
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_GREPENV=y
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@ -5,7 +5,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
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CONFIG_SYS_EXTRA_OPTIONS="SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000"
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CONFIG_BOOTDELAY=10
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CONFIG_HUSH_PARSER=y
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# CONFIG_CMD_IMLS is not set
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@ -5,7 +5,6 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
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CONFIG_BOOTDELAY=10
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_GREPENV=y
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@ -12,7 +12,7 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
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CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
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CONFIG_BOOTDELAY=10
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CONFIG_SPL=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
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@ -5,7 +5,6 @@ CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="PPC_T4240"
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CONFIG_BOOTDELAY=10
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_GREPENV=y
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@ -32,7 +32,7 @@ obj-$(CONFIG_ARCH_T1023) += t1024.o
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obj-$(CONFIG_ARCH_T1024) += t1024.o
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obj-$(CONFIG_ARCH_T2080) += t2080.o
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obj-$(CONFIG_ARCH_T2081) += t2080.o
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obj-$(CONFIG_PPC_T4240) += t4240.o
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obj-$(CONFIG_ARCH_T4240) += t4240.o
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obj-$(CONFIG_ARCH_T4160) += t4240.o
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obj-$(CONFIG_PPC_T4080) += t4240.o
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obj-$(CONFIG_ARCH_B4420) += b4860.o
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@ -542,7 +542,7 @@ unsigned long get_board_ddr_clk(void);
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* interleaving. It can be cacheline, page, bank, superbank.
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* See doc/README.fsl-ddr for details.
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*/
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#ifdef CONFIG_PPC_T4240
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#ifdef CONFIG_ARCH_T4240
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#define CTRL_INTLV_PREFERED 3way_4KB
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#else
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#define CTRL_INTLV_PREFERED cacheline
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@ -732,7 +732,7 @@ unsigned long get_board_ddr_clk(void);
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* interleaving. It can be cacheline, page, bank, superbank.
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* See doc/README.fsl-ddr for details.
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*/
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#ifdef CONFIG_PPC_T4240
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#ifdef CONFIG_ARCH_T4240
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#define CTRL_INTLV_PREFERED 3way_4KB
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#else
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#define CTRL_INTLV_PREFERED cacheline
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@ -3640,7 +3640,6 @@ CONFIG_PPC4xx_EMAC
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CONFIG_PPC64BRIDGE
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CONFIG_PPC_CLUSTER_START
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CONFIG_PPC_SPINTABLE_COMPATIBLE
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CONFIG_PPC_T4240
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CONFIG_PQ_MDS_PIB
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CONFIG_PQ_MDS_PIB_ATM
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CONFIG_PRAM
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