x86: broadwell: Add support for SDRAM setup
Broadwell uses a binary blob called the memory reference code (MRC) to start up its SDRAM. This is similar to ivybridge so we can mostly use common code for running this blob. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
71a8f2080b
commit
2627c7e2c1
@ -13,3 +13,4 @@ obj-y += pinctrl_broadwell.o
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obj-y += power_state.o
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obj-y += refcode.o
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obj-y += sata.o
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obj-y += sdram.o
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307
arch/x86/cpu/broadwell/sdram.c
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307
arch/x86/cpu/broadwell/sdram.c
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@ -0,0 +1,307 @@
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/*
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* Copyright (c) 2016 Google, Inc
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*
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* From coreboot src/soc/intel/broadwell/romstage/raminit.c
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <syscon.h>
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#include <asm/cpu.h>
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#include <asm/io.h>
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#include <asm/lpc_common.h>
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#include <asm/mrccache.h>
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#include <asm/mrc_common.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/arch/iomap.h>
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#include <asm/arch/me.h>
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#include <asm/arch/pch.h>
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#include <asm/arch/pei_data.h>
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#include <asm/arch/pm.h>
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return mrc_common_board_get_usable_ram_top(total_size);
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}
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void dram_init_banksize(void)
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{
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mrc_common_dram_init_banksize();
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}
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void broadwell_fill_pei_data(struct pei_data *pei_data)
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{
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pei_data->pei_version = PEI_VERSION;
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pei_data->board_type = BOARD_TYPE_ULT;
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pei_data->pciexbar = MCFG_BASE_ADDRESS;
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pei_data->smbusbar = SMBUS_BASE_ADDRESS;
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pei_data->ehcibar = EARLY_EHCI_BAR;
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pei_data->xhcibar = EARLY_XHCI_BAR;
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pei_data->gttbar = EARLY_GTT_BAR;
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pei_data->pmbase = ACPI_BASE_ADDRESS;
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pei_data->gpiobase = GPIO_BASE_ADDRESS;
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pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE;
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pei_data->temp_mmio_base = EARLY_TEMP_MMIO;
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pei_data->tx_byte = sdram_console_tx_byte;
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pei_data->ddr_refresh_2x = 1;
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}
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static inline void pei_data_usb2_port(struct pei_data *pei_data, int port,
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uint16_t length, uint8_t enable,
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uint8_t oc_pin, uint8_t location)
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{
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pei_data->usb2_ports[port].length = length;
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pei_data->usb2_ports[port].enable = enable;
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pei_data->usb2_ports[port].oc_pin = oc_pin;
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pei_data->usb2_ports[port].location = location;
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}
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static inline void pei_data_usb3_port(struct pei_data *pei_data, int port,
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uint8_t enable, uint8_t oc_pin,
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uint8_t fixed_eq)
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{
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pei_data->usb3_ports[port].enable = enable;
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pei_data->usb3_ports[port].oc_pin = oc_pin;
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pei_data->usb3_ports[port].fixed_eq = fixed_eq;
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}
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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/* DQ byte map for Samus board */
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const u8 dq_map[2][6][2] = {
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{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
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{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } },
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{ { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 },
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{ 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } };
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/* DQS CPU<>DRAM map for Samus board */
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const u8 dqs_map[2][8] = {
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{ 2, 0, 1, 3, 6, 4, 7, 5 },
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{ 2, 1, 0, 3, 6, 5, 4, 7 } };
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pei_data->ec_present = 1;
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/* One installed DIMM per channel */
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pei_data->dimm_channel0_disabled = 2;
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pei_data->dimm_channel1_disabled = 2;
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memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
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memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
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/* P0: HOST PORT */
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pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0,
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USB_PORT_BACK_PANEL);
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/* P1: HOST PORT */
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pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1,
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USB_PORT_BACK_PANEL);
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/* P2: RAIDEN */
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pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P3: SD CARD */
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pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P4: RAIDEN */
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pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP,
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USB_PORT_BACK_PANEL);
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/* P5: WWAN (Disabled) */
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pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP,
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USB_PORT_SKIP);
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/* P6: CAMERA */
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pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P7: BT */
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pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP,
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USB_PORT_INTERNAL);
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/* P1: HOST PORT */
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pei_data_usb3_port(pei_data, 0, 1, 0, 0);
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/* P2: HOST PORT */
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pei_data_usb3_port(pei_data, 1, 1, 1, 0);
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/* P3: RAIDEN */
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pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0);
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/* P4: RAIDEN */
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pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0);
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}
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static unsigned long get_top_of_ram(struct udevice *dev)
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{
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/*
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* Base of DPR is top of usable DRAM below 4GiB. The register has
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* 1 MiB alignment and reports the TOP of the range, the base
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* must be calculated from the size in MiB in bits 11:4.
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*/
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u32 dpr, tom;
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dm_pci_read_config32(dev, DPR, &dpr);
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tom = dpr & ~((1 << 20) - 1);
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debug("dpt %08x tom %08x\n", dpr, tom);
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/* Subtract DMA Protected Range size if enabled */
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if (dpr & DPR_EPM)
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tom -= (dpr & DPR_SIZE_MASK) << 16;
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return (unsigned long)tom;
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}
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/**
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* sdram_find() - Find available memory
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*
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* This is a bit complicated since on x86 there are system memory holes all
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* over the place. We create a list of available memory blocks
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*
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* @dev: Northbridge device
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*/
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static int sdram_find(struct udevice *dev)
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{
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struct memory_info *info = &gd->arch.meminfo;
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ulong top_of_ram;
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top_of_ram = get_top_of_ram(dev);
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mrc_add_memory_area(info, 0, top_of_ram);
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/* Add MTRRs for memory */
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mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
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return 0;
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}
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static int prepare_mrc_cache(struct pei_data *pei_data)
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{
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struct mrc_data_container *mrc_cache;
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struct mrc_region entry;
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int ret;
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ret = mrccache_get_region(NULL, &entry);
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if (ret)
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return ret;
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mrc_cache = mrccache_find_current(&entry);
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if (!mrc_cache)
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return -ENOENT;
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pei_data->saved_data = mrc_cache->data;
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pei_data->saved_data_size = mrc_cache->data_size;
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debug("%s: at %p, size %x checksum %04x\n", __func__,
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pei_data->saved_data, pei_data->saved_data_size,
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mrc_cache->checksum);
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return 0;
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}
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int reserve_arch(void)
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{
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return mrccache_reserve();
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}
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int dram_init(void)
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{
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struct pei_data _pei_data __aligned(8);
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struct pei_data *pei_data = &_pei_data;
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struct udevice *dev, *me_dev, *pch_dev;
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struct chipset_power_state ps;
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const void *spd_data;
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int ret, size;
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memset(pei_data, '\0', sizeof(struct pei_data));
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/* Print ME state before MRC */
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ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
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if (ret)
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return ret;
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intel_me_status(me_dev);
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/* Save ME HSIO version */
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ret = uclass_first_device(UCLASS_PCH, &pch_dev);
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if (ret)
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return ret;
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if (!pch_dev)
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return -ENODEV;
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power_state_get(pch_dev, &ps);
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intel_me_hsio_version(me_dev, &ps.hsio_version, &ps.hsio_checksum);
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broadwell_fill_pei_data(pei_data);
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mainboard_fill_pei_data(pei_data);
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ret = uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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size = 256;
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ret = mrc_locate_spd(dev, size, &spd_data);
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if (ret)
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return ret;
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memcpy(pei_data->spd_data[0][0], spd_data, size);
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memcpy(pei_data->spd_data[1][0], spd_data, size);
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ret = prepare_mrc_cache(pei_data);
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if (ret)
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debug("prepare_mrc_cache failed: %d\n", ret);
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debug("PEI version %#x\n", pei_data->pei_version);
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ret = mrc_common_init(dev, pei_data, true);
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if (ret)
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return ret;
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debug("Memory init done\n");
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ret = sdram_find(dev);
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if (ret)
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return ret;
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gd->ram_size = gd->arch.meminfo.total_32bit_memory;
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debug("RAM size %llx\n", (unsigned long long)gd->ram_size);
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debug("MRC output data length %#x at %p\n", pei_data->data_to_save_size,
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pei_data->data_to_save);
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/* S3 resume: don't save scrambler seed or MRC data */
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if (pei_data->boot_mode != SLEEP_STATE_S3) {
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/*
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* This will be copied to SDRAM in reserve_arch(), then written
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* to SPI flash in mrccache_save()
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*/
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gd->arch.mrc_output = (char *)pei_data->data_to_save;
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gd->arch.mrc_output_len = pei_data->data_to_save_size;
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}
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gd->arch.pei_meminfo = pei_data->meminfo;
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return 0;
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}
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/* Use this hook to save our SDRAM parameters */
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int misc_init_r(void)
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{
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int ret;
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ret = mrccache_save();
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if (ret)
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printf("Unable to save MRC data: %d\n", ret);
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else
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debug("Saved MRC cache data\n");
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return 0;
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}
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void board_debug_uart_init(void)
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{
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struct udevice *bus = NULL;
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/* com1 / com2 decode range */
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pci_x86_write_config(bus, PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
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pci_x86_write_config(bus, PCH_DEV_LPC, LPC_EN, COMA_LPC_EN,
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PCI_SIZE_16);
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}
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static const struct udevice_id broadwell_syscon_ids[] = {
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{ .compatible = "intel,me", .data = X86_SYSCON_ME },
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{ .compatible = "intel,gma", .data = X86_SYSCON_GMA },
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{ }
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};
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U_BOOT_DRIVER(syscon_intel_me) = {
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.name = "intel_me_syscon",
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.id = UCLASS_SYSCON,
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.of_match = broadwell_syscon_ids,
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};
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177
arch/x86/include/asm/arch-broadwell/pei_data.h
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177
arch/x86/include/asm/arch-broadwell/pei_data.h
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@ -0,0 +1,177 @@
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/*
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* From Coreboot soc/intel/broadwell/include/soc/pei_data.h
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*
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* Copyright (C) 2014 Google Inc.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef ASM_ARCH_PEI_DATA_H
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#define ASM_ARCH_PEI_DATA_H
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#include <linux/linkage.h>
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#define PEI_VERSION 22
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typedef void asmlinkage (*tx_byte_func)(unsigned char byte);
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enum board_type {
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BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
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BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */
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BOARD_TYPE_USER1, /* SV mobile */
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BOARD_TYPE_USER2, /* SV desktop */
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BOARD_TYPE_USER3, /* SV server */
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BOARD_TYPE_ULT, /* ULT */
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BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */
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BOARD_TYPE_UNKNOWN,
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};
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#define MAX_USB2_PORTS 14
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#define MAX_USB3_PORTS 6
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#define USB_OC_PIN_SKIP 8
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enum usb2_port_location {
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USB_PORT_BACK_PANEL = 0,
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USB_PORT_FRONT_PANEL,
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USB_PORT_DOCK,
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USB_PORT_MINI_PCIE,
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USB_PORT_FLEX,
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USB_PORT_INTERNAL,
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USB_PORT_SKIP,
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USB_PORT_NGFF_DEVICE_DOWN,
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};
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struct usb2_port_setting {
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/*
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* Usb Port Length:
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* [16:4] = length in inches in octal format
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* [3:0] = decimal point
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*/
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uint16_t length;
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uint8_t enable;
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uint8_t oc_pin;
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uint8_t location;
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} __packed;
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struct usb3_port_setting {
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uint8_t enable;
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uint8_t oc_pin;
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/*
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* Set to 0 if trace length is > 5 inches
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* Set to 1 if trace length is <= 5 inches
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*/
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uint8_t fixed_eq;
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} __packed;
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struct pei_data {
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uint32_t pei_version;
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enum board_type board_type;
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int boot_mode;
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int ec_present;
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int usbdebug;
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/* Base addresses */
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uint32_t pciexbar;
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uint16_t smbusbar;
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uint32_t xhcibar;
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uint32_t ehcibar;
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uint32_t gttbar;
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uint32_t rcba;
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uint32_t pmbase;
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uint32_t gpiobase;
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uint32_t temp_mmio_base;
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uint32_t tseg_size;
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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int dimm_channel0_disabled;
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int dimm_channel1_disabled;
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/* Set to 0 for memory down */
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uint8_t spd_addresses[4];
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/* Enable 2x Refresh Mode */
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int ddr_refresh_2x;
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/* DQ pins are interleaved on board */
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int dq_pins_interleaved;
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/* Limit DDR3 frequency */
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int max_ddr3_freq;
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/* Disable self refresh */
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int disable_self_refresh;
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/* Disable cmd power/CKEPD */
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int disable_cmd_pwr;
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/* USB port configuration */
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS];
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS];
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/*
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* USB3 board specific PHY tuning
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*/
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/* Valid range: 0x69 - 0x80 */
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uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x80 - 0x9c */
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uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x39 - 0x80 */
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uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS];
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/* Valid range: 0x3d - 0x4a */
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uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS];
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/* Console output function */
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tx_byte_func tx_byte;
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||||
|
||||
/*
|
||||
* DIMM SPD data for memory down configurations
|
||||
* [CHANNEL][SLOT][SPD]
|
||||
*/
|
||||
uint8_t spd_data[2][2][512];
|
||||
|
||||
/*
|
||||
* LPDDR3 DQ byte map
|
||||
* [CHANNEL][ITERATION][2]
|
||||
*
|
||||
* Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side)
|
||||
* DQByteMap[0] - ClkDQByteMap:
|
||||
* - If clock is per rank, program to [0xFF, 0xFF]
|
||||
* - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF]
|
||||
* - If clock is shared by 2 ranks but does not go to all bytes,
|
||||
* Entry[i] defines which DQ bytes Group i services
|
||||
* DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB
|
||||
* DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB
|
||||
* DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB
|
||||
* For DDR, DQByteMap[3:1] = [0xFF, 0]
|
||||
* DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0]
|
||||
* since we have 1 CTL / rank
|
||||
* DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0]
|
||||
* since we have 1 CA Vref
|
||||
*/
|
||||
uint8_t dq_map[2][6][2];
|
||||
|
||||
/*
|
||||
* LPDDR3 Map from CPU DQS pins to SDRAM DQS pins
|
||||
* [CHANNEL][MAX_BYTES]
|
||||
*/
|
||||
uint8_t dqs_map[2][8];
|
||||
|
||||
/* Data read from flash and passed into MRC */
|
||||
const void *saved_data;
|
||||
int saved_data_size;
|
||||
|
||||
/* Disable use of saved data (can be set by mainboard) */
|
||||
int disable_saved_data;
|
||||
|
||||
/* Data from MRC that should be saved to flash */
|
||||
void *data_to_save;
|
||||
int data_to_save_size;
|
||||
struct pei_memory_info meminfo;
|
||||
} __packed;
|
||||
|
||||
void mainboard_fill_pei_data(struct pei_data *pei_data);
|
||||
void broadwell_fill_pei_data(struct pei_data *pei_data);
|
||||
|
||||
#endif
|
||||
@ -19,6 +19,29 @@ enum pei_boot_mode_t {
|
||||
|
||||
};
|
||||
|
||||
struct dimm_info {
|
||||
uint32_t dimm_size;
|
||||
uint16_t ddr_type;
|
||||
uint16_t ddr_frequency;
|
||||
uint8_t rank_per_dimm;
|
||||
uint8_t channel_num;
|
||||
uint8_t dimm_num;
|
||||
uint8_t bank_locator;
|
||||
/* The 5th byte is '\0' for the end of string */
|
||||
uint8_t serial[5];
|
||||
/* The 19th byte is '\0' for the end of string */
|
||||
uint8_t module_part_number[19];
|
||||
uint16_t mod_id;
|
||||
uint8_t mod_type;
|
||||
uint8_t bus_width;
|
||||
} __packed;
|
||||
|
||||
struct pei_memory_info {
|
||||
uint8_t dimm_cnt;
|
||||
/* Maximum num of dimm is 8 */
|
||||
struct dimm_info dimm[8];
|
||||
} __packed;
|
||||
|
||||
struct memory_area {
|
||||
uint64_t start;
|
||||
uint64_t size;
|
||||
@ -59,6 +82,7 @@ struct arch_global_data {
|
||||
enum pei_boot_mode_t pei_boot_mode;
|
||||
const struct pch_gpio_map *gpio_map; /* board GPIO map */
|
||||
struct memory_info meminfo; /* Memory information */
|
||||
struct pei_memory_info pei_meminfo; /* PEI memory information */
|
||||
#ifdef CONFIG_HAVE_FSP
|
||||
void *hob_list; /* FSP HOB list */
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user