leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse Source 
Enable DM PCI for T2080RDB, T4240RDB, T1024RDB, T1042D4RDB, P1020RDB,
P2020RDB, P2041RDB, P3041DS, P4080DS, and MPC8548CDS
This commit is contained in:
Tom Rini
2019-08-29 07:26:13 -04:00
parent 80505e59df 43e881e38b
commit 25f32e0dff
87 changed files with 893 additions and 262 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
arch/powerpc/dts/mpc8548-post.dtsi
View File

@@ -25,3 +25,12 @@
last-interrupt-source = <255>;
};
};
&pcie {
compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

6
arch/powerpc/dts/mpc8548cds.dts
View File

@@ -18,6 +18,12 @@
soc: soc8548@e0000000 {
ranges = <0x0 0x0 0xe0000000 0x100000>;
};
pcie: pcie@e000a000 {
reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "mpc8548-post.dtsi"

6
arch/powerpc/dts/mpc8548cds_36b.dts
View File

@@ -18,6 +18,12 @@
soc: soc8548@fe0000000 {
ranges = <0x0 0xf 0xe0000000 0x100000>;
};
pcie: pcie@fe000a000 {
reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "mpc8548-post.dtsi"

20
arch/powerpc/dts/p1020-post.dtsi
View File

@@ -25,3 +25,23 @@
last-interrupt-source = <255>;
};
};
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* PCIe controller base address 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

12
arch/powerpc/dts/p1020rdb-pc.dts
View File

@@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"

12
arch/powerpc/dts/p1020rdb-pc_36b.dts
View File

@@ -18,6 +18,18 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"

12
arch/powerpc/dts/p1020rdb-pd.dts
View File

@@ -18,6 +18,18 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci1: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p1020-post.dtsi"

30
arch/powerpc/dts/p2020-post.dtsi
View File

@@ -25,3 +25,33 @@
last-interrupt-source = <255>;
};
};
/* PCIe controller base address 0x8000 */
&pci2 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* PCIe controller base address 0x9000 */
&pci1 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};
/* PCIe controller base address 0xa000 */
&pci0 {
compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
};

17
arch/powerpc/dts/p2020rdb-pc.dts
View File

@@ -18,6 +18,23 @@
soc: soc@ffe00000 {
ranges = <0x0 0x0 0xffe00000 0x100000>;
};
pci2: pcie@ffe08000 {
reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
status = "disabled";
};
pci1: pcie@ffe09000 {
reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@ffe0a000 {
reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p2020-post.dtsi"

17
arch/powerpc/dts/p2020rdb-pc_36b.dts
View File

@@ -18,6 +18,23 @@
soc: soc@fffe00000 {
ranges = <0x0 0xf 0xffe00000 0x100000>;
};
pci2: pcie@fffe08000 {
reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */
status = "disabled";
};
pci1: pcie@fffe09000 {
reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pci0: pcie@fffe0a000 {
reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */
ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};
/include/ "p2020-post.dtsi"

36
arch/powerpc/dts/p2041.dtsi
View File

@@ -60,4 +60,40 @@
clock-frequency = <0x0>;
};
};
pcie@ffe200000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};

48
arch/powerpc/dts/p3041.dtsi
View File

@@ -60,4 +60,52 @@
clock-frequency = <0x0>;
};
};
pcie@ffe200000 {
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe203000 {
compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
law_trgt_if = <3>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};

36
arch/powerpc/dts/p4080.dtsi
View File

@@ -80,4 +80,40 @@
clock-frequency = <0x0>;
};
};
pcie@ffe200000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};

36
arch/powerpc/dts/p5040.dtsi
View File

@@ -59,4 +59,40 @@
clock-frequency = <0x0>;
};
};
pcie@ffe200000 {
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe201000 {
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe202000 {
compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};

36
arch/powerpc/dts/t102x.dtsi
View File

@@ -49,4 +49,40 @@
clock-frequency = <0x0>;
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe250000 {
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe260000 {
compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
};
};

48
arch/powerpc/dts/t104x.dtsi
View File

@@ -59,4 +59,52 @@
clock-frequency = <0x0>;
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe250000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe260000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */
};
pcie@ffe270000 {
compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */
law_trgt_if = <3>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */
};
};

48
arch/powerpc/dts/t4240.dtsi
View File

@@ -99,4 +99,52 @@
clock-frequency = <0x0>;
};
};
pcie@ffe240000 {
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */
law_trgt_if = <0>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe250000 {
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */
law_trgt_if = <1>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe260000 {
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */
law_trgt_if = <2>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
};
pcie@ffe270000 {
compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq";
reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */
law_trgt_if = <3>;
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
};
};