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mips: jz47xx: Add Creator CI20 platform

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Add support for the Creator CI20 platform based on the JZ4780 SoC.

Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This commit is contained in:
Paul Burton 2018-12-16 19:25:23 -03:00 committed by Daniel Schwierzeck
parent cd71b1d5d2
commit 25c7de2255
10 changed files with 650 additions and 0 deletions
arch/mips
dts
Makefileci20.dts
mach-jz47xx
Kconfig
board/imgtec/ci20
KconfigMAINTAINERSMakefileREADMEci20.c
configs
ci20_mmc_defconfig
include/configs
ci20.h

1
arch/mips/dts/Makefile
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@ -16,6 +16,7 @@ dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
dtb-$(CONFIG_TARGET_JZ4780_CI20) += ci20.dtb
targets += $(dtb-y)

122
arch/mips/dts/ci20.dts Normal file
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@ -0,0 +1,122 @@
// SPDX-License-Identifier: GPL-2.0+
/dts-v1/;
#include "jz4780.dtsi"
/ {
compatible = "img,ci20", "ingenic,jz4780";
aliases {
serial0 = &uart0;
serial1 = &uart1;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial4:115200n8";
};
memory {
device_type = "memory";
reg = <0x0 0x10000000
0x30000000 0x30000000>;
};
};
&ext {
clock-frequency = <48000000>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&nemc {
status = "okay";
nandc: nand-controller@1 {
compatible = "ingenic,jz4780-nand";
reg = <1 0 0x1000000>;
#address-cells = <1>;
#size-cells = <0>;
ingenic,bch-controller = <&bch>;
ingenic,nemc-tAS = <10>;
ingenic,nemc-tAH = <5>;
ingenic,nemc-tBP = <10>;
ingenic,nemc-tAW = <15>;
ingenic,nemc-tSTRV = <100>;
nand@1 {
reg = <1>;
nand-ecc-step-size = <1024>;
nand-ecc-strength = <24>;
nand-ecc-mode = "hw";
nand-on-flash-bbt;
partitions {
compatible = "fixed-partitions";
#address-cells = <2>;
#size-cells = <2>;
partition@0 {
label = "u-boot-spl";
reg = <0x0 0x0 0x0 0x800000>;
};
partition@0x800000 {
label = "u-boot";
reg = <0x0 0x800000 0x0 0x200000>;
};
partition@0xa00000 {
label = "u-boot-env";
reg = <0x0 0xa00000 0x0 0x200000>;
};
partition@0xc00000 {
label = "boot";
reg = <0x0 0xc00000 0x0 0x4000000>;
};
partition@0x8c00000 {
label = "system";
reg = <0x0 0x4c00000 0x1 0xfb400000>;
};
};
};
};
};
&bch {
status = "okay";
};
&mmc0 {
bus-width = <4>;
max-frequency = <50000000>;
status = "okay";
};
&mmc1 {
bus-width = <4>;
max-frequency = <50000000>;
status = "okay";
};

11
arch/mips/mach-jz47xx/Kconfig
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@ -12,4 +12,15 @@ config SOC_JZ4780
help
Support for Ingenic JZ4780 family SoCs.
choice
prompt "Board select"
config TARGET_JZ4780_CI20
bool "Creator CI20 Reference Board"
select SOC_JZ4780
endchoice
source "board/imgtec/ci20/Kconfig"
endmenu

15
board/imgtec/ci20/Kconfig Normal file
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@ -0,0 +1,15 @@
if TARGET_JZ4780_CI20
config SYS_BOARD
default "ci20"
config SYS_VENDOR
default "imgtec"
config SYS_CONFIG_NAME
default "ci20"
config SYS_TEXT_BASE
default 0x80000000
endif

6
board/imgtec/ci20/MAINTAINERS Normal file
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@ -0,0 +1,6 @@
Creator CI20 BOARD
M: Ezequiel Garcia <ezequiel@collabora.com>
S: Maintained
F: board/imgtec/ci20/
F: include/configs/ci20.h
F: configs/ci20_mmc_defconfig

3
board/imgtec/ci20/Makefile Normal file
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@ -0,0 +1,3 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := ci20.o

10
board/imgtec/ci20/README Normal file
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@ -0,0 +1,10 @@
CI20 U-Boot
Installation to an SD card:
Repartition your card with an MBR such that the first partition starts at an
offset of no less than 270KB. Then install U-Boot SPL & the full U-Boot image
to the card like so:
dd if=spl/u-boot-spl.bin of=/dev/sdX obs=512 seek=1
dd if=u-boot-dtb.img of=/dev/sdX obs=1K seek=14
sync

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board/imgtec/ci20/ci20.c Normal file
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@ -0,0 +1,362 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* CI20 setup code
*
* Copyright (c) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@imgtec.com>
*/
#include <common.h>
#include <environment.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/gpio.h>
#include <mach/jz4780.h>
#include <mach/jz4780_dram.h>
#include <mach/jz4780_gpio.h>
struct ci20_otp {
u32 serial_number;
u32 date;
u8 manufacturer[2];
u8 mac[6];
} __packed;
static void ci20_mux_mmc(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
/* setup MSC1 pins */
writel(0x30f00000, gpio_regs + GPIO_PXINTC(4));
writel(0x30f00000, gpio_regs + GPIO_PXMASKC(4));
writel(0x30f00000, gpio_regs + GPIO_PXPAT1C(4));
writel(0x30f00000, gpio_regs + GPIO_PXPAT0C(4));
writel(0x30f00000, gpio_regs + GPIO_PXPENC(4));
jz4780_clk_ungate_mmc();
}
#ifndef CONFIG_SPL_BUILD
static void ci20_mux_eth(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
#ifdef CONFIG_NAND
/* setup pins (some already setup for NAND) */
writel(0x04030000, gpio_regs + GPIO_PXINTC(0));
writel(0x04030000, gpio_regs + GPIO_PXMASKC(0));
writel(0x04030000, gpio_regs + GPIO_PXPAT1C(0));
writel(0x04030000, gpio_regs + GPIO_PXPAT0C(0));
writel(0x04030000, gpio_regs + GPIO_PXPENS(0));
#else
/* setup pins (as above +NAND CS +RD/WE +SDx +SAx) */
writel(0x0dff00ff, gpio_regs + GPIO_PXINTC(0));
writel(0x0dff00ff, gpio_regs + GPIO_PXMASKC(0));
writel(0x0dff00ff, gpio_regs + GPIO_PXPAT1C(0));
writel(0x0dff00ff, gpio_regs + GPIO_PXPAT0C(0));
writel(0x0dff00ff, gpio_regs + GPIO_PXPENS(0));
writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
#endif
}
static void ci20_mux_jtag(void)
{
#ifdef CONFIG_JTAG
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
/* enable JTAG */
writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
writel(3 << 30, gpio_regs + GPIO_PXPAT0C(0));
#endif
}
static void ci20_mux_nand(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
/* setup pins */
writel(0x002c00ff, gpio_regs + GPIO_PXINTC(0));
writel(0x002c00ff, gpio_regs + GPIO_PXMASKC(0));
writel(0x002c00ff, gpio_regs + GPIO_PXPAT1C(0));
writel(0x002c00ff, gpio_regs + GPIO_PXPAT0C(0));
writel(0x002c00ff, gpio_regs + GPIO_PXPENS(0));
writel(0x00000003, gpio_regs + GPIO_PXINTC(1));
writel(0x00000003, gpio_regs + GPIO_PXMASKC(1));
writel(0x00000003, gpio_regs + GPIO_PXPAT1C(1));
writel(0x00000003, gpio_regs + GPIO_PXPAT0C(1));
writel(0x00000003, gpio_regs + GPIO_PXPENS(1));
/* FRB0_N */
jz47xx_gpio_direction_input(JZ_GPIO(0, 20));
writel(20, gpio_regs + GPIO_PXPENS(0));
/* disable write protect */
jz47xx_gpio_direction_output(JZ_GPIO(5, 22), 1);
}
static void ci20_mux_uart(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
/* UART0 */
writel(0x9, gpio_regs + GPIO_PXINTC(5));
writel(0x9, gpio_regs + GPIO_PXMASKC(5));
writel(0x9, gpio_regs + GPIO_PXPAT1C(5));
writel(0x9, gpio_regs + GPIO_PXPAT0C(5));
writel(0x9, gpio_regs + GPIO_PXPENC(5));
jz4780_clk_ungate_uart(0);
/* UART 1 and 2 */
jz4780_clk_ungate_uart(1);
jz4780_clk_ungate_uart(2);
#ifndef CONFIG_JTAG
/* UART3 */
writel(1 << 12, gpio_regs + GPIO_PXINTC(3));
writel(1 << 12, gpio_regs + GPIO_PXMASKS(3));
writel(1 << 12, gpio_regs + GPIO_PXPAT1S(3));
writel(1 << 12, gpio_regs + GPIO_PXPAT0C(3));
writel(3 << 30, gpio_regs + GPIO_PXINTC(0));
writel(3 << 30, gpio_regs + GPIO_PXMASKC(0));
writel(3 << 30, gpio_regs + GPIO_PXPAT1C(0));
writel(1 << 30, gpio_regs + GPIO_PXPAT0C(0));
writel(1 << 31, gpio_regs + GPIO_PXPAT0S(0));
jz4780_clk_ungate_uart(3);
#endif
/* UART4 */
writel(0x100400, gpio_regs + GPIO_PXINTC(2));
writel(0x100400, gpio_regs + GPIO_PXMASKC(2));
writel(0x100400, gpio_regs + GPIO_PXPAT1S(2));
writel(0x100400, gpio_regs + GPIO_PXPAT0C(2));
writel(0x100400, gpio_regs + GPIO_PXPENC(2));
jz4780_clk_ungate_uart(4);
}
int board_early_init_f(void)
{
ci20_mux_jtag();
ci20_mux_uart();
ci20_mux_eth();
ci20_mux_mmc();
ci20_mux_nand();
/* SYS_POWER_IND high (LED blue, VBUS off) */
jz47xx_gpio_direction_output(JZ_GPIO(5, 15), 0);
/* LEDs off */
jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0);
jz47xx_gpio_direction_output(JZ_GPIO(2, 1), 0);
jz47xx_gpio_direction_output(JZ_GPIO(2, 2), 0);
jz47xx_gpio_direction_output(JZ_GPIO(2, 3), 0);
return 0;
}
int misc_init_r(void)
{
const u32 efuse_clk = jz4780_clk_get_efuse_clk();
struct ci20_otp otp;
char manufacturer[3];
/* Read the board OTP data */
jz4780_efuse_init(efuse_clk);
jz4780_efuse_read(0x18, 16, (u8 *)&otp);
/* Set MAC address */
if (!is_valid_ethaddr(otp.mac)) {
/* no MAC assigned, generate one from the unique chip ID */
jz4780_efuse_read(0x8, 4, &otp.mac[0]);
jz4780_efuse_read(0x12, 2, &otp.mac[4]);
otp.mac[0] = (otp.mac[0] | 0x02) & ~0x01;
}
eth_env_set_enetaddr("ethaddr", otp.mac);
/* Put other board information into the environment */
env_set_ulong("serial#", otp.serial_number);
env_set_ulong("board_date", otp.date);
manufacturer[0] = otp.manufacturer[0];
manufacturer[1] = otp.manufacturer[1];
manufacturer[2] = 0;
env_set("board_mfr", manufacturer);
return 0;
}
#ifdef CONFIG_DRIVER_DM9000
int board_eth_init(bd_t *bis)
{
/* Enable clock */
jz4780_clk_ungate_ethernet();
/* Enable power (PB25) */
jz47xx_gpio_direction_output(JZ_GPIO(1, 25), 1);
/* Reset (PF12) */
mdelay(10);
jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 0);
mdelay(10);
jz47xx_gpio_direction_output(JZ_GPIO(5, 12), 1);
mdelay(10);
return dm9000_initialize(bis);
}
#endif /* CONFIG_DRIVER_DM9000 */
#endif
static u8 ci20_revision(void)
{
void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
int val;
jz47xx_gpio_direction_input(JZ_GPIO(2, 18));
jz47xx_gpio_direction_input(JZ_GPIO(2, 19));
/* Enable pullups */
writel(BIT(18) | BIT(19), gpio_regs + GPIO_PXPENC(2));
/* Read PC18/19 for version */
val = (!!jz47xx_gpio_get_value(JZ_GPIO(2, 18))) |
((!!jz47xx_gpio_get_value(JZ_GPIO(2, 19))) << 1);
if (val == 3) /* Rev 1 boards had no pulldowns - giving 3 */
return 1;
if (val == 1) /* Rev 2 boards pulldown port C bit 18 giving 1 */
return 2;
return 0;
}
int dram_init(void)
{
gd->ram_size = sdram_size(0) + sdram_size(1);
return 0;
}
/* U-Boot common routines */
int checkboard(void)
{
printf("Board: Creator CI20 (rev.%d)\n", ci20_revision());
return 0;
}
#ifdef CONFIG_SPL_BUILD
#if defined(CONFIG_SPL_MMC_SUPPORT)
int board_mmc_init(bd_t *bd)
{
ci20_mux_mmc();
return jz_mmc_init((void __iomem *)MSC0_BASE);
}
#endif
static const struct jz4780_ddr_config K4B2G0846Q_48_config = {
.timing = {
(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
(4 << DDRC_TIMING2_TCCD_BIT) | (15 << DDRC_TIMING2_TRAS_BIT) |
(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
(21 << DDRC_TIMING3_TRC_BIT),
(31 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
(4 << DDRC_TIMING4_TCKE_BIT) | (9 << DDRC_TIMING4_TMINSR_BIT) |
(8 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
(4 << DDRC_TIMING5_TWDLAT_BIT),
(25 << DDRC_TIMING6_TXSRD_BIT) | (12 << DDRC_TIMING6_TFAW_BIT) |
(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
},
/* PHY */
/* Mode Register 0 */
.mr0 = 0x420,
#ifdef SDRAM_DISABLE_DLL
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
#else
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
#endif
.ptr0 = 0x002000d4,
.ptr1 = 0x02230d40,
.ptr2 = 0x04013880,
.dtpr0 = 0x2a8f6690,
.dtpr1 = 0x00400860,
.dtpr2 = 0x10042a00,
.pullup = 0x0b,
.pulldn = 0x0b,
};
static const struct jz4780_ddr_config H5TQ2G83CFR_48_config = {
.timing = {
(4 << DDRC_TIMING1_TRTP_BIT) | (13 << DDRC_TIMING1_TWTR_BIT) |
(6 << DDRC_TIMING1_TWR_BIT) | (5 << DDRC_TIMING1_TWL_BIT),
(4 << DDRC_TIMING2_TCCD_BIT) | (16 << DDRC_TIMING2_TRAS_BIT) |
(6 << DDRC_TIMING2_TRCD_BIT) | (6 << DDRC_TIMING2_TRL_BIT),
(4 << DDRC_TIMING3_ONUM) | (7 << DDRC_TIMING3_TCKSRE_BIT) |
(6 << DDRC_TIMING3_TRP_BIT) | (4 << DDRC_TIMING3_TRRD_BIT) |
(22 << DDRC_TIMING3_TRC_BIT),
(42 << DDRC_TIMING4_TRFC_BIT) | (1 << DDRC_TIMING4_TRWCOV_BIT) |
(4 << DDRC_TIMING4_TCKE_BIT) | (7 << DDRC_TIMING4_TMINSR_BIT) |
(3 << DDRC_TIMING4_TXP_BIT) | (3 << DDRC_TIMING4_TMRD_BIT),
(8 << DDRC_TIMING5_TRTW_BIT) | (4 << DDRC_TIMING5_TRDLAT_BIT) |
(4 << DDRC_TIMING5_TWDLAT_BIT),
(25 << DDRC_TIMING6_TXSRD_BIT) | (20 << DDRC_TIMING6_TFAW_BIT) |
(2 << DDRC_TIMING6_TCFGW_BIT) | (2 << DDRC_TIMING6_TCFGR_BIT),
},
/* PHY */
/* Mode Register 0 */
.mr0 = 0x420,
#ifdef SDRAM_DISABLE_DLL
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
#else
.mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
#endif
.ptr0 = 0x002000d4,
.ptr1 = 0x02d30d40,
.ptr2 = 0x04013880,
.dtpr0 = 0x2c906690,
.dtpr1 = 0x005608a0,
.dtpr2 = 0x10042a00,
.pullup = 0x0e,
.pulldn = 0x0e,
};
#if (CONFIG_SYS_MHZ != 1200)
#error No DDR configuration for CPU speed
#endif
const struct jz4780_ddr_config *jz4780_get_ddr_config(void)
{
const int board_revision = ci20_revision();
if (board_revision == 2)
return &K4B2G0846Q_48_config;
else /* Fall back to H5TQ2G83CFR RAM */
return &H5TQ2G83CFR_48_config;
}
#endif

48
configs/ci20_mmc_defconfig Normal file
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@ -0,0 +1,48 @@
CONFIG_MIPS=y
CONFIG_SPL_LDSCRIPT="arch/mips/mach-jz47xx/jz4780/u-boot-spl.lds"
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL=y
CONFIG_ARCH_JZ47XX=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_FIT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1"
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="ext4load mmc 0:1 0x88000000 /boot/uImage; bootm 0x88000000"
CONFIG_MISC_INIT_R=y
CONFIG_DISPLAY_CPUINFO=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_BANNER_PRINT is not set
# CONFIG_TPL_BANNER_PRINT is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DM=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_FAT=y
# CONFIG_SPL_DOS_PARTITION is not set
CONFIG_DEFAULT_DEVICE_TREE="ci20"
CONFIG_ENV_IS_IN_MMC=y
# CONFIG_DM_WARN is not set
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_JZ4780_EFUSE=y
CONFIG_MMC=y
CONFIG_MMC_BROKEN_CD=y
CONFIG_DM_MMC=y
# CONFIG_MMC_HW_PARTITIONING is not set
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
# CONFIG_MMC_VERBOSE is not set
CONFIG_SPL_MMC_TINY=y
CONFIG_JZ47XX_MMC=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_LZO=y

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include/configs/ci20.h Normal file
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@ -0,0 +1,72 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* CI20 configuration
*
* Copyright (c) 2013 Imagination Technologies
* Author: Paul Burton <paul.burton@imgtec.com>
*/
#ifndef __CONFIG_CI20_H__
#define __CONFIG_CI20_H__
#define CONFIG_SKIP_LOWLEVEL_INIT
/* Ingenic JZ4780 clock configuration. */
#define CONFIG_SYS_HZ 1000
#define CONFIG_SYS_MHZ 1200
#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Memory configuration */
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */
#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x88000000
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
/* NS16550-ish UARTs */
#define CONFIG_SYS_NS16550_CLK 48000000
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
/* Ethernet: davicom DM9000 */
#define CONFIG_DRIVER_DM9000 1
#define CONFIG_DM9000_BASE 0xb6000000
#define DM9000_IO CONFIG_DM9000_BASE
#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
/* Environment */
#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_ENV_SIZE (32 << 10)
#define CONFIG_ENV_OFFSET ((14 + 512) << 10)
#define CONFIG_ENV_OVERWRITE
/* Command line configuration. */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
/* Boot argument buffer size */
#define CONFIG_VERSION_VARIABLE /* U-BOOT version */
/* Miscellaneous configuration options */
#define CONFIG_SYS_BOOTM_LEN (64 << 20)
/* SPL */
#define CONFIG_SPL_STACK 0xf4008000 /* only max. 2KB spare! */
#define CONFIG_SPL_TEXT_BASE 0xf4000a00
#define CONFIG_SPL_MAX_SIZE ((14 * 1024) - 0xa00)
#define CONFIG_SPL_BSS_START_ADDR 0xf4004000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00002000 /* 512KB, arbitrary */
#define CONFIG_SPL_START_S_PATH "arch/mips/mach-jz47xx"
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1c /* 14 KiB offset */
#endif /* __CONFIG_CI20_H__ */