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arm: Remove unused mx27 code

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We no longer have any i.MX27 platforms, remove the remaining support
code.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-11-19 18:45:27 -05:00
parent 4982e123b2
commit 2568bd6db7
13 changed files with 9 additions and 825 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/cpu/arm926ejs/Makefile
View File

@ -12,7 +12,6 @@ extra-y :=
endif
endif
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
obj-$(CONFIG_ARCH_SUNXI) += sunxi/

7
arch/arm/cpu/arm926ejs/mx27/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

378
arch/arm/cpu/arm926ejs/mx27/generic.c
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@ -1,378 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/mach-imx/sys_proto.h>
#ifdef CONFIG_MMC_MXC
#include <asm/arch/mxcmmc.h>
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> 10) & 0xf;
unsigned int mfn = pll & 0x3ff;
unsigned int mfd = (pll >> 16) & 0x3ff;
unsigned int pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
(mfd + 1) * (pd + 1));
}
static ulong clk_in_32k(void)
{
return 1024 * CONFIG_MX27_CLK32;
}
static ulong clk_in_26m(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
/* divide by 1.5 */
return 26000000 * 2 / 3;
} else {
return 26000000;
}
}
static ulong imx_get_mpllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_MCU_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->mpctl0), fref);
}
static ulong imx_get_armclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
if (!(cscr & CSCR_ARM_SRC_MPLL))
fref = lldiv((fref * 2), 3);
div = ((cscr >> 12) & 0x3) + 1;
return lldiv(fref, div);
}
static ulong imx_get_ahbclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref = imx_get_mpllclk();
ulong div;
div = ((cscr >> 8) & 0x3) + 1;
return lldiv(fref * 2, 3 * div);
}
static __attribute__((unused)) ulong imx_get_spllclk(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
ulong cscr = readl(&pll->cscr);
ulong fref;
if (cscr & CSCR_SP_SEL)
fref = clk_in_26m();
else
fref = clk_in_32k();
return imx_decode_pll(readl(&pll->spctl0), fref);
}
static ulong imx_decode_perclk(ulong div)
{
return lldiv((imx_get_mpllclk() * 2), (div * 3));
}
static ulong imx_get_perclk1(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
}
static ulong imx_get_perclk2(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk3(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
}
static __attribute__((unused)) ulong imx_get_perclk4(void)
{
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_I2C_CLK:
return imx_get_ahbclk()/2;
case MXC_UART_CLK:
return imx_get_perclk1();
case MXC_FEC_CLK:
return imx_get_ahbclk();
case MXC_ESDHC_CLK:
return imx_get_perclk2();
}
return -1;
}
u32 get_cpu_rev(void)
{
return MXC_CPU_MX27 << 12;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo (void)
{
char buf[32];
printf("CPU: Freescale i.MX27 at %s MHz\n\n",
strmhz(buf, imx_get_mpllclk()));
return 0;
}
#endif
int cpu_eth_init(struct bd_info *bis)
{
#if defined(CONFIG_FEC_MXC)
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* enable FEC clock */
writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
return fecmxc_initialize(bis);
#else
return 0;
#endif
}
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
#ifdef CONFIG_MMC_MXC
return mxc_mmc_init(bis);
#else
return 0;
#endif
}
void imx_gpio_mode(int gpio_mode)
{
struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
unsigned int pin = gpio_mode & GPIO_PIN_MASK;
unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
unsigned int tmp;
/* Pullup enable */
if (gpio_mode & GPIO_PUEN) {
writel(readl(&regs->port[port].puen) | (1 << pin),
&regs->port[port].puen);
} else {
writel(readl(&regs->port[port].puen) & ~(1 << pin),
&regs->port[port].puen);
}
/* Data direction */
if (gpio_mode & GPIO_OUT) {
writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
&regs->port[port].gpio_dir);
} else {
writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
&regs->port[port].gpio_dir);
}
/* Primary / alternate function */
if (gpio_mode & GPIO_AF) {
writel(readl(&regs->port[port].gpr) | (1 << pin),
&regs->port[port].gpr);
} else {
writel(readl(&regs->port[port].gpr) & ~(1 << pin),
&regs->port[port].gpr);
}
/* use as gpio? */
if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
writel(readl(&regs->port[port].gius) | (1 << pin),
&regs->port[port].gius);
} else {
writel(readl(&regs->port[port].gius) & ~(1 << pin),
&regs->port[port].gius);
}
/* Output / input configuration */
if (pin < 16) {
tmp = readl(&regs->port[port].ocr1);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr1);
writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
&regs->port[port].iconfa1);
writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
&regs->port[port].iconfb1);
writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
&regs->port[port].iconfb1);
} else {
pin -= 16;
tmp = readl(&regs->port[port].ocr2);
tmp &= ~(3 << (pin * 2));
tmp |= (ocr << (pin * 2));
writel(tmp, &regs->port[port].ocr2);
writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
&regs->port[port].iconfa2);
writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
&regs->port[port].iconfb2);
writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
&regs->port[port].iconfb2);
}
}
#ifdef CONFIG_MXC_UART
void mx27_uart1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MXC_UART */
#ifdef CONFIG_FEC_MXC
void mx27_fec_init_pins(void)
{
int i;
unsigned int mode[] = {
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC | GPIO_PUEN,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_CLR,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */
#ifdef CONFIG_MMC_MXC
void mx27_sd1_init_pins(void)
{
int i;
unsigned int mode[] = {
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
void mx27_sd2_init_pins(void)
{
int i;
unsigned int mode[] = {
PB4_PF_SD2_D0,
PB5_PF_SD2_D1,
PB6_PF_SD2_D2,
PB7_PF_SD2_D3,
PB8_PF_SD2_CMD,
PB9_PF_SD2_CLK,
};
for (i = 0; i < ARRAY_SIZE(mode); i++)
imx_gpio_mode(mode[i]);
}
#endif /* CONFIG_MMC_MXC */

50
arch/arm/cpu/arm926ejs/mx27/relocate.S
View File

@ -1,50 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX27-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <asm-offsets.h>
#include <config.h>
#include <linux/linkage.h>
/*
* The i.MX27 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM. Therefore, vectors cannot be changed at all.
*
* However, these ROM-based vectors actually just perform indirect
* calls through pointers located in RAM at SoC-specific addresses,
* as follows:
*
* Offset Exception Use by ROM code
* 0x00000000 reset indirect branch to [0x00000014]
* 0x00000004 undefined instruction indirect branch to [0xfffffef0]
* 0x00000008 software interrupt indirect branch to [0xfffffef4]
* 0x0000000c prefetch abort indirect branch to [0xfffffef8]
* 0x00000010 data abort indirect branch to [0xfffffefc]
* 0x00000014 (reserved in ARMv5) vector to ROM reset: 0xc0000000
* 0x00000018 IRQ indirect branch to [0xffffff00]
* 0x0000001c FIQ indirect branch to [0xffffff04]
*
* In order to initialize exceptions on i.MX27, we must copy U-Boot's
* indirect (not exception!) vector table into 0xfffffef0..0xffffff04
* taking care not to copy vectors number 5 (reserved exception).
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
ldr r0, [r9, #GD_RELOCADDR] /* r0 = gd->relocaddr */
ldr r1, =32 /* size of vector table */
add r0, r0, r1 /* skip to indirect table */
ldr r1, =0xFFFFFEF0 /* i.MX27 indirect table */
ldmia r0!, {r2-r8} /* load indirect vectors 1..7 */
stmia r1!, {r2-r5, r7,r8} /* write all but vector 5 */
bx lr
ENDPROC(relocate_vectors)

41
arch/arm/cpu/arm926ejs/mx27/reset.c
View File

@ -1,41 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0x0000, &regs->wcr);
/* Write Service Sequence */
writew(0x5555, &regs->wsr);
writew(0xAAAA, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1);
/*NOTREACHED*/
}

166
arch/arm/cpu/arm926ejs/mx27/timer.c
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@ -1,166 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <div64.h>
#include <init.h>
#include <time.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
#include <linux/delay.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1 << 15) /* Software reset */
#define GPTCR_FRR (1 << 8) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 1) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
DECLARE_GLOBAL_DATA_PTR;
#define timestamp (gd->arch.tbl)
#define lastinc (gd->arch.lastinc)
/*
* "time" is measured in 1 / CONFIG_SYS_HZ seconds,
* "tick" is internal timer period
*/
#ifdef CONFIG_MX27_TIMER_HIGH_PRECISION
/* ~0.4% error - measured with stop-watch on 100s boot-delay */
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, CONFIG_MX27_CLK32);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
time *= CONFIG_MX27_CLK32;
do_div(time, CONFIG_SYS_HZ);
return time;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us = us * CONFIG_MX27_CLK32 + 999999;
do_div(us, 1000000);
return us;
}
#else
/* ~2% error */
#define TICK_PER_TIME ((CONFIG_MX27_CLK32 + CONFIG_SYS_HZ / 2) / \
CONFIG_SYS_HZ)
#define US_PER_TICK (1000000 / CONFIG_MX27_CLK32)
static inline unsigned long long tick_to_time(unsigned long long tick)
{
do_div(tick, TICK_PER_TIME);
return tick;
}
static inline unsigned long long time_to_tick(unsigned long long time)
{
return time * TICK_PER_TIME;
}
static inline unsigned long long us_to_tick(unsigned long long us)
{
us += US_PER_TICK - 1;
do_div(us, US_PER_TICK);
return us;
}
#endif
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32768Hz 32-bit timer overruns in 131072 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &regs->gpt_tctl);
writel(readl(&pll->pccr0) | PCCR0_GPT1_EN, &pll->pccr0);
writel(readl(&pll->pccr1) | PCCR1_PERCLK1_EN, &pll->pccr1);
for (i = 0; i < 100; i++)
writel(0, &regs->gpt_tctl); /* We have no udelay by now */
writel(0, &regs->gpt_tprer); /* 32Khz */
/* Freerun Mode, PERCLK1 input */
writel(readl(&regs->gpt_tctl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&regs->gpt_tctl);
writel(readl(&regs->gpt_tctl) | GPTCR_TEN, &regs->gpt_tctl);
return 0;
}
unsigned long long get_ticks(void)
{
struct gpt_regs *regs = (struct gpt_regs *)IMX_TIM1_BASE;
ulong now = readl(&regs->gpt_tcn); /* current tick value */
if (now >= lastinc) {
/*
* normal mode (non roll)
* move stamp forward with absolut diff ticks
*/
timestamp += (now - lastinc);
} else {
/* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
}
lastinc = now;
return timestamp;
}
static ulong get_timer_masked(void)
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
* 2^64 / CONFIG_MX27_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
return tick_to_time(get_ticks());
}
ulong get_timer(ulong base)
{
return get_timer_masked() - base;
}
/* delay x useconds AND preserve advance timstamp value */
void __udelay(unsigned long usec)
{
unsigned long long tmp;
ulong tmo;
tmo = us_to_tick(usec);
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
}
ulong get_tbclk(void)
{
return CONFIG_MX27_CLK32;
}

29
arch/arm/lib/asm-offsets.c
View File

@ -15,8 +15,7 @@
#include <linux/kbuild.h>
#include <linux/arm-smccc.h>
#if defined(CONFIG_MX27) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53)
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
@ -35,32 +34,6 @@ int main(void)
* code. Is it better to define the macros directly in headers?
*/
#if defined(CONFIG_MX27)
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI2_PSR1, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr1));
DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr));
DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0));
DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0));
DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0));
DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
DEFINE(ESDCTL1_ROF, offsetof(struct esdramc_regs, esdctl1));
DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
DEFINE(GPCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, gpcr));
DEFINE(FMCR, IMX_SYSTEM_CTL_BASE +
offsetof(struct system_control_regs, fmcr));
#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));

12
drivers/gpio/mxc_gpio.c
View File

@ -44,13 +44,13 @@ static unsigned long gpio_ports[] = {
[0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
#if defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
[3] = GPIO4_BASE_ADDR,
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
[4] = GPIO5_BASE_ADDR,
@ -352,12 +352,12 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
#if defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 4, (struct gpio_regs *)GPIO5_BASE_ADDR },
#ifndef CONFIG_IMX8M
@ -376,12 +376,12 @@ U_BOOT_DRVINFOS(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[0] },
{ "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
#if defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] },
#endif
#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[4] },
#ifndef CONFIG_IMX8M

3
drivers/mtd/nand/raw/mxc_nand.c
View File

@ -12,8 +12,7 @@
#include <linux/err.h>
#include <linux/mtd/rawnand.h>
#include <asm/io.h>
#if defined(CONFIG_MX27) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53)
#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h>
#endif
#include "mxc_nand.h"

2
drivers/mtd/nand/raw/mxc_nand.h
View File

@ -24,7 +24,7 @@
* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
* Also some of registers are moved and/or changed meaning as seen below.
*/
#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
#if defined(CONFIG_MX31)
#define MXC_NFC_V1
#define is_mxc_nfc_1() 1
#define is_mxc_nfc_21() 0

3
drivers/net/fec_mxc.c
View File

@ -251,9 +251,6 @@ static int miiphy_restart_aneg(struct eth_device *dev)
* Wake up from sleep if necessary
* Reset PHY, then delay 300ns
*/
#ifdef CONFIG_MX27
fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
#endif
fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
udelay(1000);

8
drivers/spi/mxc_spi.c
View File

@ -91,14 +91,6 @@ struct cspi_regs {
#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
#endif
#ifdef CONFIG_MX27
/* i.MX27 has a completely wrong register layout and register definitions in the
* datasheet, the correct one is in the Freescale's Linux driver */
#error "i.MX27 CSPI not supported due to drastic differences in register definitions" \
"See linux mxc_spi driver from Freescale for details."
#endif
__weak int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
return -1;

134
include/configs/imx27lite-common.h
View File

@ -1,134 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2010 Heiko Schocher <hs@denx.de>
*
* based on:
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#ifndef __IMX27LITE_COMMON_CONFIG_H
#define __IMX27LITE_COMMON_CONFIG_H
/*
* SoC Configuration
*/
#define CONFIG_MX27
#define CONFIG_MX27_CLK32 32768 /* OSC32K frequency */
/*
* Lowlevel configuration
*/
#define SDRAM_ESDCFG_REGISTER_VAL(cas) \
(ESDCFG_TRC(10) | \
ESDCFG_TRCD(3) | \
ESDCFG_TCAS(cas) | \
ESDCFG_TRRD(1) | \
ESDCFG_TRAS(5) | \
ESDCFG_TWR | \
ESDCFG_TMRD(2) | \
ESDCFG_TRP(2) | \
ESDCFG_TXP(3))
#define SDRAM_ESDCTL_REGISTER_VAL \
(ESDCTL_PRCT(0) | \
ESDCTL_BL | \
ESDCTL_PWDT(0) | \
ESDCTL_SREFR(3) | \
ESDCTL_DSIZ_32 | \
ESDCTL_COL10 | \
ESDCTL_ROW13 | \
ESDCTL_SDE)
#define SDRAM_ALL_VAL 0xf00
#define SDRAM_MODE_REGISTER_VAL 0x33 /* BL: 8, CAS: 3 */
#define SDRAM_EXT_MODE_REGISTER_VAL 0x1000000
#define MPCTL0_VAL 0x1ef15d5
#define SPCTL0_VAL 0x043a1c09
#define CSCR_VAL 0x33f08107
#define PCDR0_VAL 0x120470c3
#define PCDR1_VAL 0x03030303
#define PCCR0_VAL 0xffffffff
#define PCCR1_VAL 0xfffffffc
#define AIPI1_PSR0_VAL 0x20040304
#define AIPI1_PSR1_VAL 0xdffbfcfb
#define AIPI2_PSR0_VAL 0x07ffc200
#define AIPI2_PSR1_VAL 0xffffffff
/*
* Memory Info
*/
/* memtest start address */
#define PHYS_SDRAM_1 0xA0000000 /* DDR Start */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */
/*
* Serial Driver info
*/
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
/*
* Flash & Environment
*/
/* Use buffered writes (~10x faster) */
/* Use hardware sector protection */
/* CS2 Base address */
#define PHYS_FLASH_1 0xc0000000
/* Flash Base for U-Boot */
#define CFG_SYS_FLASH_BASE PHYS_FLASH_1
/* Address and size of Redundant Environment Sector */
/*
* Ethernet
*/
#define CONFIG_FEC_MXC_PHYADDR 0x1f
/*
* MTD
*/
/*
* NAND
*/
#define CONFIG_MXC_NAND_REGS_BASE 0xd8000000
#define CFG_SYS_NAND_BASE 0xd8000000
#define CONFIG_MXC_NAND_HWECC
/*
* U-Boot general configuration
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
"kernel_addr_r=a0800000\0" \
"bootfile=" CONFIG_HOSTNAME "/uImage\0" \
"rootpath=/opt/eldk-4.2-arm/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
"bootcmd=run net_nfs\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
/* additions for new relocation code, must be added to all boards */
#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
#endif /* __IMX27LITE_COMMON_CONFIG_H */