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* Patch by Martin Krause, 17 Jul 2003:

Browse Source 
add delay to get I2C working with "imm" command and s3c24x0_i2c.c

* Patch by Richard Woodruff, 17 July 03:
  - Fixed bug in OMAP1510 baud rate divisor settings.

* Patch by Nye Liu, 16 July 2003:
  MPC860FADS fixes:
  - add MPC86xADS support (uses MPC86xADS.h)
  - add 866P/T core support (also MPC859T/MPC859DSL/MPC852T)
    o PLPRCR changes
    o BRG changes (EXTAL/XTAL restricted to 10MHz)
    o don't trust gclk() software measurement by default, depend on
      CONFIG_8xx_GCLK_FREQ
  - add DRAM SIMM not installed detection
  - use more "correct" SDRAM initialization sequence
  - allow different SDRAM sizes (8xxADS has 8M)
  - default DER is 0
  - remove unused MAMR defines from FADS860T.h (all done in fads.c)
  - rename MAMR/MBMR defines to be more consistent. Should eventually
    be merged into MxMR to better reflect the PowerQUICC datasheet.

* Patch by Yuli Barcohen, 16 Jul 2003:
  support new Motorola PQ2FADS-ZU evaluation board which replaced
  MPC8260ADS and MPC8266ADS
This commit is contained in:
wdenk
2003-07-17 23:16:40 +00:00
parent 945af8d723
commit 2535d60277
47 changed files with 1466 additions and 710 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
board/eltec/mhpc/mhpc.c
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@@ -254,7 +254,7 @@ long int initdram (int board_type)
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mbmr = MAMR_GPL_B4DIS;
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* should this be mamr? - NTL */
memctl->memc_mptpr = MPTPR_PTP_DIV64;
memctl->memc_mar = 0x00008800;

863
board/fads/fads.c
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File diff suppressed because it is too large Load Diff

4
board/flagadm/flagadm.c
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@@ -128,7 +128,7 @@ long int initdram (int board_type)
/* That should do it, just enable the periodic refresh in burst of 4*/
memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_B4DIS);
memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
size_b0 = 16*1024*1024;
@@ -141,7 +141,7 @@ long int initdram (int board_type)
upmconfig(UPMB, (uint *)dsp_disp_table, sizeof(dsp_disp_table)/sizeof(uint));
memctl->memc_mbmr = MAMR_GPL_B4DIS;
memctl->memc_mbmr = MBMR_GPL_B4DIS;
memctl->memc_or4 = CFG_OR4;
memctl->memc_br4 = CFG_BR4;

2
board/genietv/genietv.c
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@@ -163,7 +163,7 @@ long int initdram (int board_type)
memctl->memc_mcr = 0x80804105; /* SDRAM bank 1 */
/* Execute refresh 8 times */
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MAMR_TLFB_MSK) | MAMR_TLFB_8X ;
memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X ;
memctl->memc_mcr = 0x80802130; /* SDRAM bank 0 - execute twice */

2
board/gth/gth.c
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@@ -218,7 +218,7 @@ int _initsdram (uint base, uint * noMbytes)
sizeof (fpga_table) / sizeof (uint));
/* Enable UPWAITB */
mc->memc_mbmr = MAMR_GPL_B4DIS; /* (16-13) */
mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */
/* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */
mc->memc_or2 = 0xffc00000 | OR_BI;

4
board/ivm/ivm.c
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@@ -246,14 +246,14 @@ initdram (int board_type)
udelay(1);
memctl->memc_mcr = 0x80806130; /* autorefresh */
memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
return (size_b0);
}

4
board/lantec/lantec.c
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@@ -149,7 +149,7 @@ long int initdram (int board_type)
udelay(1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF(1) | MCR_MAD(0x06);
memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
udelay(200);
@@ -170,7 +170,7 @@ long int initdram (int board_type)
(ulong *)SDRAM_BASE3_PRELIM,
SDRAM_MAX_SIZE);
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
/*
* Final mapping:

6
board/lwmon/lwmon.c
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@@ -246,7 +246,7 @@ long int initdram (int board_type)
udelay (1); /* 0x80006106 */
memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);
memctl->memc_mamr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mamr |= MAMR_PTAE; /* refresh enabled */
udelay (200);
@@ -276,11 +276,11 @@ long int initdram (int board_type)
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
udelay (500);
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
udelay (500);
}

68
board/mpc8260ads/mpc8260ads.c
View File

@@ -198,11 +198,19 @@ void reset_phy (void)
vu_long *bcsr = (vu_long *)CFG_BCSR;
/* reset the FEC port */
bcsr[1] &= ~FETH_RST;
bcsr[1] &= ~FETH1_RST;
udelay(2);
bcsr[1] |= FETH_RST;
bcsr[1] |= FETH1_RST;
udelay(1000);
#ifdef CONFIG_MII
#if CONFIG_ADSTYPE == CFG_PQ2FADS
/*
* Do not bypass Rx/Tx (de)scrambler (fix configuration error)
* Enable autonegotiation.
*/
miiphy_write(0, 16, 0x610);
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#else
/*
* Ethernet PHY is configured (by means of configuration pins)
* to work at 10Mb/s only. We reconfigure it using MII
@@ -212,6 +220,7 @@ void reset_phy (void)
miiphy_write(0, PHY_ANAR, 0x01E1); /* Advertise all capabilities */
miiphy_write(0, PHY_DCR, 0x0000); /* Do not bypass Rx/Tx (de)scrambler */
miiphy_write(0, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
#endif /* CONFIG_MII */
}
@@ -219,7 +228,7 @@ int board_pre_init (void)
{
vu_long *bcsr = (vu_long *)CFG_BCSR;
bcsr[1] = ~FETHIEN & ~RS232EN_1;
bcsr[1] = ~FETHIEN1 & ~RS232EN_1;
return 0;
}
@@ -231,12 +240,10 @@ long int initdram (int board_type)
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar *ramaddr, c = 0xff;
/* Initialisation is for 16MB DIMM the board is shipped with */
long int msize = 16;
uint or = 0xFF000CA0;
uint psdmr = CFG_PSDMR;
uint psrt = CFG_PSRT;
long int msize;
uint or;
uint psdmr;
uint psrt;
int i;
@@ -246,22 +253,29 @@ long int initdram (int board_type)
immap->im_siu_conf.sc_tescr1 = 0x00004000;
memctl->memc_mptpr = CFG_MPTPR;
/* init local sdram, bank 4 */
memctl->memc_lsrt = 0x00000010;
#ifdef CFG_LSDRAM_BASE
/* Init local bus SDRAM */
memctl->memc_lsrt = CFG_LSRT;
#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
memctl->memc_or3 = 0xFF803280;
memctl->memc_br3 = CFG_LSDRAM_BASE | 0x00001861;
#else /* CS4 */
memctl->memc_or4 = 0xFFC01480;
memctl->memc_br4 = 0x04001861;
memctl->memc_lsdmr = 0x2886A522;
memctl->memc_br4 = CFG_LSDRAM_BASE | 0x00001861;
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
ramaddr = (uchar *) CFG_LSDRAM_BASE;
*ramaddr = c;
memctl->memc_lsdmr = 0x0886A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
for (i = 0; i < 8; i++) {
*ramaddr = c;
}
memctl->memc_lsdmr = 0x1886A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
*ramaddr = c;
memctl->memc_lsdmr = 0x4086A522;
memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
#endif /* CFG_LSDRAM_BASE */
/* init sdram dimm */
/* Init 60x bus SDRAM */
#ifdef CONFIG_SPD_EEPROM
{
spd_eeprom_t spd;
@@ -398,6 +412,16 @@ long int initdram (int board_type)
printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
#endif /* SPD_DEBUG */
}
#else /* !CONFIG_SPD_EEPROM */
#if CONFIG_ADSTYPE == CFG_PQ2FADS
msize = 32;
or = 0xFE002EC0;
#else
msize = 16;
or = 0xFF000CA0;
#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
psdmr = CFG_PSDMR;
psrt = CFG_PSRT;
#endif /* CONFIG_SPD_EEPROM */
memctl->memc_psrt = psrt;
memctl->memc_or2 = or;
@@ -415,12 +439,20 @@ long int initdram (int board_type)
*ramaddr = c;
#endif
/* return total ram size of DIMM */
/* return total 60x bus SDRAM size */
return (msize * 1024 * 1024);
}
int checkboard (void)
{
#if CONFIG_ADSTYPE == CFG_8260ADS
puts ("Board: Motorola MPC8260ADS\n");
#elif CONFIG_ADSTYPE == CFG_8266ADS
puts ("Board: Motorola MPC8266ADS\n");
#elif CONFIG_ADSTYPE == CFG_PQ2FADS
puts ("Board: Motorola PQ2FADS-ZU\n");
#else
puts ("Board: unknown\n");
#endif
return 0;
}

2
board/mvs1/u-boot.lds
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@@ -57,7 +57,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
cpu/mpc8xx/speed.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
@@ -67,7 +66,6 @@ SECTIONS
lib_generic/string.o (.text)
lib_ppc/extable.o (.text)
lib_ppc/kgdb.o (.text)
/* lib_ppc/ticks.o (.text) */
. = env_offset;
common/environment.o(.text)

2
board/r360mpi/r360mpi.c
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@@ -205,7 +205,7 @@ long int initdram (int board_type)
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 works as UPWAITB */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;

2
board/siemens/CCM/ccm.c
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@@ -267,7 +267,7 @@ void can_driver_enable (void)
volatile memctl8xx_t *memctl = &immap->im_memctl;
/* Initialize MBMR */
memctl->memc_mbmr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;

8
board/siemens/pcu_e/pcu_e.c
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@@ -217,9 +217,9 @@ initdram (int board_type)
#endif /* XXX */
reg = memctl->memc_mamr;
reg &= ~MAMR_TLFB_MSK; /* switch timer loop ... */
reg |= MAMR_TLFB_4X; /* ... to 4x */
reg |= MAMR_PTBE; /* enable refresh */
reg &= ~MAMR_TLFA_MSK; /* switch timer loop ... */
reg |= MAMR_TLFA_4X; /* ... to 4x */
reg |= MAMR_PTAE; /* enable refresh */
memctl->memc_mamr = reg;
udelay(200);
@@ -246,7 +246,7 @@ initdram (int board_type)
size_b0 = dram_size (CFG_MAMR, (ulong *)SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
#endif /* XXX */
memctl->memc_mamr = CFG_MAMR | MAMR_PTBE;
memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
/*
* Final mapping:

4
board/spd8xx/spd8xx.c
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@@ -200,14 +200,14 @@ initdram (int board_type)
udelay(1);
memctl->memc_mcr = 0x80806106;
memctl->memc_mbmr |= MAMR_PTBE; /* refresh enabled */
memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
/*
* Check Bank 0 Memory Size for re-configuration
*/
size_b0 = dram_size (CFG_MBMR_8COL, (ulong *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
memctl->memc_mbmr = CFG_MBMR_8COL | MAMR_PTBE;
memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
return (size_b0);
}

2
board/v37/v37.c
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@@ -140,7 +140,7 @@ long int initdram (int board_type)
memctl->memc_br3 = CFG_BR3_CAN;
/* Initialize MBMR */
memctl->memc_mamr = MAMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
memctl->memc_mamr = MAMR_GPL_A4DIS; /* GPL_A4 ouput line Disable */
/* Initialize UPMB for CAN: single read */
memctl->memc_mdr = 0xFFFFC004;