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imx8mm: synchronise device tree with linux

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Synchronise device tree with linux v5.19-rc5.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
This commit is contained in:
Marcel Ziswiler 2022-07-21 15:27:40 +02:00 committed by Stefano Babic
parent 87c4601c57
commit 24a7a3c1c0
18 changed files with 723 additions and 177 deletions
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118
arch/arm/dts/imx8mm-beacon-baseboard.dtsi
View File

@ -3,6 +3,8 @@
* Copyright 2020 Compass Electronics Group, LLC
*/
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
leds {
compatible = "gpio-leds";
@ -34,6 +36,19 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pcie0_refclk_gated: pcie0-refclk-gated {
compatible = "gpio-gate-clock";
clocks = <&pcie0_refclk>;
#clock-cells = <0>;
enable-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "3v3_aud";
@ -54,6 +69,26 @@
enable-active-high;
};
reg_camera: regulator-camera {
compatible = "regulator-fixed";
regulator-name = "mipi_pwr";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
gpio = <&pca6416_1 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100000>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
regulator-name = "pci_pwr_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
enable-active-high;
gpio = <&pca6416_1 1 GPIO_ACTIVE_HIGH>;
startup-delay-us = <100000>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
@ -78,6 +113,10 @@
};
};
&csi {
status = "okay";
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
@ -101,6 +140,30 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
camera@3c {
compatible = "ovti,ov5640";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ov5640>;
reg = <0x3c>;
clocks = <&clk IMX8MM_CLK_CLKO1>;
clock-names = "xclk";
assigned-clocks = <&clk IMX8MM_CLK_CLKO1>;
assigned-clock-parents = <&clk IMX8MM_CLK_24M>;
assigned-clock-rates = <24000000>;
AVDD-supply = <&reg_camera>; /* 2.8v */
powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
port {
/* MIPI CSI-2 bus endpoint */
ov5640_to_mipi_csi2: endpoint {
remote-endpoint = <&imx8mm_mipi_csi_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&i2c4 {
@ -152,6 +215,44 @@
};
};
&mipi_csi {
status = "okay";
ports {
port@0 {
imx8mm_mipi_csi_in: endpoint {
remote-endpoint = <&ov5640_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk_gated>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk_gated>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -177,6 +278,7 @@
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MM_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
};
@ -238,6 +340,14 @@
>;
};
pinctrl_ov5640: ov5640grp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
>;
};
pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
@ -250,6 +360,12 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
@ -271,6 +387,8 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x40
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x40
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x40
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x40
>;
};

3
arch/arm/dts/imx8mm-data-modul-edm-sbc.dts
View File

@ -35,7 +35,7 @@
brightness-levels = <0 1 10 20 30 40 50 60 70 75 80 90 100>;
default-brightness-level = <7>;
enable-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
pwms = <&pwm1 0 5000000>;
pwms = <&pwm1 0 5000000 0>;
/* Disabled by default, unless display board plugged in. */
status = "disabled";
};
@ -962,6 +962,7 @@
};
&usbotg2 {
disable-over-current;
dr_mode = "host";
status = "okay";
};

4
arch/arm/dts/imx8mm-evk-u-boot.dtsi
View File

@ -105,11 +105,11 @@
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} {
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} {
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};

2
arch/arm/dts/imx8mm-evk.dts
View File

@ -48,7 +48,7 @@
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <80000000>;
spi-tx-bus-width = <4>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
};
};

207
arch/arm/dts/imx8mm-evk.dtsi
View File

@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"
@ -30,6 +31,23 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_pcie0: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0_reg>;
regulator-name = "MPCIE_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@ -42,9 +60,8 @@
};
backlight: backlight {
status = "disabled";
compatible = "pwm-backlight";
pwms = <&pwm1 0 5000000>;
pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 255>;
num-interpolated-steps = <255>;
default-brightness-level = <250>;
@ -125,6 +142,13 @@
reg = <0>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
qca,disable-smarteee;
vddio-supply = <&vddio>;
vddio: vddio-regulator {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
};
};
@ -135,120 +159,115 @@
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pca9450@25 {
reg = <0x25>;
compatible = "nxp,pca9450a";
/* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
#address-cells = <1>;
#size-cells = <0>;
pca9450,pmic-buck2-uses-i2c-dvs;
/* Run/Standby voltage */
pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>;
buck1_reg: regulator@0 {
reg = <0>;
regulator-compatible = "buck1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
buck1_reg: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
regulator-ramp-delay = <1250>;
};
buck2_reg: regulator@1 {
reg = <1>;
regulator-compatible = "buck2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
buck2_reg: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
regulator-ramp-delay = <1250>;
rohm,dvs-run-voltage = <1000000>;
rohm,dvs-idle-voltage = <900000>;
};
buck3_reg: regulator@2 {
reg = <2>;
regulator-compatible = "buck3";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
buck3_reg: BUCK3 {
// BUCK5 in datasheet
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: regulator@3 {
reg = <3>;
regulator-compatible = "buck4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
buck4_reg: BUCK4 {
// BUCK6 in datasheet
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: regulator@4 {
reg = <4>;
regulator-compatible = "buck5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
buck5_reg: BUCK5 {
// BUCK7 in datasheet
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: regulator@5 {
reg = <5>;
regulator-compatible = "buck6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
buck6_reg: BUCK6 {
// BUCK8 in datasheet
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: regulator@6 {
reg = <6>;
regulator-compatible = "ldo1";
ldo1_reg: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: regulator@7 {
reg = <7>;
regulator-compatible = "ldo2";
ldo2_reg: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: regulator@8 {
reg = <8>;
regulator-compatible = "ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: regulator@9 {
reg = <9>;
regulator-compatible = "ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5_reg: regulator@10 {
reg = <10>;
regulator-compatible = "ldo5";
ldo3_reg: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 {
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
@ -303,6 +322,30 @@
};
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,tx-deemph-gen1 = <0x2d>;
fsl,tx-deemph-gen2 = <0xf>;
clocks = <&pcie0_refclk>;
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
vpcie-supply = <&reg_pcie0>;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
@ -328,6 +371,7 @@
srp-disable;
adp-disable;
usb-role-switch;
disable-over-current;
samsung,picophy-pre-emp-curr-control = <3>;
samsung,picophy-dc-vol-level-adjust = <7>;
status = "okay";
@ -362,7 +406,7 @@
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_backlight>;
status = "disabled";
status = "okay";
};
&iomuxc {
@ -425,6 +469,19 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x61
MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x41
>;
};
pinctrl_pcie0_reg: pcie0reggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x41
>;
};
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141

1
arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
View File

@ -91,7 +91,6 @@
max-frequency = <50000000>;
bus-width = <4>;
no-1-8-v;
pm-ignore-notify;
keep-power-in-suspend;
status = "okay";
};

1
arch/arm/dts/imx8mm-icore-mx8mm-edimm2.2.dts
View File

@ -91,7 +91,6 @@
max-frequency = <50000000>;
bus-width = <4>;
no-1-8-v;
pm-ignore-notify;
keep-power-in-suspend;
status = "okay";
};

51
arch/arm/dts/imx8mm-mx8menlo.dts
View File

@ -3,7 +3,9 @@
* Copyright 2021-2022 Marek Vasut <marex@denx.de>
*/
#include "imx8mm-verdin.dts"
/dts-v1/;
#include "imx8mm-verdin.dtsi"
/ {
model = "MENLO MX8MM EMBEDDED DEVICE";
@ -37,6 +39,13 @@
pinctrl-0 = <&pinctrl_beeper>;
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
};
/* Fixed clock dedicated to SPI CAN on carrier board */
clk_xtal20: clk-xtal20 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <20000000>;
};
};
&ecspi1 {
@ -50,13 +59,11 @@
/* CAN controller on the baseboard */
canfd: can@0 {
compatible = "microchip,mcp2518fd";
clocks = <&clk20m>;
gpio-controller;
clocks = <&clk_xtal20>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
reg = <0>;
spi-max-frequency = <2000000>;
status = "okay";
};
};
@ -64,7 +71,20 @@
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_gpio1>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 4 GPIO_ACTIVE_LOW>;
status = "disabled";
status = "okay";
spidev@0 {
compatible = "menlo,m53cpld";
reg = <0>;
spi-max-frequency = <25000000>;
};
spidev@1 {
compatible = "menlo,m53cpld";
reg = <1>;
spi-max-frequency = <25000000>;
};
};
&ethphy0 {
@ -158,30 +178,20 @@
status = "okay";
};
&i2c1 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
};
&i2c2 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
&hwmon {
status = "okay";
};
&i2c3 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
status = "okay";
};
&i2c4 {
/* IMX8MM ERRATA e7805 -- I2C is limited to 384 kHz due to SoC bug */
clock-frequency = <100000>;
/* None of this is present on the SoM. */
/delete-node/ bridge@2c;
/delete-node/ hwmon@40;
/delete-node/ hdmi@48;
/delete-node/ touch@4a;
/delete-node/ hwmontemp@4f;
/delete-node/ sensor@4f;
/delete-node/ eeprom@50;
/delete-node/ eeprom@57;
};
@ -299,7 +309,6 @@
};
&uart2 {
uart-has-rtscts;
status = "okay";
};
@ -311,7 +320,7 @@
};
&usbotg1 {
dr_mode = "gadget";
dr_mode = "peripheral";
status = "okay";
};

6
arch/arm/dts/imx8mm-pinfunc.h
View File

@ -280,7 +280,7 @@
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4 0x150 0x3B8 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC 0x150 0x3B8 0x4CC 0x2 0x1
#define MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x150 0x3B8 0x4E8 0x3 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53c 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0x150 0x3B8 0x53C 0x4 0x0
#define MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x150 0x3B8 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0x154 0x3BC 0x4E0 0x0 0x0
#define MX8MM_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5 0x154 0x3BC 0x000 0x1 0x0
@ -487,7 +487,7 @@
#define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4Fc 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x4FC 0x4 0x2
#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0
@ -495,7 +495,7 @@
#define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0
#define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x000 0x4 0x0
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4Fc 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3
#define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0
#define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0
#define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0

10
arch/arm/dts/imx8mm-u-boot.dtsi
View File

@ -200,3 +200,13 @@
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&spba1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&spba2 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};

11
arch/arm/dts/imx8mm-venice-gw700x.dtsi
View File

@ -111,7 +111,8 @@
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
};
};
};
@ -277,8 +278,6 @@
pmic@69 {
compatible = "mps,mp5416";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
reg = <0x69>;
regulators {
@ -443,12 +442,6 @@
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140

56
arch/arm/dts/imx8mm-venice-gw71xx.dtsi
View File

@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
@ -33,6 +34,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
@ -57,10 +64,24 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "pci_usb_sel", "dio0",
"", "dio1", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "", "", "", "dio2", "dio3", "", "", "pci_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -87,6 +108,29 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
/* GPS */
&uart1 {
pinctrl-names = "default";
@ -103,12 +147,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
@ -148,6 +194,12 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
@ -166,7 +218,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

85
arch/arm/dts/imx8mm-venice-gw72xx.dtsi
View File

@ -5,9 +5,11 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
@ -33,6 +35,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
@ -76,10 +84,26 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpio1 {
gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
"", "", "pci_usb_sel", "dio0",
"", "dio1", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
"mipi_gpio1", "", "", "pci_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -106,6 +130,55 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
pcie@1,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
pcie@2,3 {
reg = <0x1800 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
eth1: pcie@5,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
@ -139,12 +212,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@ -198,6 +273,12 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
@ -231,7 +312,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

86
arch/arm/dts/imx8mm-venice-gw73xx.dtsi
View File

@ -5,9 +5,11 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
@ -33,6 +35,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
@ -96,10 +104,26 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
&gpio1 {
gpio-line-names = "rs485_term", "mipi_gpio4", "", "",
"", "", "pci_usb_sel", "dio0",
"", "dio1", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "rs485_en", "mipi_gpio3", "rs485_hd", "mipi_gpio2",
"mipi_gpio1", "", "", "pci_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
@ -126,6 +150,55 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 6 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
pcie@1,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
pcie@2,4 {
reg = <0x2000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
eth1: pcie@6,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
@ -149,6 +222,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>;
cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {
@ -166,12 +240,14 @@
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_usb_otg2_vbus>;
status = "okay";
};
@ -241,6 +317,12 @@
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x41
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41
@ -280,7 +362,7 @@
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6
>;
};

126
arch/arm/dts/imx8mm-venice-gw7901.dts
View File

@ -8,6 +8,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
@ -179,6 +180,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
@ -255,6 +262,10 @@
};
};
&disp_blk_ctrl {
status = "disabled";
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
@ -282,6 +293,37 @@
};
};
&gpio1 {
gpio-line-names = "uart1_rs422#", "", "", "uart1_rs485#",
"", "uart1_rs232#", "dig1_in", "dig1_out",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "", "", "", "",
"", "", "uart3_rs232#", "uart3_rs422#",
"uart3_rs485#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "uart4_rs485#", "", "sim1det#", "sim2det#", "";
};
&gpio5 {
gpio-line-names = "", "", "", "dig2_out", "dig2_in", "sim2sel", "", "",
"", "", "uart4_rs232#", "", "", "uart4_rs422#", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpu_2d {
status = "disabled";
};
&gpu_3d {
status = "disabled";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -296,8 +338,6 @@
interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
adc {
compatible = "gw,gsc-adc";
@ -577,6 +617,7 @@
pinctrl-0 = <&pinctrl_ksz>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
phy-mode = "rgmii-id";
ports {
#address-cells = <1>;
@ -586,32 +627,24 @@
reg = <0>;
label = "lan1";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&sw_phy0>;
phy-mode = "internal";
};
lan2: port@1 {
reg = <1>;
label = "lan2";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&sw_phy1>;
phy-mode = "internal";
};
lan3: port@2 {
reg = <2>;
label = "lan3";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&sw_phy2>;
phy-mode = "internal";
};
lan4: port@3 {
reg = <3>;
label = "lan4";
local-mac-address = [00 00 00 00 00 00];
phy-handle = <&sw_phy3>;
phy-mode = "internal";
};
port@5 {
@ -626,34 +659,6 @@
};
};
};
mdios {
#address-cells = <1>;
#size-cells = <0>;
mdio@0 {
reg = <0>;
compatible = "microchip,ksz-mdio";
#address-cells = <1>;
#size-cells = <0>;
sw_phy0: ethernet-phy@0 {
reg = <0x0>;
};
sw_phy1: ethernet-phy@1 {
reg = <0x1>;
};
sw_phy2: ethernet-phy@2 {
reg = <0x2>;
};
sw_phy3: ethernet-phy@3 {
reg = <0x3>;
};
};
};
};
crypto@60 {
@ -669,6 +674,41 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio5 2 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
};
&pgc_gpu {
status = "disabled";
};
&pgc_gpumix {
status = "disabled";
};
&pgc_mipi {
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
@ -677,6 +717,7 @@
dtr-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -692,6 +733,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
cts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -700,6 +742,7 @@
pinctrl-0 = <&pinctrl_uart4>, <&pinctrl_uart4_gpio>;
cts-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
rts-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -833,6 +876,13 @@
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x40000041 /* WDIS# */
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x41
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x41

119
arch/arm/dts/imx8mm-venice-gw7902.dts
View File

@ -9,6 +9,7 @@
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mm.dtsi"
@ -17,6 +18,7 @@
compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
aliases {
ethernet1 = &eth1;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
@ -128,6 +130,12 @@
};
};
pcie0_refclk: pcie0-refclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
@ -141,12 +149,13 @@
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_usb1_vbus: regulator-usb1 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1>;
compatible = "regulator-fixed";
regulator-name = "usb_usb1_vbus";
gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
@ -155,9 +164,9 @@
};
reg_wifi: regulator-wifi {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_wl>;
compatible = "regulator-fixed";
regulator-name = "wifi";
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
@ -243,18 +252,51 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
/* TI DP83867 props */
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
/* GPY111 props */
rx-internal-delay-ps = <2000>;
tx-internal-delay-ps = <2500>;
};
};
};
&gpio1 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "", "", "m2_reset", "", "m2_wdis#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names = "", "", "", "", "", "", "", "",
"uart2_en#", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names = "", "", "", "", "", "", "", "",
"", "", "", "amp_gpio3", "amp_gpio2", "", "amp_gpio1", "",
"", "", "", "", "amp_gpio4", "app_gpio1", "", "uart1_rs485",
"", "uart1_term", "uart1_half", "app_gpio2",
"mipi_gpio1", "", "", "";
};
&gpio5 {
gpio-line-names = "", "", "", "mipi_gpio4",
"mipi_gpio3", "mipi_gpio2", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
@ -530,20 +572,15 @@
status = "okay";
accelerometer@19 {
compatible = "st,lis2de12";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
compatible = "st,lis2de12";
reg = <0x19>;
st,drdy-int-pin = <1>;
interrupt-parent = <&gpio1>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "INT1";
};
secure-element@60 {
compatible = "nxp,se050";
reg = <0x60>;
};
};
/* off-board header */
@ -562,6 +599,43 @@
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
&pcie0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 5 GPIO_ACTIVE_LOW>;
clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>,
<&pcie0_refclk>;
clock-names = "pcie", "pcie_aux", "pcie_bus";
assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
<&clk IMX8MM_CLK_PCIE1_CTRL>;
assigned-clock-rates = <10000000>, <250000000>;
assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
<&clk IMX8MM_SYS_PLL2_250M>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
eth1: pcie@1,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <1>;
#size-cells = <0>;
local-mac-address = [00 00 00 00 00 00];
};
};
};
/* off-board header */
&sai3 {
pinctrl-names = "default";
@ -578,6 +652,7 @@
pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -594,6 +669,7 @@
pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
bluetooth {
@ -611,6 +687,7 @@
dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
uart-has-rtscts;
status = "okay";
};
@ -662,7 +739,7 @@
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
@ -744,11 +821,17 @@
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};
pinctrl_pcie0: pciegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x41
>;
};

5
arch/arm/dts/imx8mm-venice-gw7903.dts
View File

@ -540,6 +540,7 @@
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
clocks = <&pcie0_refclk>;
clock-names = "ref";
status = "okay";
};
@ -558,6 +559,10 @@
status = "okay";
};
&pgc_mipi {
status = "disabled";
};
/* off-board RS232/RS485/RS422 */
&uart1 {
pinctrl-names = "default";

9
include/dt-bindings/clock/imx8mm-clock.h
View File

@ -274,6 +274,13 @@
#define IMX8MM_CLK_A53_CORE 251
#define IMX8MM_CLK_END 252
#define IMX8MM_CLK_CLKOUT1_SEL 252
#define IMX8MM_CLK_CLKOUT1_DIV 253
#define IMX8MM_CLK_CLKOUT1 254
#define IMX8MM_CLK_CLKOUT2_SEL 255
#define IMX8MM_CLK_CLKOUT2_DIV 256
#define IMX8MM_CLK_CLKOUT2 257
#define IMX8MM_CLK_END 258
#endif