sunxi: video: Convert panel I2C to use DM_I2C
Two displays supported by the sunxi display driver (each one used by a single board) require initialization over I2C. Both previously used i2c_soft; replace this with the i2c-gpio instance that already exists in those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus). Since the i2c-gpio nodes are not referenced by any other node in the device trees (the device trees have no panel node), the I2C bus is selected by its node name. This panel initialization code was the only i2c_soft user, so the i2c_soft GPIO setup code can be removed now as well. Reviewed-by: Heiko Schocher <hs@denx.de> Signed-off-by: Samuel Holland <samuel@sholland.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This commit is contained in:
Samuel Holland
committed by
Andre Przywara
Andre Przywara
parent
8b0eacdf2b
commit
2421497cb7
@@ -21,18 +21,23 @@
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* This function will init an anx9804 parallel lcd to dp bridge chip
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* using the passed in parameters.
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*
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* @i2c_bus: Number of the i2c bus to which the anx9804 is connected.
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* @i2c_bus: Device of the i2c bus to which the anx9804 is connected.
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* @lanes: Number of displayport lanes to use
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* @data_rate: Register value for the bandwidth reg 0x06: 1.62G, 0x0a: 2.7G
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* @bpp: Bits per pixel, must be 18 or 24
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*/
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void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
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void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp)
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{
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unsigned int orig_i2c_bus = i2c_get_bus_num();
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u8 c, colordepth;
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int i;
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struct udevice *chip0, *chip1;
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int c, colordepth, i, ret;
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i2c_set_bus_num(i2c_bus);
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ret = i2c_get_chip(i2c_bus, 0x38, 1, &chip0);
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if (ret)
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return;
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ret = i2c_get_chip(i2c_bus, 0x39, 1, &chip1);
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if (ret)
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return;
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if (bpp == 18)
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colordepth = 0x00; /* 6 bit */
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@@ -40,24 +45,23 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
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colordepth = 0x10; /* 8 bit */
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/* Reset */
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i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 1);
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dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 1);
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mdelay(100);
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i2c_reg_write(0x39, ANX9804_RST_CTRL_REG, 0);
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dm_i2c_reg_write(chip1, ANX9804_RST_CTRL_REG, 0);
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/* Write 0 to the powerdown reg (powerup everything) */
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i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, 0);
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dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, 0);
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c = i2c_reg_read(0x39, ANX9804_DEV_IDH_REG);
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c = dm_i2c_reg_read(chip1, ANX9804_DEV_IDH_REG);
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if (c != 0x98) {
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printf("Error anx9804 chipid mismatch\n");
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i2c_set_bus_num(orig_i2c_bus);
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return;
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}
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for (i = 0; i < 100; i++) {
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c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
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i2c_reg_write(0x38, ANX9804_SYS_CTRL2_REG, c);
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c = i2c_reg_read(0x38, ANX9804_SYS_CTRL2_REG);
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c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
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dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL2_REG, c);
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c = dm_i2c_reg_read(chip0, ANX9804_SYS_CTRL2_REG);
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if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
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break;
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@@ -66,51 +70,51 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
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if (i == 100)
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printf("Error anx9804 clock is not stable\n");
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i2c_reg_write(0x39, ANX9804_VID_CTRL2_REG, colordepth);
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dm_i2c_reg_write(chip1, ANX9804_VID_CTRL2_REG, colordepth);
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/* Set a bunch of analog related register values */
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i2c_reg_write(0x38, ANX9804_PLL_CTRL_REG, 0x07);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL3, 0x19);
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i2c_reg_write(0x39, ANX9804_PLL_CTRL3, 0xd9);
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
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i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
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i2c_reg_write(0x39, ANX9804_ANALOG_DEBUG_REG3, 0x99);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL1, 0x7b);
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i2c_reg_write(0x38, ANX9804_LINK_DEBUG_REG, 0x30);
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i2c_reg_write(0x39, ANX9804_PLL_FILTER_CTRL, 0x06);
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dm_i2c_reg_write(chip0, ANX9804_PLL_CTRL_REG, 0x07);
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dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL3, 0x19);
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dm_i2c_reg_write(chip1, ANX9804_PLL_CTRL3, 0xd9);
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dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG, ANX9804_RST_CTRL2_AC_MODE);
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dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG1, 0xf0);
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dm_i2c_reg_write(chip1, ANX9804_ANALOG_DEBUG_REG3, 0x99);
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dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL1, 0x7b);
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dm_i2c_reg_write(chip0, ANX9804_LINK_DEBUG_REG, 0x30);
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dm_i2c_reg_write(chip1, ANX9804_PLL_FILTER_CTRL, 0x06);
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/* Force HPD */
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i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
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dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
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/* Power up and configure lanes */
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i2c_reg_write(0x38, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
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i2c_reg_write(0x38, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
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dm_i2c_reg_write(chip0, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
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dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
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dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
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dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
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dm_i2c_reg_write(chip0, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
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/* Reset AUX CH */
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
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i2c_reg_write(0x39, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE);
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dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE | ANX9804_RST_CTRL2_AUX);
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dm_i2c_reg_write(chip1, ANX9804_RST_CTRL2_REG,
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ANX9804_RST_CTRL2_AC_MODE);
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/* Powerdown audio and some other unused bits */
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i2c_reg_write(0x39, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
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i2c_reg_write(0x38, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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i2c_reg_write(0x38, 0xa7, 0x00);
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dm_i2c_reg_write(chip1, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
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dm_i2c_reg_write(chip0, ANX9804_HDCP_CONTROL_0_REG, 0x00);
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dm_i2c_reg_write(chip0, 0xa7, 0x00);
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/* Set data-rate / lanes */
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i2c_reg_write(0x38, ANX9804_LINK_BW_SET_REG, data_rate);
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i2c_reg_write(0x38, ANX9804_LANE_COUNT_SET_REG, lanes);
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dm_i2c_reg_write(chip0, ANX9804_LINK_BW_SET_REG, data_rate);
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dm_i2c_reg_write(chip0, ANX9804_LANE_COUNT_SET_REG, lanes);
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/* Link training */
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i2c_reg_write(0x38, ANX9804_LINK_TRAINING_CTRL_REG,
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ANX9804_LINK_TRAINING_CTRL_EN);
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dm_i2c_reg_write(chip0, ANX9804_LINK_TRAINING_CTRL_REG,
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ANX9804_LINK_TRAINING_CTRL_EN);
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mdelay(5);
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for (i = 0; i < 100; i++) {
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c = i2c_reg_read(0x38, ANX9804_LINK_TRAINING_CTRL_REG);
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c = dm_i2c_reg_read(chip0, ANX9804_LINK_TRAINING_CTRL_REG);
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if ((c & 0x01) == 0)
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break;
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@@ -118,17 +122,14 @@ void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp)
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}
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if(i == 100) {
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printf("Error anx9804 link training timeout\n");
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i2c_set_bus_num(orig_i2c_bus);
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return;
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}
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/* Enable */
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i2c_reg_write(0x39, ANX9804_VID_CTRL1_REG,
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ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
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dm_i2c_reg_write(chip1, ANX9804_VID_CTRL1_REG,
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ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
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/* Force stream valid */
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i2c_reg_write(0x38, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
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ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
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i2c_set_bus_num(orig_i2c_bus);
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dm_i2c_reg_write(chip0, ANX9804_SYS_CTRL3_REG,
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ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL |
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ANX9804_SYS_CTRL3_F_VALID | ANX9804_SYS_CTRL3_VALID_CTRL);
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}
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@@ -16,9 +16,10 @@
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#define ANX9804_DATA_RATE_2700M 0x0a
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#ifdef CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
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void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate, int bpp);
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void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate, int bpp);
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#else
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static inline void anx9804_init(unsigned int i2c_bus, u8 lanes, u8 data_rate,
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static inline void anx9804_init(struct udevice *i2c_bus, u8 lanes, u8 data_rate,
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int bpp) {}
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#endif
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#endif
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@@ -901,6 +901,42 @@ static int sunxi_ssd2828_init(const struct ctfb_res_modes *mode)
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}
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#endif /* CONFIG_VIDEO_LCD_SSD2828 */
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#ifdef CONFIG_VIDEO_LCD_PANEL_I2C
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static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display)
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{
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const char *name = CONFIG_VIDEO_LCD_PANEL_I2C_NAME;
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struct udevice *i2c_bus;
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int ret;
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ret = uclass_get_device_by_name(UCLASS_I2C, name, &i2c_bus);
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if (ret)
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return;
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if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
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/*
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* The anx9804 needs 1.8V from eldo3, we do this here
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* and not via CONFIG_AXP_ELDO3_VOLT from board_init()
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* to avoid turning this on when using hdmi output.
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*/
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axp_set_eldo(3, 1800);
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anx9804_init(i2c_bus, 4,
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ANX9804_DATA_RATE_1620M,
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sunxi_display->depth);
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}
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if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
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struct udevice *chip;
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ret = i2c_get_chip(i2c_bus, 0x5c, 1, &chip);
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if (ret)
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return;
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dm_i2c_reg_write(chip, 0x04, 0x42); /* Turn on the LCD */
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}
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}
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#else
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static void sunxi_panel_i2c_init(struct sunxi_display_priv *sunxi_display) {}
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#endif
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static void sunxi_engines_init(void)
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{
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sunxi_composer_init();
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@@ -935,27 +971,12 @@ static void sunxi_mode_set(struct sunxi_display_priv *sunxi_display,
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break;
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case sunxi_monitor_lcd:
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sunxi_lcdc_panel_enable();
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if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804)) {
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/*
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* The anx9804 needs 1.8V from eldo3, we do this here
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* and not via CONFIG_AXP_ELDO3_VOLT from board_init()
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* to avoid turning this on when using hdmi output.
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*/
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axp_set_eldo(3, 1800);
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anx9804_init(CONFIG_VIDEO_LCD_I2C_BUS, 4,
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ANX9804_DATA_RATE_1620M,
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sunxi_display->depth);
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}
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if (IS_ENABLED(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM)) {
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mdelay(50); /* Wait for lcd controller power on */
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hitachi_tx18d42vm_init();
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}
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if (IS_ENABLED(CONFIG_VIDEO_LCD_TL059WV5C0)) {
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unsigned int orig_i2c_bus = i2c_get_bus_num();
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i2c_set_bus_num(CONFIG_VIDEO_LCD_I2C_BUS);
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i2c_reg_write(0x5c, 0x04, 0x42); /* Turn on the LCD */
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i2c_set_bus_num(orig_i2c_bus);
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}
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if (IS_ENABLED(CONFIG_VIDEO_LCD_PANEL_I2C))
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sunxi_panel_i2c_init(sunxi_display);
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sunxi_composer_mode_set(mode, address, monitor);
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sunxi_lcdc_tcon0_mode_set(sunxi_display, mode, false);
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sunxi_composer_enable();
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