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imx: mx6: ddr no support MMDC1 for i.MX6SL

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i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan 2015-08-17 16:10:58 +08:00 committed by Stefano Babic
parent 43d9dc4136
commit 24139754f5
1 changed files with 4 additions and 2 deletions
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6
arch/arm/cpu/armv7/mx6/ddr.c
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@ -288,7 +288,8 @@ void mx6sdl_dram_iocfg(unsigned width,
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL)) \
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) && \
!is_cpu_type(MXC_CPU_MX6SL)) \
mmdc1->entry = value; \
} while (0)
@ -312,7 +313,8 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL))
if (!is_cpu_type(MXC_CPU_MX6SX) && !is_cpu_type(MXC_CPU_MX6UL) &&
!is_cpu_type(MXC_CPU_MX6SL))
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */