PXA: Cleanup serial_pxa
* Cleanup register definitions by introducing new regs-uart.h, compliant with rest of U-Boot. * Remove old register definitions from pxa-regs.h * Convert serial_pxa to new regs-uart.h * Cleanup serial_pxa Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
This commit is contained in:
Marek Vasut
Albert ARIBAUD
parent
dd36d806fe
commit
237ce0fe97
@ -313,117 +313,6 @@ typedef void (*ExcpHndlr) (void) ;
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#define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
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#define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
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/******************************************************************************/
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/*
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* UARTs
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*/
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/* Full Function UART (FFUART) */
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#define FFUART FFRBR
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#define FFRBR 0x40100000 /* Receive Buffer Register (read only) */
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#define FFTHR 0x40100000 /* Transmit Holding Register (write only) */
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#define FFIER 0x40100004 /* Interrupt Enable Register (read/write) */
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#define FFIIR 0x40100008 /* Interrupt ID Register (read only) */
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#define FFFCR 0x40100008 /* FIFO Control Register (write only) */
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#define FFLCR 0x4010000C /* Line Control Register (read/write) */
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#define FFMCR 0x40100010 /* Modem Control Register (read/write) */
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#define FFLSR 0x40100014 /* Line Status Register (read only) */
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#define FFMSR 0x40100018 /* Modem Status Register (read only) */
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#define FFSPR 0x4010001C /* Scratch Pad Register (read/write) */
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#define FFISR 0x40100020 /* Infrared Selection Register (read/write) */
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#define FFDLL 0x40100000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define FFDLH 0x40100004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Bluetooth UART (BTUART) */
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#define BTUART BTRBR
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#define BTRBR 0x40200000 /* Receive Buffer Register (read only) */
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#define BTTHR 0x40200000 /* Transmit Holding Register (write only) */
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#define BTIER 0x40200004 /* Interrupt Enable Register (read/write) */
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#define BTIIR 0x40200008 /* Interrupt ID Register (read only) */
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#define BTFCR 0x40200008 /* FIFO Control Register (write only) */
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#define BTLCR 0x4020000C /* Line Control Register (read/write) */
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#define BTMCR 0x40200010 /* Modem Control Register (read/write) */
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#define BTLSR 0x40200014 /* Line Status Register (read only) */
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#define BTMSR 0x40200018 /* Modem Status Register (read only) */
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#define BTSPR 0x4020001C /* Scratch Pad Register (read/write) */
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#define BTISR 0x40200020 /* Infrared Selection Register (read/write) */
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#define BTDLL 0x40200000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define BTDLH 0x40200004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
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/* Standard UART (STUART) */
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#define STUART STRBR
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#define STRBR 0x40700000 /* Receive Buffer Register (read only) */
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#define STTHR 0x40700000 /* Transmit Holding Register (write only) */
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#define STIER 0x40700004 /* Interrupt Enable Register (read/write) */
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#define STIIR 0x40700008 /* Interrupt ID Register (read only) */
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#define STFCR 0x40700008 /* FIFO Control Register (write only) */
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#define STLCR 0x4070000C /* Line Control Register (read/write) */
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#define STMCR 0x40700010 /* Modem Control Register (read/write) */
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#define STLSR 0x40700014 /* Line Status Register (read only) */
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#define STMSR 0x40700018 /* Reserved */
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#define STSPR 0x4070001C /* Scratch Pad Register (read/write) */
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#define STISR 0x40700020 /* Infrared Selection Register (read/write) */
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#define STDLL 0x40700000 /* Divisor Latch Low Register (DLAB = 1) (read/write) */
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#define STDLH 0x40700004 /* Divisor Latch High Register (DLAB = 1) (read/write) */
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#define IER_DMAE (1 << 7) /* DMA Requests Enable */
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#define IER_UUE (1 << 6) /* UART Unit Enable */
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#define IER_NRZE (1 << 5) /* NRZ coding Enable */
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#define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
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#define IER_MIE (1 << 3) /* Modem Interrupt Enable */
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#define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
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#define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
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#define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
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#define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
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#define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
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#define IIR_TOD (1 << 3) /* Time Out Detected */
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#define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
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#define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
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#define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
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#define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
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#define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
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#define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
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#define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
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#define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
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#define FCR_ITL_1 (0)
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#define FCR_ITL_8 (FCR_ITL1)
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#define FCR_ITL_16 (FCR_ITL2)
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#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
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#define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
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#define LCR_SB (1 << 6) /* Set Break */
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#define LCR_STKYP (1 << 5) /* Sticky Parity */
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#define LCR_EPS (1 << 4) /* Even Parity Select */
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#define LCR_PEN (1 << 3) /* Parity Enable */
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#define LCR_STB (1 << 2) /* Stop Bit */
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#define LCR_WLS1 (1 << 1) /* Word Length Select */
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#define LCR_WLS0 (1 << 0) /* Word Length Select */
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#define LSR_FIFOE (1 << 7) /* FIFO Error Status */
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#define LSR_TEMT (1 << 6) /* Transmitter Empty */
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#define LSR_TDRQ (1 << 5) /* Transmit Data Request */
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#define LSR_BI (1 << 4) /* Break Interrupt */
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#define LSR_FE (1 << 3) /* Framing Error */
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#define LSR_PE (1 << 2) /* Parity Error */
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#define LSR_OE (1 << 1) /* Overrun Error */
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#define LSR_DR (1 << 0) /* Data Ready */
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#define MCR_LOOP (1 << 4) /* */
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#define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
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#define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
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#define MCR_RTS (1 << 1) /* Request to Send */
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#define MCR_DTR (1 << 0) /* Data Terminal Ready */
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#define MSR_DCD (1 << 7) /* Data Carrier Detect */
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#define MSR_RI (1 << 6) /* Ring Indicator */
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#define MSR_DSR (1 << 5) /* Data Set Ready */
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#define MSR_CTS (1 << 4) /* Clear To Send */
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#define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
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#define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
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#define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
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#define MSR_DCTS (1 << 0) /* Delta Clear To Send */
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/******************************************************************************/
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/*
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* IrSR (Infrared Selection Register)
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109
arch/arm/include/asm/arch-pxa/regs-uart.h
Normal file
109
arch/arm/include/asm/arch-pxa/regs-uart.h
Normal file
@ -0,0 +1,109 @@
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/*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __REGS_UART_H__
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#define __REGS_UART_H__
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#define FFUART_BASE 0x40100000
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#define BTUART_BASE 0x40200000
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#define STUART_BASE 0x40700000
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#define HWUART_BASE 0x41600000
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struct pxa_uart_regs {
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union {
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uint32_t thr;
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uint32_t rbr;
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uint32_t dll;
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};
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union {
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uint32_t ier;
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uint32_t dlh;
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};
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union {
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uint32_t fcr;
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uint32_t iir;
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};
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uint32_t lcr;
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uint32_t mcr;
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uint32_t lsr;
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uint32_t msr;
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uint32_t spr;
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uint32_t isr;
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};
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#define IER_DMAE (1 << 7)
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#define IER_UUE (1 << 6)
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#define IER_NRZE (1 << 5)
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#define IER_RTIOE (1 << 4)
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#define IER_MIE (1 << 3)
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#define IER_RLSE (1 << 2)
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#define IER_TIE (1 << 1)
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#define IER_RAVIE (1 << 0)
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#define IIR_FIFOES1 (1 << 7)
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#define IIR_FIFOES0 (1 << 6)
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#define IIR_TOD (1 << 3)
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#define IIR_IID2 (1 << 2)
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#define IIR_IID1 (1 << 1)
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#define IIR_IP (1 << 0)
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#define FCR_ITL2 (1 << 7)
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#define FCR_ITL1 (1 << 6)
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#define FCR_RESETTF (1 << 2)
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#define FCR_RESETRF (1 << 1)
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#define FCR_TRFIFOE (1 << 0)
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#define FCR_ITL_1 0
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#define FCR_ITL_8 (FCR_ITL1)
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#define FCR_ITL_16 (FCR_ITL2)
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#define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
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#define LCR_DLAB (1 << 7)
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#define LCR_SB (1 << 6)
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#define LCR_STKYP (1 << 5)
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#define LCR_EPS (1 << 4)
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#define LCR_PEN (1 << 3)
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#define LCR_STB (1 << 2)
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#define LCR_WLS1 (1 << 1)
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#define LCR_WLS0 (1 << 0)
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#define LSR_FIFOE (1 << 7)
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#define LSR_TEMT (1 << 6)
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#define LSR_TDRQ (1 << 5)
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#define LSR_BI (1 << 4)
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#define LSR_FE (1 << 3)
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#define LSR_PE (1 << 2)
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#define LSR_OE (1 << 1)
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#define LSR_DR (1 << 0)
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#define MCR_LOOP (1 << 4)
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#define MCR_OUT2 (1 << 3)
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#define MCR_OUT1 (1 << 2)
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#define MCR_RTS (1 << 1)
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#define MCR_DTR (1 << 0)
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#define MSR_DCD (1 << 7)
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#define MSR_RI (1 << 6)
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#define MSR_DSR (1 << 5)
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#define MSR_CTS (1 << 4)
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#define MSR_DDCD (1 << 3)
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#define MSR_TERI (1 << 2)
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#define MSR_DDSR (1 << 1)
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#define MSR_DCTS (1 << 0)
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#endif /* __REGS_UART_H__ */
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@ -1,4 +1,6 @@
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/*
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* Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
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*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
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*
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@ -32,148 +34,161 @@
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#include <watchdog.h>
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#include <serial.h>
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#include <asm/arch/pxa-regs.h>
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#include <asm/arch/regs-uart.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define FFUART_INDEX 0
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#define BTUART_INDEX 1
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#define STUART_INDEX 2
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/*
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* The numbering scheme differs here for PXA25x, PXA27x and PXA3xx so we can
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* easily handle enabling of clock.
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*/
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#ifdef CONFIG_CPU_MONAHANS
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#define UART_CLK_BASE CKENA_21_BTUART
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#define UART_CLK_REG CKENA
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#define BTUART_INDEX 0
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#define FFUART_INDEX 1
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#define STUART_INDEX 2
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#elif CONFIG_PXA250
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#define UART_CLK_BASE (1 << 4) /* HWUART */
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#define UART_CLK_REG CKEN
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#define HWUART_INDEX 0
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#define STUART_INDEX 1
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#define FFUART_INDEX 2
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#define BTUART_INDEX 3
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#else /* PXA27x */
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#define UART_CLK_BASE CKEN5_STUART
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#define UART_CLK_REG CKEN
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#define STUART_INDEX 0
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#define FFUART_INDEX 1
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#define BTUART_INDEX 2
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#endif
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/*
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* Only PXA250 has HWUART, to avoid poluting the code with more macros,
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* artificially introduce this.
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*/
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#ifndef CONFIG_PXA250
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#define HWUART_INDEX 0xff
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#endif
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#ifndef CONFIG_SERIAL_MULTI
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#if defined (CONFIG_FFUART)
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#if defined(CONFIG_FFUART)
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#define UART_INDEX FFUART_INDEX
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#elif defined (CONFIG_BTUART)
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#elif defined(CONFIG_BTUART)
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#define UART_INDEX BTUART_INDEX
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#elif defined (CONFIG_STUART)
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#elif defined(CONFIG_STUART)
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#define UART_INDEX STUART_INDEX
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#elif defined(CONFIG_HWUART)
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#define UART_INDEX HWUART_INDEX
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#else
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#error "Bad: you didn't configure serial ..."
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#error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
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#endif
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#endif
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void pxa_setbrg_dev (unsigned int uart_index)
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uint32_t pxa_uart_get_baud_divider(void)
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{
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unsigned int quot = 0;
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if (gd->baudrate == 1200)
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quot = 768;
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return 768;
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else if (gd->baudrate == 9600)
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quot = 96;
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return 96;
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else if (gd->baudrate == 19200)
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quot = 48;
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return 48;
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else if (gd->baudrate == 38400)
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quot = 24;
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return 24;
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else if (gd->baudrate == 57600)
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quot = 16;
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return 16;
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else if (gd->baudrate == 115200)
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quot = 8;
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else
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hang ();
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return 8;
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else /* Unsupported baudrate */
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return 0;
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}
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struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
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{
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switch (uart_index) {
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case FFUART_INDEX:
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENA) | CKENA_22_FFUART, CKENA);
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#else
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writel(readl(CKEN) | CKEN6_FFUART, CKEN);
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#endif /* CONFIG_CPU_MONAHANS */
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writel(0, FFIER); /* Disable for now */
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writel(0, FFFCR); /* No fifos enabled */
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/* set baud rate */
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writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, FFLCR);
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writel(quot & 0xff, FFDLL);
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writel(quot >> 8, FFDLH);
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writel(LCR_WLS0 | LCR_WLS1, FFLCR);
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writel(IER_UUE, FFIER); /* Enable FFUART */
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break;
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case BTUART_INDEX:
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENA) | CKENA_21_BTUART, CKENA);
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#else
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writel(readl(CKEN) | CKEN7_BTUART, CKEN);
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#endif /* CONFIG_CPU_MONAHANS */
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writel(0, BTIER);
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writel(0, BTFCR);
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/* set baud rate */
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writel(LCR_DLAB, BTLCR);
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writel(quot & 0xff, BTDLL);
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writel(quot >> 8, BTDLH);
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writel(LCR_WLS0 | LCR_WLS1, BTLCR);
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writel(IER_UUE, BTIER); /* Enable BFUART */
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break;
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case STUART_INDEX:
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#ifdef CONFIG_CPU_MONAHANS
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writel(readl(CKENA) | CKENA_23_STUART, CKENA);
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#else
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writel(readl(CKEN) | CKEN5_STUART, CKEN);
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#endif /* CONFIG_CPU_MONAHANS */
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writel(0, STIER);
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writel(0, STFCR);
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/* set baud rate */
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writel(LCR_DLAB, STLCR);
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writel(quot & 0xff, STDLL);
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writel(quot >> 8, STDLH);
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writel(LCR_WLS0 | LCR_WLS1, STLCR);
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writel(IER_UUE, STIER); /* Enable STUART */
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break;
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default:
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hang();
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case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
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case BTUART_INDEX: return (struct pxa_uart_regs *)BTUART_BASE;
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case STUART_INDEX: return (struct pxa_uart_regs *)STUART_BASE;
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case HWUART_INDEX: return (struct pxa_uart_regs *)HWUART_BASE;
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default:
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return NULL;
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}
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}
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void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
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{
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uint32_t clk_reg, clk_offset, reg;
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clk_reg = UART_CLK_REG;
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clk_offset = UART_CLK_BASE << uart_index;
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||||
reg = readl(clk_reg);
|
||||
|
||||
if (enable)
|
||||
reg |= clk_offset;
|
||||
else
|
||||
reg &= ~clk_offset;
|
||||
|
||||
writel(reg, clk_reg);
|
||||
}
|
||||
|
||||
/*
|
||||
* Enable clock and set baud rate, parity etc.
|
||||
*/
|
||||
void pxa_setbrg_dev(uint32_t uart_index)
|
||||
{
|
||||
uint32_t divider = 0;
|
||||
struct pxa_uart_regs *uart_regs;
|
||||
|
||||
divider = pxa_uart_get_baud_divider();
|
||||
if (!divider)
|
||||
hang();
|
||||
|
||||
uart_regs = pxa_uart_index_to_regs(uart_index);
|
||||
if (!uart_regs)
|
||||
hang();
|
||||
|
||||
pxa_uart_toggle_clock(uart_index, 1);
|
||||
|
||||
/* Disable interrupts and FIFOs */
|
||||
writel(0, &uart_regs->ier);
|
||||
writel(0, &uart_regs->fcr);
|
||||
|
||||
/* Set baud rate */
|
||||
writel(LCR_WLS0 | LCR_WLS1 | LCR_DLAB, &uart_regs->lcr);
|
||||
writel(divider & 0xff, &uart_regs->dll);
|
||||
writel(divider >> 8, &uart_regs->dlh);
|
||||
writel(LCR_WLS0 | LCR_WLS1, &uart_regs->lcr);
|
||||
|
||||
/* Enable UART */
|
||||
writel(IER_UUE, &uart_regs->ier);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialise the serial port with the given baudrate. The settings
|
||||
* are always 8 data bits, no parity, 1 stop bit, no start bits.
|
||||
*
|
||||
*/
|
||||
int pxa_init_dev (unsigned int uart_index)
|
||||
int pxa_init_dev(unsigned int uart_index)
|
||||
{
|
||||
pxa_setbrg_dev (uart_index);
|
||||
|
||||
return (0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Output a single byte to the serial port.
|
||||
*/
|
||||
void pxa_putc_dev (unsigned int uart_index,const char c)
|
||||
void pxa_putc_dev(unsigned int uart_index, const char c)
|
||||
{
|
||||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
/* wait for room in the tx FIFO on FFUART */
|
||||
while ((readl(FFLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
writel(c, FFTHR);
|
||||
break;
|
||||
struct pxa_uart_regs *uart_regs;
|
||||
|
||||
case BTUART_INDEX:
|
||||
while ((readl(BTLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
writel(c, BTTHR);
|
||||
break;
|
||||
uart_regs = pxa_uart_index_to_regs(uart_index);
|
||||
if (!uart_regs)
|
||||
hang();
|
||||
|
||||
case STUART_INDEX:
|
||||
while ((readl(STLSR) & LSR_TEMT) == 0)
|
||||
WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
|
||||
writel(c, STTHR);
|
||||
break;
|
||||
}
|
||||
while (!(readl(&uart_regs->lsr) & LSR_TEMT))
|
||||
WATCHDOG_RESET();
|
||||
writel(c, &uart_regs->thr);
|
||||
|
||||
/* If \n, also do \r */
|
||||
if (c == '\n')
|
||||
@ -185,17 +200,15 @@ void pxa_putc_dev (unsigned int uart_index,const char c)
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
int pxa_tstc_dev (unsigned int uart_index)
|
||||
int pxa_tstc_dev(unsigned int uart_index)
|
||||
{
|
||||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
return readl(FFLSR) & LSR_DR;
|
||||
case BTUART_INDEX:
|
||||
return readl(BTLSR) & LSR_DR;
|
||||
case STUART_INDEX:
|
||||
return readl(STLSR) & LSR_DR;
|
||||
}
|
||||
return -1;
|
||||
struct pxa_uart_regs *uart_regs;
|
||||
|
||||
uart_regs = pxa_uart_index_to_regs(uart_index);
|
||||
if (!uart_regs)
|
||||
return -1;
|
||||
|
||||
return readl(&uart_regs->lsr) & LSR_DR;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -203,187 +216,86 @@ int pxa_tstc_dev (unsigned int uart_index)
|
||||
* otherwise. When the function is succesfull, the character read is
|
||||
* written into its argument c.
|
||||
*/
|
||||
int pxa_getc_dev (unsigned int uart_index)
|
||||
int pxa_getc_dev(unsigned int uart_index)
|
||||
{
|
||||
switch (uart_index) {
|
||||
case FFUART_INDEX:
|
||||
while (!(readl(FFLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(FFRBR) & 0xff;
|
||||
struct pxa_uart_regs *uart_regs;
|
||||
|
||||
case BTUART_INDEX:
|
||||
while (!(readl(BTLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(BTRBR) & 0xff;
|
||||
case STUART_INDEX:
|
||||
while (!(readl(STLSR) & LSR_DR))
|
||||
/* Reset HW Watchdog, if needed */
|
||||
WATCHDOG_RESET();
|
||||
return (char) readl(STRBR) & 0xff;
|
||||
}
|
||||
return -1;
|
||||
uart_regs = pxa_uart_index_to_regs(uart_index);
|
||||
if (!uart_regs)
|
||||
return -1;
|
||||
|
||||
while (!(readl(&uart_regs->lsr) & LSR_DR))
|
||||
WATCHDOG_RESET();
|
||||
return readl(&uart_regs->rbr) & 0xff;
|
||||
}
|
||||
|
||||
void
|
||||
pxa_puts_dev (unsigned int uart_index,const char *s)
|
||||
void pxa_puts_dev(unsigned int uart_index, const char *s)
|
||||
{
|
||||
while (*s) {
|
||||
pxa_putc_dev (uart_index,*s++);
|
||||
}
|
||||
while (*s)
|
||||
pxa_putc_dev(uart_index, *s++);
|
||||
}
|
||||
|
||||
#if defined (CONFIG_FFUART)
|
||||
static int ffuart_init(void)
|
||||
{
|
||||
return pxa_init_dev(FFUART_INDEX);
|
||||
}
|
||||
#define pxa_uart(uart, UART) \
|
||||
int uart##_init(void) \
|
||||
{ \
|
||||
return pxa_init_dev(UART##_INDEX); \
|
||||
} \
|
||||
\
|
||||
void uart##_setbrg(void) \
|
||||
{ \
|
||||
return pxa_setbrg_dev(UART##_INDEX); \
|
||||
} \
|
||||
\
|
||||
void uart##_putc(const char c) \
|
||||
{ \
|
||||
return pxa_putc_dev(UART##_INDEX, c); \
|
||||
} \
|
||||
\
|
||||
void uart##_puts(const char *s) \
|
||||
{ \
|
||||
return pxa_puts_dev(UART##_INDEX, s); \
|
||||
} \
|
||||
\
|
||||
int uart##_getc(void) \
|
||||
{ \
|
||||
return pxa_getc_dev(UART##_INDEX); \
|
||||
} \
|
||||
\
|
||||
int uart##_tstc(void) \
|
||||
{ \
|
||||
return pxa_tstc_dev(UART##_INDEX); \
|
||||
} \
|
||||
|
||||
static void ffuart_setbrg(void)
|
||||
{
|
||||
return pxa_setbrg_dev(FFUART_INDEX);
|
||||
}
|
||||
#define pxa_uart_desc(uart) \
|
||||
struct serial_device serial_##uart##_device = \
|
||||
{ \
|
||||
"serial_"#uart, \
|
||||
uart##_init, \
|
||||
NULL, \
|
||||
uart##_setbrg, \
|
||||
uart##_getc, \
|
||||
uart##_tstc, \
|
||||
uart##_putc, \
|
||||
uart##_puts, \
|
||||
};
|
||||
|
||||
static void ffuart_putc(const char c)
|
||||
{
|
||||
return pxa_putc_dev(FFUART_INDEX,c);
|
||||
}
|
||||
#define pxa_uart_multi(uart, UART) \
|
||||
pxa_uart(uart, UART) \
|
||||
pxa_uart_desc(uart)
|
||||
|
||||
static void ffuart_puts(const char *s)
|
||||
{
|
||||
return pxa_puts_dev(FFUART_INDEX,s);
|
||||
}
|
||||
|
||||
static int ffuart_getc(void)
|
||||
{
|
||||
return pxa_getc_dev(FFUART_INDEX);
|
||||
}
|
||||
|
||||
static int ffuart_tstc(void)
|
||||
{
|
||||
return pxa_tstc_dev(FFUART_INDEX);
|
||||
}
|
||||
|
||||
struct serial_device serial_ffuart_device =
|
||||
{
|
||||
"serial_ffuart",
|
||||
ffuart_init,
|
||||
NULL,
|
||||
ffuart_setbrg,
|
||||
ffuart_getc,
|
||||
ffuart_tstc,
|
||||
ffuart_putc,
|
||||
ffuart_puts,
|
||||
};
|
||||
#if defined(CONFIG_HWUART)
|
||||
pxa_uart_multi(hwuart, HWUART)
|
||||
#endif
|
||||
#if defined(CONFIG_STUART)
|
||||
pxa_uart_multi(stuart, STUART)
|
||||
#endif
|
||||
#if defined(CONFIG_FFUART)
|
||||
pxa_uart_multi(ffuart, FFUART)
|
||||
#endif
|
||||
#if defined(CONFIG_BTUART)
|
||||
pxa_uart_multi(btuart, BTUART)
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_BTUART)
|
||||
static int btuart_init(void)
|
||||
{
|
||||
return pxa_init_dev(BTUART_INDEX);
|
||||
}
|
||||
|
||||
static void btuart_setbrg(void)
|
||||
{
|
||||
return pxa_setbrg_dev(BTUART_INDEX);
|
||||
}
|
||||
|
||||
static void btuart_putc(const char c)
|
||||
{
|
||||
return pxa_putc_dev(BTUART_INDEX,c);
|
||||
}
|
||||
|
||||
static void btuart_puts(const char *s)
|
||||
{
|
||||
return pxa_puts_dev(BTUART_INDEX,s);
|
||||
}
|
||||
|
||||
static int btuart_getc(void)
|
||||
{
|
||||
return pxa_getc_dev(BTUART_INDEX);
|
||||
}
|
||||
|
||||
static int btuart_tstc(void)
|
||||
{
|
||||
return pxa_tstc_dev(BTUART_INDEX);
|
||||
}
|
||||
|
||||
struct serial_device serial_btuart_device =
|
||||
{
|
||||
"serial_btuart",
|
||||
btuart_init,
|
||||
NULL,
|
||||
btuart_setbrg,
|
||||
btuart_getc,
|
||||
btuart_tstc,
|
||||
btuart_putc,
|
||||
btuart_puts,
|
||||
};
|
||||
#ifndef CONFIG_SERIAL_MULTI
|
||||
pxa_uart(serial, UART)
|
||||
#endif
|
||||
|
||||
#if defined (CONFIG_STUART)
|
||||
static int stuart_init(void)
|
||||
{
|
||||
return pxa_init_dev(STUART_INDEX);
|
||||
}
|
||||
|
||||
static void stuart_setbrg(void)
|
||||
{
|
||||
return pxa_setbrg_dev(STUART_INDEX);
|
||||
}
|
||||
|
||||
static void stuart_putc(const char c)
|
||||
{
|
||||
return pxa_putc_dev(STUART_INDEX,c);
|
||||
}
|
||||
|
||||
static void stuart_puts(const char *s)
|
||||
{
|
||||
return pxa_puts_dev(STUART_INDEX,s);
|
||||
}
|
||||
|
||||
static int stuart_getc(void)
|
||||
{
|
||||
return pxa_getc_dev(STUART_INDEX);
|
||||
}
|
||||
|
||||
static int stuart_tstc(void)
|
||||
{
|
||||
return pxa_tstc_dev(STUART_INDEX);
|
||||
}
|
||||
|
||||
struct serial_device serial_stuart_device =
|
||||
{
|
||||
"serial_stuart",
|
||||
stuart_init,
|
||||
NULL,
|
||||
stuart_setbrg,
|
||||
stuart_getc,
|
||||
stuart_tstc,
|
||||
stuart_putc,
|
||||
stuart_puts,
|
||||
};
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef CONFIG_SERIAL_MULTI
|
||||
inline int serial_init(void) {
|
||||
return (pxa_init_dev(UART_INDEX));
|
||||
}
|
||||
void serial_setbrg(void) {
|
||||
pxa_setbrg_dev(UART_INDEX);
|
||||
}
|
||||
int serial_getc(void) {
|
||||
return(pxa_getc_dev(UART_INDEX));
|
||||
}
|
||||
int serial_tstc(void) {
|
||||
return(pxa_tstc_dev(UART_INDEX));
|
||||
}
|
||||
void serial_putc(const char c) {
|
||||
pxa_putc_dev(UART_INDEX,c);
|
||||
}
|
||||
void serial_puts(const char *s) {
|
||||
pxa_puts_dev(UART_INDEX,s);
|
||||
}
|
||||
#endif /* CONFIG_SERIAL_MULTI */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user