riscv: Enable AI ram on K210

We just need to initialize all the clocks pre-reloc. The clock driver
creates a bunch of devices, so we need to increase the pre-reloc malloc
arena.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
This commit is contained in:
Sean Anderson 2021-04-08 22:13:10 -04:00 committed by Leo Yu-Chi Liang
parent 2eebe5b373
commit 23058052de
3 changed files with 14 additions and 3 deletions

View File

@ -14,7 +14,7 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_SDRAM_SIZE;
}
int board_init(void)
static int sram_init(void)
{
int ret, i;
const char * const banks[] = { "sram0", "sram1", "airam" };
@ -39,3 +39,13 @@ int board_init(void)
return 0;
}
int board_early_init_f(void)
{
return sram_init();
}
int board_init(void)
{
return 0;
}

View File

@ -1,4 +1,5 @@
CONFIG_RISCV=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x1000
CONFIG_ENV_OFFSET=0xfff000
CONFIG_ENV_SECT_SIZE=0x1000
@ -7,6 +8,7 @@ CONFIG_ARCH_RV64I=y
CONFIG_STACK_SIZE=0x100000
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="run k210_bootcmd"
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_MTDIDS_DEFAULT="nor0=spi3:0"
CONFIG_MTDPARTS_DEFAULT="nor0:1M(u-boot),0x1000@0xfff000(env)"

View File

@ -15,8 +15,7 @@
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_SYS_SDRAM_BASE 0x80000000
/* Don't relocate into AI ram since it isn't set up yet */
#define CONFIG_SYS_SDRAM_SIZE (SZ_4M + SZ_2M)
#define CONFIG_SYS_SDRAM_SIZE SZ_8M
#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \