pci: tegra: use #address-/size-cells from DT
The number of cells used by each entry in the DT ranges property is determined by the #address-cells/#size-cells properties. Fix the code to respect this. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -406,9 +406,34 @@ static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
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static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
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struct tegra_pcie *pcie)
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{
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int parent, na_parent, na_pcie, ns_pcie;
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const u32 *ptr, *end;
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int len;
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parent = fdt_parent_offset(fdt, node);
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if (parent < 0) {
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error("Can't find PCI parent node\n");
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return -FDT_ERR_NOTFOUND;
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}
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na_parent = fdt_address_cells(fdt, parent);
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if (na_parent < 1) {
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error("bad #address-cells for PCIE parent\n");
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return -FDT_ERR_NOTFOUND;
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}
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na_pcie = fdt_address_cells(fdt, node);
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if (na_pcie < 1) {
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error("bad #address-cells for PCIE\n");
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return -FDT_ERR_NOTFOUND;
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}
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ns_pcie = fdt_size_cells(fdt, node);
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if (ns_pcie < 1) {
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error("bad #size-cells for PCIE\n");
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return -FDT_ERR_NOTFOUND;
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}
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ptr = fdt_getprop(fdt, node, "ranges", &len);
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if (!ptr) {
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error("missing \"ranges\" property");
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@ -437,11 +462,13 @@ static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
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}
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if (res) {
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res->start = fdt32_to_cpu(ptr[3]);
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res->end = res->start + fdt32_to_cpu(ptr[5]);
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int start_low = na_pcie + (na_parent - 1);
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int size_low = na_pcie + na_parent + (ns_pcie - 1);
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res->start = fdt32_to_cpu(ptr[start_low]);
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res->end = res->start + fdt32_to_cpu(ptr[size_low]);
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}
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ptr += 3 + 1 + 2;
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ptr += na_pcie + na_parent + ns_pcie;
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}
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debug("PCI regions:\n");
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