leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge tag 'u-boot-stm32-20220510' of https://source.denx.de/u-boot/custodians/u-boot-stm

Browse Source 
Add new STM32 MCU boards and Documentation
STM32 programmer improvements
video: support several LTDC HW versions and fix data enable polarity
board: fix stboard error message, consider USB cable connected when boot device is USB
configs: stm32mp1: set console variable for extlinux.conf
configs: stm32mp1: add support for baudrate higher than 115200 for ST-Link
ARM: stm32mp: Fix Silicon version handling and ft_system_setup()
phy: stm32-usbphyc: Add DT phy tuning support
arm: dts: stm32mp15: alignment with v5.18
ram: Conditionally enable ASR
mach-stm32mp: psci: retain MCUDIVR, PLL3CR, PLL4CR, MSSCKSELR across suspend
configs: Use TFTP_TSIZE on DHSOM and STMicroelectronics boards
ARM: stm32: Use default CONFIG_TFTP_BLOCKSIZE on DHSOM
pinctrl: stm32: rework GPIO holes management
This commit is contained in:
Tom Rini
2022-05-10 15:28:02 -04:00
parent b4eb577663 e198d4fe7c
commit 21e25992c8
60 changed files with 1573 additions and 306 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/clk/clk_stm32mp1.c
View File

@@ -2205,7 +2205,7 @@ static void stm32mp1_osc_init(struct udevice *dev)
for (i = 0; i < NB_OSC; i++) {
if (clk_get_by_name(dev, name[i], &priv->osc_clk[i]))
dev_dbg(dev, "No source clock \"%s\"", name[i]);
dev_dbg(dev, "No source clock \"%s\"\n", name[i]);
else
dev_dbg(dev, "%s clock rate: %luHz\n",
name[i], clk_get_rate(&priv->osc_clk[i]));

101
drivers/gpio/stm32_gpio.c
View File

@@ -83,38 +83,22 @@ static enum stm32_gpio_pupd stm32_gpio_get_pupd(struct stm32_gpio_regs *regs,
return (readl(&regs->pupdr) >> PUPD_BITS(idx)) & PUPD_MASK;
}
/*
* convert gpio offset to gpio index taking into account gpio holes
* into gpio bank
*/
int stm32_offset_to_index(struct udevice *dev, unsigned int offset)
static bool stm32_gpio_is_mapped(struct udevice *dev, int offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
unsigned int idx = 0;
int i;
for (i = 0; i < STM32_GPIOS_PER_BANK; i++) {
if (priv->gpio_range & BIT(i)) {
if (idx == offset)
return idx;
idx++;
}
}
/* shouldn't happen */
return -EINVAL;
return !!(priv->gpio_range & BIT(offset));
}
static int stm32_gpio_direction_input(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
return 0;
}
@@ -124,15 +108,13 @@ static int stm32_gpio_direction_output(struct udevice *dev, unsigned offset,
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
writel(BSRR_BIT(idx, value), &regs->bsrr);
writel(BSRR_BIT(offset, value), &regs->bsrr);
return 0;
}
@@ -141,26 +123,22 @@ static int stm32_gpio_get_value(struct udevice *dev, unsigned offset)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
return readl(&regs->idr) & BIT(idx) ? 1 : 0;
return readl(&regs->idr) & BIT(offset) ? 1 : 0;
}
static int stm32_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
writel(BSRR_BIT(idx, value), &regs->bsrr);
writel(BSRR_BIT(offset, value), &regs->bsrr);
return 0;
}
@@ -171,14 +149,12 @@ static int stm32_gpio_get_function(struct udevice *dev, unsigned int offset)
struct stm32_gpio_regs *regs = priv->regs;
int bits_index;
int mask;
int idx;
u32 mode;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return GPIOF_UNKNOWN;
bits_index = MODE_BITS(idx);
bits_index = MODE_BITS(offset);
mask = MODE_BITS_MASK << bits_index;
mode = (readl(&regs->moder) & mask) >> bits_index;
@@ -197,30 +173,28 @@ static int stm32_gpio_set_flags(struct udevice *dev, unsigned int offset,
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
if (flags & GPIOD_IS_OUT) {
bool value = flags & GPIOD_IS_OUT_ACTIVE;
if (flags & GPIOD_OPEN_DRAIN)
stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_OD);
stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_OD);
else
stm32_gpio_set_otype(regs, idx, STM32_GPIO_OTYPE_PP);
stm32_gpio_set_otype(regs, offset, STM32_GPIO_OTYPE_PP);
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_OUT);
writel(BSRR_BIT(idx, value), &regs->bsrr);
stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_OUT);
writel(BSRR_BIT(offset, value), &regs->bsrr);
} else if (flags & GPIOD_IS_IN) {
stm32_gpio_set_moder(regs, idx, STM32_GPIO_MODE_IN);
stm32_gpio_set_moder(regs, offset, STM32_GPIO_MODE_IN);
}
if (flags & GPIOD_PULL_UP)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_UP);
stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_UP);
else if (flags & GPIOD_PULL_DOWN)
stm32_gpio_set_pupd(regs, idx, STM32_GPIO_PUPD_DOWN);
stm32_gpio_set_pupd(regs, offset, STM32_GPIO_PUPD_DOWN);
return 0;
}
@@ -230,19 +204,17 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
{
struct stm32_gpio_priv *priv = dev_get_priv(dev);
struct stm32_gpio_regs *regs = priv->regs;
int idx;
ulong dir_flags = 0;
idx = stm32_offset_to_index(dev, offset);
if (idx < 0)
return idx;
if (!stm32_gpio_is_mapped(dev, offset))
return -ENXIO;
switch (stm32_gpio_get_moder(regs, idx)) {
switch (stm32_gpio_get_moder(regs, offset)) {
case STM32_GPIO_MODE_OUT:
dir_flags |= GPIOD_IS_OUT;
if (stm32_gpio_get_otype(regs, idx) == STM32_GPIO_OTYPE_OD)
if (stm32_gpio_get_otype(regs, offset) == STM32_GPIO_OTYPE_OD)
dir_flags |= GPIOD_OPEN_DRAIN;
if (readl(&regs->idr) & BIT(idx))
if (readl(&regs->idr) & BIT(offset))
dir_flags |= GPIOD_IS_OUT_ACTIVE;
break;
case STM32_GPIO_MODE_IN:
@@ -251,7 +223,7 @@ static int stm32_gpio_get_flags(struct udevice *dev, unsigned int offset,
default:
break;
}
switch (stm32_gpio_get_pupd(regs, idx)) {
switch (stm32_gpio_get_pupd(regs, offset)) {
case STM32_GPIO_PUPD_UP:
dir_flags |= GPIOD_PULL_UP;
break;
@@ -304,17 +276,14 @@ static int gpio_stm32_probe(struct udevice *dev)
if (!ret && args.args_count < 3)
return -EINVAL;
if (ret == -ENOENT) {
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
uc_priv->gpio_count = STM32_GPIOS_PER_BANK;
if (ret == -ENOENT)
priv->gpio_range = GENMASK(STM32_GPIOS_PER_BANK - 1, 0);
}
while (ret != -ENOENT) {
priv->gpio_range |= GENMASK(args.args[2] + args.args[0] - 1,
args.args[0]);
uc_priv->gpio_count += args.args[2];
ret = dev_read_phandle_with_args(dev, "gpio-ranges", NULL, 3,
++i, &args);
if (!ret && args.args_count < 3)

2
drivers/gpio/stm32_gpio_priv.h
View File

@@ -81,6 +81,4 @@ struct stm32_gpio_priv {
unsigned int gpio_range;
};
int stm32_offset_to_index(struct udevice *dev, unsigned int offset);
#endif /* _STM32_GPIO_PRIV_H_ */

167
drivers/phy/phy-stm32-usbphyc.c
View File

@@ -17,6 +17,8 @@
#include <usb.h>
#include <asm/io.h>
#include <dm/device_compat.h>
#include <dm/of_access.h>
#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <power/regulator.h>
@@ -24,6 +26,7 @@
/* USBPHYC registers */
#define STM32_USBPHYC_PLL 0x0
#define STM32_USBPHYC_MISC 0x8
#define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
/* STM32_USBPHYC_PLL bit fields */
#define PLLNDIV GENMASK(6, 0)
@@ -40,6 +43,26 @@
/* STM32_USBPHYC_MISC bit fields */
#define SWITHOST BIT(0)
/* STM32_USBPHYC_TUNE bit fields */
#define INCURREN BIT(0)
#define INCURRINT BIT(1)
#define LFSCAPEN BIT(2)
#define HSDRVSLEW BIT(3)
#define HSDRVDCCUR BIT(4)
#define HSDRVDCLEV BIT(5)
#define HSDRVCURINCR BIT(6)
#define FSDRVRFADJ BIT(7)
#define HSDRVRFRED BIT(8)
#define HSDRVCHKITRM GENMASK(12, 9)
#define HSDRVCHKZTRM GENMASK(14, 13)
#define OTPCOMP GENMASK(19, 15)
#define SQLCHCTL GENMASK(21, 20)
#define HDRXGNEQEN BIT(22)
#define HSRXOFF GENMASK(24, 23)
#define HSFALLPREEM BIT(25)
#define SHTCCTCTLPROT BIT(26)
#define STAGSEL BIT(27)
#define MAX_PHYS 2
/* max 100 us for PLL lock and 100 us for PHY init */
@@ -49,6 +72,62 @@
#define PLL_INFF_MIN_RATE 19200000 /* in Hz */
#define PLL_INFF_MAX_RATE 38400000 /* in Hz */
enum boosting_vals {
BOOST_1000_UA = 1000,
BOOST_2000_UA = 2000,
};
enum dc_level_vals {
DC_MINUS_5_TO_7_MV,
DC_PLUS_5_TO_7_MV,
DC_PLUS_10_TO_14_MV,
DC_MAX,
};
enum current_trim {
CUR_NOMINAL,
CUR_PLUS_1_56_PCT,
CUR_PLUS_3_12_PCT,
CUR_PLUS_4_68_PCT,
CUR_PLUS_6_24_PCT,
CUR_PLUS_7_8_PCT,
CUR_PLUS_9_36_PCT,
CUR_PLUS_10_92_PCT,
CUR_PLUS_12_48_PCT,
CUR_PLUS_14_04_PCT,
CUR_PLUS_15_6_PCT,
CUR_PLUS_17_16_PCT,
CUR_PLUS_19_01_PCT,
CUR_PLUS_20_58_PCT,
CUR_PLUS_22_16_PCT,
CUR_PLUS_23_73_PCT,
CUR_MAX,
};
enum impedance_trim {
IMP_NOMINAL,
IMP_MINUS_2_OHMS,
IMP_MINUS_4_OMHS,
IMP_MINUS_6_OHMS,
IMP_MAX,
};
enum squelch_level {
SQLCH_NOMINAL,
SQLCH_PLUS_7_MV,
SQLCH_MINUS_5_MV,
SQLCH_PLUS_14_MV,
SQLCH_MAX,
};
enum rx_offset {
NO_RX_OFFSET,
RX_OFFSET_PLUS_5_MV,
RX_OFFSET_PLUS_10_MV,
RX_OFFSET_MINUS_5_MV,
RX_OFFSET_MAX,
};
struct pll_params {
u8 ndiv;
u16 frac;
@@ -327,6 +406,90 @@ static int stm32_usbphyc_of_xlate(struct phy *phy,
return 0;
}
static void stm32_usbphyc_tuning(struct udevice *dev, ofnode node, u32 index)
{
struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
u32 reg = STM32_USBPHYC_TUNE(index);
u32 otpcomp, val, tune = 0;
int ret;
/* Backup OTP compensation code */
otpcomp = FIELD_GET(OTPCOMP, readl(usbphyc->base + reg));
ret = ofnode_read_u32(node, "st,current-boost-microamp", &val);
if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
val = (val == BOOST_2000_UA) ? 1 : 0;
tune |= INCURREN | FIELD_PREP(INCURRINT, val);
} else if (ret != -EINVAL) {
dev_warn(dev, "phy%d: invalid st,current-boost-microamp value\n", index);
}
if (!ofnode_read_bool(node, "st,no-lsfs-fb-cap"))
tune |= LFSCAPEN;
if (ofnode_read_bool(node, "st,decrease-hs-slew-rate"))
tune |= HSDRVSLEW;
ret = ofnode_read_u32(node, "st,tune-hs-dc-level", &val);
if (!ret && val < DC_MAX) {
if (val == DC_MINUS_5_TO_7_MV) {
tune |= HSDRVDCCUR;
} else {
val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
}
} else if (ret != -EINVAL) {
dev_warn(dev, "phy%d: invalid st,tune-hs-dc-level value\n", index);
}
if (ofnode_read_bool(node, "st,enable-fs-rftime-tuning"))
tune |= FSDRVRFADJ;
if (ofnode_read_bool(node, "st,enable-hs-rftime-reduction"))
tune |= HSDRVRFRED;
ret = ofnode_read_u32(node, "st,trim-hs-current", &val);
if (!ret && val < CUR_MAX)
tune |= FIELD_PREP(HSDRVCHKITRM, val);
else if (ret != -EINVAL)
dev_warn(dev, "phy%d: invalid st,trim-hs-current value\n", index);
ret = ofnode_read_u32(node, "st,trim-hs-impedance", &val);
if (!ret && val < IMP_MAX)
tune |= FIELD_PREP(HSDRVCHKZTRM, val);
else if (ret != -EINVAL)
dev_warn(dev, "phy%d: invalid trim-hs-impedance value\n", index);
ret = ofnode_read_u32(node, "st,tune-squelch-level", &val);
if (!ret && val < SQLCH_MAX)
tune |= FIELD_PREP(SQLCHCTL, val);
else if (ret != -EINVAL)
dev_warn(dev, "phy%d: invalid st,tune-squelch-level value\n", index);
if (ofnode_read_bool(node, "st,enable-hs-rx-gain-eq"))
tune |= HDRXGNEQEN;
ret = ofnode_read_u32(node, "st,tune-hs-rx-offset", &val);
if (!ret && val < RX_OFFSET_MAX)
tune |= FIELD_PREP(HSRXOFF, val);
else if (ret != -EINVAL)
dev_warn(dev, "phy%d: invalid st,tune-hs-rx-offset value\n", index);
if (ofnode_read_bool(node, "st,no-hs-ftime-ctrl"))
tune |= HSFALLPREEM;
if (!ofnode_read_bool(node, "st,no-lsfs-sc"))
tune |= SHTCCTCTLPROT;
if (ofnode_read_bool(node, "st,enable-hs-tx-staggering"))
tune |= STAGSEL;
/* Restore OTP compensation code */
tune |= FIELD_PREP(OTPCOMP, otpcomp);
writel(tune, usbphyc->base + reg);
}
static const struct phy_ops stm32_usbphyc_phy_ops = {
.init = stm32_usbphyc_phy_init,
.exit = stm32_usbphyc_phy_exit,
@@ -389,6 +552,10 @@ static int stm32_usbphyc_probe(struct udevice *dev)
phy_id, ofnode_get_name(node));
return -ENOENT;
}
/* Configure phy tuning */
stm32_usbphyc_tuning(dev, node, phy_id);
usbphyc_phy = usbphyc->phys + phy_id;
usbphyc_phy->init = false;
usbphyc_phy->powered = false;

20
drivers/pinctrl/pinctrl_stm32.c
View File

@@ -42,13 +42,12 @@ struct stm32_gpio_bank {
#ifndef CONFIG_SPL_BUILD
static char pin_name[PINNAME_SIZE];
#define PINMUX_MODE_COUNT 5
static const char * const pinmux_mode[PINMUX_MODE_COUNT] = {
"gpio input",
"gpio output",
"analog",
"unknown",
"alt function",
static const char * const pinmux_mode[GPIOF_COUNT] = {
[GPIOF_INPUT] = "gpio input",
[GPIOF_OUTPUT] = "gpio output",
[GPIOF_UNUSED] = "analog",
[GPIOF_UNKNOWN] = "unknown",
[GPIOF_FUNC] = "alt function",
};
static const char * const pinmux_bias[] = {
@@ -158,10 +157,7 @@ static struct udevice *stm32_pinctrl_get_gpio_dev(struct udevice *dev,
* we found the bank, convert pin selector to
* gpio bank index
*/
*idx = stm32_offset_to_index(gpio_bank->gpio_dev,
selector - pin_count);
if (IS_ERR_VALUE(*idx))
return NULL;
*idx = selector - pin_count;
return gpio_bank->gpio_dev;
}
@@ -221,8 +217,6 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev,
switch (mode) {
case GPIOF_UNKNOWN:
/* should never happen */
return -EINVAL;
case GPIOF_UNUSED:
snprintf(buf, size, "%s", pinmux_mode[mode]);
break;

14
drivers/ram/stm32mp1/stm32mp1_ddr.c
View File

@@ -653,10 +653,14 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
wait_sw_done_ack(ctl);
}
static void stm32mp1_asr_enable(struct ddr_info *priv)
static void stm32mp1_asr_enable(struct ddr_info *priv, const u32 pwrctl)
{
struct stm32mp1_ddrctl *ctl = priv->ctl;
/* SSR is the best we can do. */
if (!(pwrctl & DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE))
return;
clrsetbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCKMOD_MASK,
RCC_DDRITFCR_DDRCKMOD_ASR);
@@ -666,8 +670,12 @@ static void stm32mp1_asr_enable(struct ddr_info *priv)
writel(DDRCTRL_PWRTMG_POWERDOWN_TO_X32(0x10) |
DDRCTRL_PWRTMG_SELFREF_TO_X32(0x01),
&ctl->pwrtmg);
/* HSR we can do. */
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_EN_DFI_DRAM_CLK_DISABLE);
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
if (pwrctl & DDRCTRL_PWRCTL_SELFREF_EN) /* ASR we can do. */
setbits_le32(&ctl->pwrctl, DDRCTRL_PWRCTL_SELFREF_EN);
setbits_le32(&ctl->dfimisc, DDRCTRL_DFIMISC_DFI_INIT_COMPLETE_EN);
wait_sw_done_ack(ctl);
@@ -845,7 +853,7 @@ start:
config->c_reg.pwrctl);
/* Enable auto-self-refresh, which saves a bit of power at runtime. */
stm32mp1_asr_enable(priv);
stm32mp1_asr_enable(priv, config->c_reg.pwrctl);
/* enable uMCTL2 AXI port 0 and 1 */
setbits_le32(&priv->ctl->pctrl_0, DDRCTRL_PCTRL_N_PORT_EN);

247
drivers/video/stm32/stm32_ltdc.c
View File

@@ -25,8 +25,114 @@ struct stm32_ltdc_priv {
void __iomem *regs;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
const u32 *layer_regs;
const u32 *pix_fmt_hw;
u32 crop_x, crop_y, crop_w, crop_h;
u32 alpha;
u32 hw_version;
};
/* Layer register offsets */
static const u32 layer_regs_a0[] = {
0x80, /* L1 configuration 0 */
0x00, /* not available */
0x00, /* not available */
0x84, /* L1 control register */
0x88, /* L1 window horizontal position configuration */
0x8c, /* L1 window vertical position configuration */
0x90, /* L1 color keying configuration */
0x94, /* L1 pixel format configuration */
0x98, /* L1 constant alpha configuration */
0x9c, /* L1 default color configuration */
0xa0, /* L1 blending factors configuration */
0x00, /* not available */
0x00, /* not available */
0xac, /* L1 color frame buffer address */
0xb0, /* L1 color frame buffer length */
0xb4, /* L1 color frame buffer line number */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0xc4, /* L1 CLUT write */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00 /* not available */
};
static const u32 layer_regs_a1[] = {
0x80, /* L1 configuration 0 */
0x84, /* L1 configuration 1 */
0x00, /* L1 reload control */
0x88, /* L1 control register */
0x8c, /* L1 window horizontal position configuration */
0x90, /* L1 window vertical position configuration */
0x94, /* L1 color keying configuration */
0x98, /* L1 pixel format configuration */
0x9c, /* L1 constant alpha configuration */
0xa0, /* L1 default color configuration */
0xa4, /* L1 blending factors configuration */
0xa8, /* L1 burst length configuration */
0x00, /* not available */
0xac, /* L1 color frame buffer address */
0xb0, /* L1 color frame buffer length */
0xb4, /* L1 color frame buffer line number */
0xb8, /* L1 auxiliary frame buffer address 0 */
0xbc, /* L1 auxiliary frame buffer address 1 */
0xc0, /* L1 auxiliary frame buffer length */
0xc4, /* L1 auxiliary frame buffer line number */
0xc8, /* L1 CLUT write */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00, /* not available */
0x00 /* not available */
};
static const u32 layer_regs_a2[] = {
0x100, /* L1 configuration 0 */
0x104, /* L1 configuration 1 */
0x108, /* L1 reload control */
0x10c, /* L1 control register */
0x110, /* L1 window horizontal position configuration */
0x114, /* L1 window vertical position configuration */
0x118, /* L1 color keying configuration */
0x11c, /* L1 pixel format configuration */
0x120, /* L1 constant alpha configuration */
0x124, /* L1 default color configuration */
0x128, /* L1 blending factors configuration */
0x12c, /* L1 burst length configuration */
0x130, /* L1 planar configuration */
0x134, /* L1 color frame buffer address */
0x138, /* L1 color frame buffer length */
0x13c, /* L1 color frame buffer line number */
0x140, /* L1 auxiliary frame buffer address 0 */
0x144, /* L1 auxiliary frame buffer address 1 */
0x148, /* L1 auxiliary frame buffer length */
0x14c, /* L1 auxiliary frame buffer line number */
0x150, /* L1 CLUT write */
0x154, /* not available */
0x158, /* not available */
0x15c, /* not available */
0x160, /* not available */
0x164, /* not available */
0x168, /* not available */
0x16c, /* L1 Conversion YCbCr RGB 0 */
0x170, /* L1 Conversion YCbCr RGB 1 */
0x174, /* L1 Flexible Pixel Format 0 */
0x178 /* L1 Flexible Pixel Format 1 */
};
/* LTDC main registers */
@@ -49,26 +155,32 @@ struct stm32_ltdc_priv {
#define LTDC_CPSR 0x44 /* Current Position Status */
#define LTDC_CDSR 0x48 /* Current Display Status */
/* LTDC layer 1 registers */
#define LTDC_L1LC1R 0x80 /* L1 Layer Configuration 1 */
#define LTDC_L1LC2R 0x84 /* L1 Layer Configuration 2 */
#define LTDC_L1CR 0x84 /* L1 Control */
#define LTDC_L1WHPCR 0x88 /* L1 Window Hor Position Config */
#define LTDC_L1WVPCR 0x8C /* L1 Window Vert Position Config */
#define LTDC_L1CKCR 0x90 /* L1 Color Keying Configuration */
#define LTDC_L1PFCR 0x94 /* L1 Pixel Format Configuration */
#define LTDC_L1CACR 0x98 /* L1 Constant Alpha Config */
#define LTDC_L1DCCR 0x9C /* L1 Default Color Configuration */
#define LTDC_L1BFCR 0xA0 /* L1 Blend Factors Configuration */
#define LTDC_L1FBBCR 0xA4 /* L1 FrameBuffer Bus Control */
#define LTDC_L1AFBCR 0xA8 /* L1 AuxFB Control */
#define LTDC_L1CFBAR 0xAC /* L1 Color FrameBuffer Address */
#define LTDC_L1CFBLR 0xB0 /* L1 Color FrameBuffer Length */
#define LTDC_L1CFBLNR 0xB4 /* L1 Color FrameBuffer Line Nb */
#define LTDC_L1AFBAR 0xB8 /* L1 AuxFB Address */
#define LTDC_L1AFBLR 0xBC /* L1 AuxFB Length */
#define LTDC_L1AFBLNR 0xC0 /* L1 AuxFB Line Number */
#define LTDC_L1CLUTWR 0xC4 /* L1 CLUT Write */
/* Layer register offsets */
#define LTDC_L1C0R (priv->layer_regs[0]) /* L1 configuration 0 */
#define LTDC_L1C1R (priv->layer_regs[1]) /* L1 configuration 1 */
#define LTDC_L1RCR (priv->layer_regs[2]) /* L1 reload control */
#define LTDC_L1CR (priv->layer_regs[3]) /* L1 control register */
#define LTDC_L1WHPCR (priv->layer_regs[4]) /* L1 window horizontal position configuration */
#define LTDC_L1WVPCR (priv->layer_regs[5]) /* L1 window vertical position configuration */
#define LTDC_L1CKCR (priv->layer_regs[6]) /* L1 color keying configuration */
#define LTDC_L1PFCR (priv->layer_regs[7]) /* L1 pixel format configuration */
#define LTDC_L1CACR (priv->layer_regs[8]) /* L1 constant alpha configuration */
#define LTDC_L1DCCR (priv->layer_regs[9]) /* L1 default color configuration */
#define LTDC_L1BFCR (priv->layer_regs[10]) /* L1 blending factors configuration */
#define LTDC_L1BLCR (priv->layer_regs[11]) /* L1 burst length configuration */
#define LTDC_L1PCR (priv->layer_regs[12]) /* L1 planar configuration */
#define LTDC_L1CFBAR (priv->layer_regs[13]) /* L1 color frame buffer address */
#define LTDC_L1CFBLR (priv->layer_regs[14]) /* L1 color frame buffer length */
#define LTDC_L1CFBLNR (priv->layer_regs[15]) /* L1 color frame buffer line number */
#define LTDC_L1AFBA0R (priv->layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
#define LTDC_L1AFBA1R (priv->layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
#define LTDC_L1AFBLR (priv->layer_regs[18]) /* L1 auxiliary frame buffer length */
#define LTDC_L1AFBLNR (priv->layer_regs[19]) /* L1 auxiliary frame buffer line number */
#define LTDC_L1CLUTWR (priv->layer_regs[20]) /* L1 CLUT write */
#define LTDC_L1CYR0R (priv->layer_regs[27]) /* L1 Conversion YCbCr RGB 0 */
#define LTDC_L1CYR1R (priv->layer_regs[28]) /* L1 Conversion YCbCr RGB 1 */
#define LTDC_L1FPF0R (priv->layer_regs[29]) /* L1 Flexible Pixel Format 0 */
#define LTDC_L1FPF1R (priv->layer_regs[30]) /* L1 Flexible Pixel Format 1 */
/* Bit definitions */
#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
@@ -144,15 +256,60 @@ struct stm32_ltdc_priv {
#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
#define BF2_1CA 0x005 /* 1 - Constant Alpha */
#define NB_PF 8 /* Max nb of HW pixel format */
#define HWVER_10200 0x010200
#define HWVER_10300 0x010300
#define HWVER_20101 0x020101
#define HWVER_40100 0x040100
enum stm32_ltdc_pix_fmt {
PF_ARGB8888 = 0,
PF_RGB888,
PF_RGB565,
PF_ARGB1555,
PF_ARGB4444,
PF_L8,
PF_AL44,
PF_AL88
PF_ARGB8888 = 0, /* ARGB [32 bits] */
PF_ABGR8888, /* ABGR [32 bits] */
PF_BGRA8888, /* BGRA [32 bits] */
PF_RGBA8888, /* RGBA [32 bits] */
PF_RGB888, /* RGB [24 bits] */
PF_BGR565, /* RGB [16 bits] */
PF_RGB565, /* RGB [16 bits] */
PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
PF_AL88, /* Alpha:8 bits + indexed 8 bits [16 bits] */
PF_L8, /* Indexed 8 bits [8 bits] */
PF_NONE
};
static const enum stm32_ltdc_pix_fmt pix_fmt_a0[NB_PF] = {
PF_ARGB8888, /* 0x00 */
PF_RGB888, /* 0x01 */
PF_RGB565, /* 0x02 */
PF_ARGB1555, /* 0x03 */
PF_ARGB4444, /* 0x04 */
PF_L8, /* 0x05 */
PF_AL44, /* 0x06 */
PF_AL88 /* 0x07 */
};
static const enum stm32_ltdc_pix_fmt pix_fmt_a1[NB_PF] = {
PF_ARGB8888, /* 0x00 */
PF_RGB888, /* 0x01 */
PF_RGB565, /* 0x02 */
PF_RGBA8888, /* 0x03 */
PF_AL44, /* 0x04 */
PF_L8, /* 0x05 */
PF_ARGB1555, /* 0x06 */
PF_ARGB4444 /* 0x07 */
};
static const enum stm32_ltdc_pix_fmt pix_fmt_a2[NB_PF] = {
PF_ARGB8888, /* 0x00 */
PF_ABGR8888, /* 0x01 */
PF_RGBA8888, /* 0x02 */
PF_BGRA8888, /* 0x03 */
PF_RGB565, /* 0x04 */
PF_BGR565, /* 0x05 */
PF_RGB888, /* 0x06 */
PF_NONE /* 0x07 (flexible pixel format) */
};
/* TODO add more color format support */
@@ -255,7 +412,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
if (timings->flags & DISPLAY_FLAGS_DE_LOW)
val |= GCR_DEPOL;
if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
@@ -306,7 +463,16 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv *priv, ulong fb_addr)
/* Pixel format */
format = stm32_ltdc_get_pixel_format(priv->l2bpp);
clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
for (val = 0; val < NB_PF; val++)
if (priv->pix_fmt_hw[val] == format)
break;
if (val >= NB_PF) {
log_err("invalid pixel format\n");
return;
}
clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
/* Constant alpha value */
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
@@ -359,6 +525,27 @@ static int stm32_ltdc_probe(struct udevice *dev)
return ret;
}
priv->hw_version = readl(priv->regs + LTDC_IDR);
debug("%s: LTDC hardware 0x%x\n", __func__, priv->hw_version);
switch (priv->hw_version) {
case HWVER_10200:
case HWVER_10300:
priv->layer_regs = layer_regs_a0;
priv->pix_fmt_hw = pix_fmt_a0;
break;
case HWVER_20101:
priv->layer_regs = layer_regs_a1;
priv->pix_fmt_hw = pix_fmt_a1;
break;
case HWVER_40100:
priv->layer_regs = layer_regs_a2;
priv->pix_fmt_hw = pix_fmt_a2;
break;
default:
return -ENODEV;
}
ret = uclass_first_device_err(UCLASS_PANEL, &panel);
if (ret) {
if (ret != -ENODEV)