regulator: bd718x7: support ROHM BD71837 and BD71847 PMICs
BD71837 and BD71847 is PMIC intended for powering single-core, dual-core, and quad-core SoC’s such as NXP-i.MX 8M. BD71847 is used for example on NXP imx8mm EVK. Add regulator driver for ROHM BD71837 and BD71847 PMICs. BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version containing 6 bucks and 6 LDOs. Voltages for DVS bucks (1-4 on BD71837, 1 and 2 on BD71847) can be adjusted when regulators are enabled. For other bucks and LDOs we may have over- or undershooting if voltage is adjusted when regulator is enabled. Thus this is prevented by default. BD718x7 has a quirk which may leave power output disabled after reset if enable/disable state was controlled by SW. Thus the SW control is only allowed for BD71837 bucks 3 and 4 by default. The impact of this limitation must be evaluated board-by board and restrictions may need to be modified. (Linux driver get's these limitations from DT and we may want to implement same on u-Boot driver). Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Matti Vaittinen
Stefano Babic
parent
d70c0fce67
commit
21b02414f1
@ -3,6 +3,8 @@
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* Copyright 2018 NXP
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*/
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#define DEBUG
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#include <common.h>
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#include <errno.h>
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#include <dm.h>
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@ -15,15 +17,15 @@ DECLARE_GLOBAL_DATA_PTR;
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static const struct pmic_child_info pmic_children_info[] = {
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/* buck */
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{ .prefix = "b", .driver = BD71837_REGULATOR_DRIVER},
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{ .prefix = "b", .driver = BD718XX_REGULATOR_DRIVER},
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/* ldo */
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{ .prefix = "l", .driver = BD71837_REGULATOR_DRIVER},
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{ .prefix = "l", .driver = BD718XX_REGULATOR_DRIVER},
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{ },
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};
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static int bd71837_reg_count(struct udevice *dev)
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{
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return BD71837_REG_NUM;
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return BD718XX_MAX_REGISTER - 1;
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}
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static int bd71837_write(struct udevice *dev, uint reg, const uint8_t *buff,
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@ -54,7 +56,7 @@ static int bd71837_bind(struct udevice *dev)
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regulators_node = dev_read_subnode(dev, "regulators");
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if (!ofnode_valid(regulators_node)) {
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debug("%s: %s regulators subnode not found!", __func__,
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debug("%s: %s regulators subnode not found!\n", __func__,
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dev->name);
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return -ENXIO;
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}
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@ -69,6 +71,24 @@ static int bd71837_bind(struct udevice *dev)
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return 0;
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}
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static int bd718x7_probe(struct udevice *dev)
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{
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int ret;
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uint8_t mask = BD718XX_REGLOCK_PWRSEQ | BD718XX_REGLOCK_VREG;
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/* Unlock the PMIC regulator control before probing the children */
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ret = pmic_clrsetbits(dev, BD718XX_REGLOCK, mask, 0);
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if (ret) {
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debug("%s: %s Failed to unlock regulator control\n", __func__,
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dev->name);
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return ret;
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}
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debug("%s: '%s' - BD718x7 PMIC registers unlocked\n", __func__,
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dev->name);
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return 0;
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}
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static struct dm_pmic_ops bd71837_ops = {
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.reg_count = bd71837_reg_count,
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.read = bd71837_read,
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@ -76,7 +96,8 @@ static struct dm_pmic_ops bd71837_ops = {
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};
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static const struct udevice_id bd71837_ids[] = {
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{ .compatible = "rohm,bd71837", .data = 0x4b, },
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{ .compatible = "rohm,bd71837", .data = ROHM_CHIP_TYPE_BD71837, },
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{ .compatible = "rohm,bd71847", .data = ROHM_CHIP_TYPE_BD71847, },
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{ }
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};
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@ -85,5 +106,6 @@ U_BOOT_DRIVER(pmic_bd71837) = {
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.id = UCLASS_PMIC,
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.of_match = bd71837_ids,
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.bind = bd71837_bind,
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.probe = bd718x7_probe,
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.ops = &bd71837_ops,
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};
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@ -43,6 +43,23 @@ config REGULATOR_AS3722
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but does not yet support change voltages. Currently this must be
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done using direct register writes to the PMIC.
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config DM_REGULATOR_BD71837
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bool "Enable Driver Model for ROHM BD71837/BD71847 regulators"
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depends on DM_REGULATOR && DM_PMIC_BD71837
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help
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This config enables implementation of driver-model regulator uclass
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features for regulators on ROHM BD71837 and BD71847 PMICs.
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BD71837 contains 8 bucks and 7 LDOS. BD71847 is reduced version
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containing 6 bucks and 6 LDOs. The driver implements get/set api for
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value and enable.
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config SPL_DM_REGULATOR_BD71837
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bool "Enable Driver Model for ROHM BD71837/BD71847 regulators in SPL"
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depends on DM_REGULATOR_BD71837
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help
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This config enables implementation of driver-model regulator uclass
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features for regulators on ROHM BD71837 and BD71847 in SPL.
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config DM_REGULATOR_PFUZE100
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bool "Enable Driver Model for REGULATOR PFUZE100"
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depends on DM_REGULATOR && DM_PMIC_PFUZE100
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@ -9,6 +9,7 @@ obj-$(CONFIG_REGULATOR_ACT8846) += act8846.o
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obj-$(CONFIG_REGULATOR_AS3722) += as3722_regulator.o
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obj-$(CONFIG_DM_REGULATOR_MAX77686) += max77686.o
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obj-$(CONFIG_$(SPL_)DM_PMIC_PFUZE100) += pfuze100.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_BD71837) += bd71837.o
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obj-$(CONFIG_$(SPL_)REGULATOR_PWM) += pwm_regulator.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_FAN53555) += fan53555.o
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obj-$(CONFIG_$(SPL_)DM_REGULATOR_COMMON) += regulator_common.o
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468
drivers/power/regulator/bd71837.c
Normal file
468
drivers/power/regulator/bd71837.c
Normal file
@ -0,0 +1,468 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2019 ROHM Semiconductors
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*
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* ROHM BD71837 regulator driver
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*/
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#include <common.h>
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#include <dm.h>
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#include <power/bd71837.h>
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#include <power/pmic.h>
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#include <power/regulator.h>
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#define HW_STATE_CONTROL 0
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#define DEBUG
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/**
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* struct bd71837_vrange - describe linear range of voltages
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*
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* @min_volt: smallest voltage in range
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* @step: how much voltage changes at each selector step
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* @min_sel: smallest selector in the range
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* @max_sel: maximum selector in the range
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* @rangeval: register value used to select this range if selectible
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* ranges are supported
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*/
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struct bd71837_vrange {
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unsigned int min_volt;
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unsigned int step;
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u8 min_sel;
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u8 max_sel;
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u8 rangeval;
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};
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/**
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* struct bd71837_platdata - describe regulator control registers
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*
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* @name: name of the regulator. Used for matching the dt-entry
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* @enable_reg: register address used to enable/disable regulator
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* @enablemask: register mask used to enable/disable regulator
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* @volt_reg: register address used to configure regulator voltage
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* @volt_mask: register mask used to configure regulator voltage
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* @ranges: pointer to ranges of regulator voltages and matching register
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* values
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* @numranges: number of voltage ranges pointed by ranges
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* @rangemask: mask for selecting used ranges if multiple ranges are supported
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* @sel_mask: bit to toggle in order to transfer the register control to SW
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* @dvs: whether the voltage can be changed when regulator is enabled
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*/
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struct bd71837_platdata {
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const char *name;
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u8 enable_reg;
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u8 enablemask;
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u8 volt_reg;
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u8 volt_mask;
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struct bd71837_vrange *ranges;
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unsigned int numranges;
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u8 rangemask;
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u8 sel_mask;
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bool dvs;
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};
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#define BD_RANGE(_min, _vstep, _sel_low, _sel_hi, _range_sel) \
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{ \
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.min_volt = (_min), .step = (_vstep), .min_sel = (_sel_low), \
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.max_sel = (_sel_hi), .rangeval = (_range_sel) \
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}
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#define BD_DATA(_name, enreg, enmask, vreg, vmask, _range, rmask, _dvs, sel) \
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{ \
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.name = (_name), .enable_reg = (enreg), .enablemask = (enmask), \
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.volt_reg = (vreg), .volt_mask = (vmask), .ranges = (_range), \
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.numranges = ARRAY_SIZE(_range), .rangemask = (rmask), .dvs = (_dvs), \
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.sel_mask = (sel) \
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}
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static struct bd71837_vrange dvs_buck_vranges[] = {
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BD_RANGE(700000, 10000, 0, 0x3c, 0),
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BD_RANGE(1300000, 0, 0x3d, 0x3f, 0),
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};
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static struct bd71837_vrange bd71847_buck3_vranges[] = {
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BD_RANGE(700000, 100000, 0x00, 0x03, 0),
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BD_RANGE(1050000, 50000, 0x04, 0x05, 0),
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BD_RANGE(1200000, 150000, 0x06, 0x07, 0),
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BD_RANGE(550000, 50000, 0x0, 0x7, 0x40),
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BD_RANGE(675000, 100000, 0x0, 0x3, 0x80),
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BD_RANGE(1025000, 50000, 0x4, 0x5, 0x80),
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BD_RANGE(1175000, 150000, 0x6, 0x7, 0x80),
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};
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static struct bd71837_vrange bd71847_buck4_vranges[] = {
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BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
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BD_RANGE(2600000, 100000, 0x00, 0x03, 40),
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};
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static struct bd71837_vrange bd71837_buck5_vranges[] = {
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BD_RANGE(700000, 100000, 0, 0x3, 0),
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BD_RANGE(1050000, 50000, 0x04, 0x05, 0),
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BD_RANGE(1200000, 150000, 0x06, 0x07, 0),
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BD_RANGE(675000, 100000, 0x0, 0x3, 0x80),
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BD_RANGE(1025000, 50000, 0x04, 0x05, 0x80),
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BD_RANGE(1175000, 150000, 0x06, 0x07, 0x80),
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};
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static struct bd71837_vrange bd71837_buck6_vranges[] = {
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BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
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};
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static struct bd71837_vrange nodvs_buck3_vranges[] = {
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BD_RANGE(1605000, 90000, 0, 1, 0),
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BD_RANGE(1755000, 45000, 2, 4, 0),
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BD_RANGE(1905000, 45000, 5, 7, 0),
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};
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static struct bd71837_vrange nodvs_buck4_vranges[] = {
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BD_RANGE(800000, 10000, 0x00, 0x3C, 0),
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};
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static struct bd71837_vrange ldo1_vranges[] = {
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BD_RANGE(3000000, 100000, 0x00, 0x03, 0),
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BD_RANGE(1600000, 100000, 0x00, 0x03, 0x20),
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};
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static struct bd71837_vrange ldo2_vranges[] = {
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BD_RANGE(900000, 0, 0, 0, 0),
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BD_RANGE(800000, 0, 1, 1, 0),
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};
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static struct bd71837_vrange ldo3_vranges[] = {
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BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
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};
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static struct bd71837_vrange ldo4_vranges[] = {
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BD_RANGE(900000, 100000, 0x00, 0x09, 0),
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};
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static struct bd71837_vrange bd71837_ldo5_vranges[] = {
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BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
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};
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static struct bd71837_vrange bd71847_ldo5_vranges[] = {
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BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
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BD_RANGE(800000, 100000, 0x00, 0x0f, 0x20),
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};
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static struct bd71837_vrange ldo6_vranges[] = {
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BD_RANGE(900000, 100000, 0x00, 0x09, 0),
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};
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static struct bd71837_vrange ldo7_vranges[] = {
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BD_RANGE(1800000, 100000, 0x00, 0x0f, 0),
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};
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/*
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* We use enable mask 'HW_STATE_CONTROL' to indicate that this regulator
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* must not be enabled or disabled by SW. The typical use-case for BD71837
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* is powering NXP i.MX8. In this use-case we (for now) only allow control
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* for BUCK3 and BUCK4 which are not boot critical.
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*/
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static struct bd71837_platdata bd71837_reg_data[] = {
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/* Bucks 1-4 which support dynamic voltage scaling */
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BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
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BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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BD_DATA("BUCK2", BD718XX_BUCK2_CTRL, HW_STATE_CONTROL,
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BD718XX_BUCK2_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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BD_DATA("BUCK3", BD71837_BUCK3_CTRL, BD718XX_BUCK_EN,
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BD71837_BUCK3_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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BD_DATA("BUCK4", BD71837_BUCK4_CTRL, BD718XX_BUCK_EN,
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BD71837_BUCK4_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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/* Bucks 5-8 which do not support dynamic voltage scaling */
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BD_DATA("BUCK5", BD718XX_1ST_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_1ST_NODVS_BUCK_VOLT, BD718XX_1ST_NODVS_BUCK_MASK,
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bd71837_buck5_vranges, 0x80, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK6", BD718XX_2ND_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_2ND_NODVS_BUCK_VOLT, BD71837_BUCK6_MASK,
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bd71837_buck6_vranges, 0, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK7", BD718XX_3RD_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_3RD_NODVS_BUCK_VOLT, BD718XX_3RD_NODVS_BUCK_MASK,
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nodvs_buck3_vranges, 0, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK8", BD718XX_4TH_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_4TH_NODVS_BUCK_VOLT, BD718XX_4TH_NODVS_BUCK_MASK,
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nodvs_buck4_vranges, 0, false, BD718XX_BUCK_SEL),
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/* LDOs */
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BD_DATA("LDO1", BD718XX_LDO1_VOLT, HW_STATE_CONTROL, BD718XX_LDO1_VOLT,
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BD718XX_LDO1_MASK, ldo1_vranges, 0x20, false, BD718XX_LDO_SEL),
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BD_DATA("LDO2", BD718XX_LDO2_VOLT, HW_STATE_CONTROL, BD718XX_LDO2_VOLT,
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BD718XX_LDO2_MASK, ldo2_vranges, 0, false, BD718XX_LDO_SEL),
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BD_DATA("LDO3", BD718XX_LDO3_VOLT, HW_STATE_CONTROL, BD718XX_LDO3_VOLT,
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BD718XX_LDO3_MASK, ldo3_vranges, 0, false, BD718XX_LDO_SEL),
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BD_DATA("LDO4", BD718XX_LDO4_VOLT, HW_STATE_CONTROL, BD718XX_LDO4_VOLT,
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BD718XX_LDO4_MASK, ldo4_vranges, 0, false, BD718XX_LDO_SEL),
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BD_DATA("LDO5", BD718XX_LDO5_VOLT, HW_STATE_CONTROL, BD718XX_LDO5_VOLT,
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BD71837_LDO5_MASK, bd71837_ldo5_vranges, 0, false,
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BD718XX_LDO_SEL),
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BD_DATA("LDO6", BD718XX_LDO6_VOLT, HW_STATE_CONTROL, BD718XX_LDO6_VOLT,
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BD718XX_LDO6_MASK, ldo6_vranges, 0, false, BD718XX_LDO_SEL),
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BD_DATA("LDO7", BD71837_LDO7_VOLT, HW_STATE_CONTROL, BD71837_LDO7_VOLT,
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BD71837_LDO7_MASK, ldo7_vranges, 0, false, BD718XX_LDO_SEL),
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};
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static struct bd71837_platdata bd71847_reg_data[] = {
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/* Bucks 1 and 2 which support dynamic voltage scaling */
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BD_DATA("BUCK1", BD718XX_BUCK1_CTRL, HW_STATE_CONTROL,
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BD718XX_BUCK1_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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BD_DATA("BUCK2", BD718XX_BUCK2_CTRL, HW_STATE_CONTROL,
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BD718XX_BUCK2_VOLT_RUN, DVS_BUCK_RUN_MASK, dvs_buck_vranges, 0,
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true, BD718XX_BUCK_SEL),
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/* Bucks 3-6 which do not support dynamic voltage scaling */
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BD_DATA("BUCK3", BD718XX_1ST_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_1ST_NODVS_BUCK_VOLT, BD718XX_1ST_NODVS_BUCK_MASK,
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bd71847_buck3_vranges, 0xc0, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK4", BD718XX_2ND_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_2ND_NODVS_BUCK_VOLT, BD71837_BUCK6_MASK,
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bd71847_buck4_vranges, 0x40, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK5", BD718XX_3RD_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_3RD_NODVS_BUCK_VOLT, BD718XX_3RD_NODVS_BUCK_MASK,
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nodvs_buck3_vranges, 0, false, BD718XX_BUCK_SEL),
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BD_DATA("BUCK6", BD718XX_4TH_NODVS_BUCK_CTRL, HW_STATE_CONTROL,
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BD718XX_4TH_NODVS_BUCK_VOLT, BD718XX_4TH_NODVS_BUCK_MASK,
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nodvs_buck4_vranges, 0, false, BD718XX_BUCK_SEL),
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/* LDOs */
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BD_DATA("LDO1", BD718XX_LDO1_VOLT, HW_STATE_CONTROL, BD718XX_LDO1_VOLT,
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BD718XX_LDO1_MASK, ldo1_vranges, 0x20, false, BD718XX_LDO_SEL),
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BD_DATA("LDO2", BD718XX_LDO2_VOLT, HW_STATE_CONTROL, BD718XX_LDO2_VOLT,
|
||||
BD718XX_LDO2_MASK, ldo2_vranges, 0, false, BD718XX_LDO_SEL),
|
||||
BD_DATA("LDO3", BD718XX_LDO3_VOLT, HW_STATE_CONTROL, BD718XX_LDO3_VOLT,
|
||||
BD718XX_LDO3_MASK, ldo3_vranges, 0, false, BD718XX_LDO_SEL),
|
||||
BD_DATA("LDO4", BD718XX_LDO4_VOLT, HW_STATE_CONTROL, BD718XX_LDO4_VOLT,
|
||||
BD718XX_LDO4_MASK, ldo4_vranges, 0, false, BD718XX_LDO_SEL),
|
||||
BD_DATA("LDO5", BD718XX_LDO5_VOLT, HW_STATE_CONTROL, BD718XX_LDO5_VOLT,
|
||||
BD71847_LDO5_MASK, bd71847_ldo5_vranges, 0x20, false,
|
||||
BD718XX_LDO_SEL),
|
||||
BD_DATA("LDO6", BD718XX_LDO6_VOLT, HW_STATE_CONTROL, BD718XX_LDO6_VOLT,
|
||||
BD718XX_LDO6_MASK, ldo6_vranges, 0, false, BD718XX_LDO_SEL),
|
||||
};
|
||||
|
||||
static int vrange_find_value(struct bd71837_vrange *r, unsigned int sel,
|
||||
unsigned int *val)
|
||||
{
|
||||
if (!val || sel < r->min_sel || sel > r->max_sel)
|
||||
return -EINVAL;
|
||||
|
||||
*val = r->min_volt + r->step * (sel - r->min_sel);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vrange_find_selector(struct bd71837_vrange *r, int val,
|
||||
unsigned int *sel)
|
||||
{
|
||||
int ret = -EINVAL;
|
||||
int num_vals = r->max_sel - r->min_sel + 1;
|
||||
|
||||
if (val >= r->min_volt &&
|
||||
val <= r->min_volt + r->step * (num_vals - 1)) {
|
||||
if (r->step) {
|
||||
*sel = r->min_sel + ((val - r->min_volt) / r->step);
|
||||
ret = 0;
|
||||
} else {
|
||||
*sel = r->min_sel;
|
||||
ret = 0;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int bd71837_get_enable(struct udevice *dev)
|
||||
{
|
||||
int val;
|
||||
struct bd71837_platdata *plat = dev_get_platdata(dev);
|
||||
|
||||
/*
|
||||
* boot critical regulators on bd71837 must not be controlled by sw
|
||||
* due to the 'feature' which leaves power rails down if bd71837 is
|
||||
* reseted to snvs state. hence we can't get the state here.
|
||||
*
|
||||
* if we are alive it means we probably are on run state and
|
||||
* if the regulator can't be controlled we can assume it is
|
||||
* enabled.
|
||||
*/
|
||||
if (plat->enablemask == HW_STATE_CONTROL)
|
||||
return 1;
|
||||
|
||||
val = pmic_reg_read(dev->parent, plat->enable_reg);
|
||||
if (val < 0)
|
||||
return val;
|
||||
|
||||
return (val & plat->enablemask);
|
||||
}
|
||||
|
||||
static int bd71837_set_enable(struct udevice *dev, bool enable)
|
||||
{
|
||||
int val = 0;
|
||||
struct bd71837_platdata *plat = dev_get_platdata(dev);
|
||||
|
||||
/*
|
||||
* boot critical regulators on bd71837 must not be controlled by sw
|
||||
* due to the 'feature' which leaves power rails down if bd71837 is
|
||||
* reseted to snvs state. Hence we can't set the state here.
|
||||
*/
|
||||
if (plat->enablemask == HW_STATE_CONTROL)
|
||||
return -EINVAL;
|
||||
|
||||
if (enable)
|
||||
val = plat->enablemask;
|
||||
|
||||
return pmic_clrsetbits(dev->parent, plat->enable_reg, plat->enablemask,
|
||||
val);
|
||||
}
|
||||
|
||||
static int bd71837_set_value(struct udevice *dev, int uvolt)
|
||||
{
|
||||
unsigned int sel;
|
||||
unsigned int range;
|
||||
int i;
|
||||
int found = 0;
|
||||
struct bd71837_platdata *plat = dev_get_platdata(dev);
|
||||
|
||||
/*
|
||||
* An under/overshooting may occur if voltage is changed for other
|
||||
* regulators but buck 1,2,3 or 4 when regulator is enabled. Prevent
|
||||
* change to protect the HW
|
||||
*/
|
||||
if (!plat->dvs)
|
||||
if (bd71837_get_enable(dev)) {
|
||||
pr_err("Only DVS bucks can be changed when enabled\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < plat->numranges; i++) {
|
||||
struct bd71837_vrange *r = &plat->ranges[i];
|
||||
|
||||
found = !vrange_find_selector(r, uvolt, &sel);
|
||||
if (found) {
|
||||
unsigned int tmp;
|
||||
|
||||
/*
|
||||
* We require exactly the requested value to be
|
||||
* supported - this can be changed later if needed
|
||||
*/
|
||||
range = r->rangeval;
|
||||
found = !vrange_find_value(r, sel, &tmp);
|
||||
if (found && tmp == uvolt)
|
||||
break;
|
||||
found = 0;
|
||||
}
|
||||
}
|
||||
|
||||
if (!found)
|
||||
return -EINVAL;
|
||||
|
||||
sel <<= ffs(plat->volt_mask) - 1;
|
||||
|
||||
if (plat->rangemask)
|
||||
sel |= range;
|
||||
|
||||
return pmic_clrsetbits(dev->parent, plat->volt_reg, plat->volt_mask |
|
||||
plat->rangemask, sel);
|
||||
}
|
||||
|
||||
static int bd71837_get_value(struct udevice *dev)
|
||||
{
|
||||
unsigned int reg, range;
|
||||
unsigned int tmp;
|
||||
struct bd71837_platdata *plat = dev_get_platdata(dev);
|
||||
int i;
|
||||
|
||||
reg = pmic_reg_read(dev->parent, plat->volt_reg);
|
||||
if (((int)reg) < 0)
|
||||
return reg;
|
||||
|
||||
range = reg & plat->rangemask;
|
||||
|
||||
reg &= plat->volt_mask;
|
||||
reg >>= ffs(plat->volt_mask) - 1;
|
||||
|
||||
for (i = 0; i < plat->numranges; i++) {
|
||||
struct bd71837_vrange *r = &plat->ranges[i];
|
||||
|
||||
if (plat->rangemask && ((plat->rangemask & range) !=
|
||||
r->rangeval))
|
||||
continue;
|
||||
|
||||
if (!vrange_find_value(r, reg, &tmp))
|
||||
return tmp;
|
||||
}
|
||||
|
||||
pr_err("Unknown voltage value read from pmic\n");
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int bd71837_regulator_probe(struct udevice *dev)
|
||||
{
|
||||
struct bd71837_platdata *plat = dev_get_platdata(dev);
|
||||
int i, ret;
|
||||
struct dm_regulator_uclass_platdata *uc_pdata;
|
||||
int type;
|
||||
struct bd71837_platdata *init_data;
|
||||
int data_amnt;
|
||||
|
||||
type = dev_get_driver_data(dev_get_parent(dev));
|
||||
|
||||
switch (type) {
|
||||
case ROHM_CHIP_TYPE_BD71837:
|
||||
init_data = bd71837_reg_data;
|
||||
data_amnt = ARRAY_SIZE(bd71837_reg_data);
|
||||
break;
|
||||
case ROHM_CHIP_TYPE_BD71847:
|
||||
init_data = bd71847_reg_data;
|
||||
data_amnt = ARRAY_SIZE(bd71847_reg_data);
|
||||
break;
|
||||
default:
|
||||
debug("Unknown PMIC type\n");
|
||||
init_data = NULL;
|
||||
data_amnt = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
for (i = 0; i < data_amnt; i++) {
|
||||
if (!strcmp(dev->name, init_data[i].name)) {
|
||||
*plat = init_data[i];
|
||||
if (plat->enablemask != HW_STATE_CONTROL) {
|
||||
/*
|
||||
* Take the regulator under SW control. Ensure
|
||||
* the initial state matches dt flags and then
|
||||
* write the SEL bit
|
||||
*/
|
||||
uc_pdata = dev_get_uclass_platdata(dev);
|
||||
ret = bd71837_set_enable(dev,
|
||||
!!(uc_pdata->boot_on ||
|
||||
uc_pdata->always_on));
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return pmic_clrsetbits(dev->parent,
|
||||
plat->enable_reg,
|
||||
plat->sel_mask,
|
||||
plat->sel_mask);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
pr_err("Unknown regulator '%s'\n", dev->name);
|
||||
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
static const struct dm_regulator_ops bd71837_regulator_ops = {
|
||||
.get_value = bd71837_get_value,
|
||||
.set_value = bd71837_set_value,
|
||||
.get_enable = bd71837_get_enable,
|
||||
.set_enable = bd71837_set_enable,
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(bd71837_regulator) = {
|
||||
.name = BD718XX_REGULATOR_DRIVER,
|
||||
.id = UCLASS_REGULATOR,
|
||||
.ops = &bd71837_regulator_ops,
|
||||
.probe = bd71837_regulator_probe,
|
||||
.platdata_auto_alloc_size = sizeof(struct bd71837_platdata),
|
||||
};
|
||||
@ -1,62 +1,103 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
/* Copyright (C) 2018 ROHM Semiconductors */
|
||||
|
||||
#ifndef BD71837_H_
|
||||
#define BD71837_H_
|
||||
#ifndef BD718XX_H_
|
||||
#define BD718XX_H_
|
||||
|
||||
#define BD71837_REGULATOR_DRIVER "bd71837_regulator"
|
||||
#define BD718XX_REGULATOR_DRIVER "bd718x7_regulator"
|
||||
|
||||
enum {
|
||||
BD71837_REV = 0x00,
|
||||
BD71837_SWRESET = 0x01,
|
||||
BD71837_I2C_DEV = 0x02,
|
||||
BD71837_PWRCTRL0 = 0x03,
|
||||
BD71837_PWRCTRL1 = 0x04,
|
||||
BD71837_BUCK1_CTRL = 0x05,
|
||||
BD71837_BUCK2_CTRL = 0x06,
|
||||
BD71837_BUCK3_CTRL = 0x07,
|
||||
BD71837_BUCK4_CTRL = 0x08,
|
||||
BD71837_BUCK5_CTRL = 0x09,
|
||||
BD71837_BUCK6_CTRL = 0x0a,
|
||||
BD71837_BUCK7_CTRL = 0x0b,
|
||||
BD71837_BUCK8_CTRL = 0x0c,
|
||||
BD71837_BUCK1_VOLT_RUN = 0x0d,
|
||||
BD71837_BUCK1_VOLT_IDLE = 0x0e,
|
||||
BD71837_BUCK1_VOLT_SUSP = 0x0f,
|
||||
BD71837_BUCK2_VOLT_RUN = 0x10,
|
||||
BD71837_BUCK2_VOLT_IDLE = 0x11,
|
||||
BD71837_BUCK3_VOLT_RUN = 0x12,
|
||||
BD71837_BUCK4_VOLT_RUN = 0x13,
|
||||
BD71837_BUCK5_VOLT = 0x14,
|
||||
BD71837_BUCK6_VOLT = 0x15,
|
||||
BD71837_BUCK7_VOLT = 0x16,
|
||||
BD71837_BUCK8_VOLT = 0x17,
|
||||
BD71837_LDO1_VOLT = 0x18,
|
||||
BD71837_LDO2_VOLT = 0x19,
|
||||
BD71837_LDO3_VOLT = 0x1a,
|
||||
BD71837_LDO4_VOLT = 0x1b,
|
||||
BD71837_LDO5_VOLT = 0x1c,
|
||||
BD71837_LDO6_VOLT = 0x1d,
|
||||
BD71837_LDO7_VOLT = 0x1e,
|
||||
BD71837_TRANS_COND0 = 0x1f,
|
||||
BD71837_TRANS_COND1 = 0x20,
|
||||
BD71837_VRFAULTEN = 0x21,
|
||||
BD71837_MVRFLTMASK0 = 0x22,
|
||||
BD71837_MVRFLTMASK1 = 0x23,
|
||||
BD71837_MVRFLTMASK2 = 0x24,
|
||||
BD71837_RCVCFG = 0x25,
|
||||
BD71837_RCVNUM = 0x26,
|
||||
BD71837_PWRONCONFIG0 = 0x27,
|
||||
BD71837_PWRONCONFIG1 = 0x28,
|
||||
BD71837_RESETSRC = 0x29,
|
||||
BD71837_MIRQ = 0x2a,
|
||||
BD71837_IRQ = 0x2b,
|
||||
BD71837_IN_MON = 0x2c,
|
||||
BD71837_POW_STATE = 0x2d,
|
||||
BD71837_OUT32K = 0x2e,
|
||||
BD71837_REGLOCK = 0x2f,
|
||||
BD71837_MUXSW_EN = 0x30,
|
||||
BD71837_REG_NUM,
|
||||
ROHM_CHIP_TYPE_BD71837 = 0,
|
||||
ROHM_CHIP_TYPE_BD71847,
|
||||
ROHM_CHIP_TYPE_BD70528,
|
||||
ROHM_CHIP_TYPE_AMOUNT
|
||||
};
|
||||
|
||||
enum {
|
||||
BD718XX_REV = 0x00,
|
||||
BD718XX_SWRESET = 0x01,
|
||||
BD718XX_I2C_DEV = 0x02,
|
||||
BD718XX_PWRCTRL0 = 0x03,
|
||||
BD718XX_PWRCTRL1 = 0x04,
|
||||
BD718XX_BUCK1_CTRL = 0x05,
|
||||
BD718XX_BUCK2_CTRL = 0x06,
|
||||
BD71837_BUCK3_CTRL = 0x07,
|
||||
BD71837_BUCK4_CTRL = 0x08,
|
||||
BD718XX_1ST_NODVS_BUCK_CTRL = 0x09,
|
||||
BD718XX_2ND_NODVS_BUCK_CTRL = 0x0a,
|
||||
BD718XX_3RD_NODVS_BUCK_CTRL = 0x0b,
|
||||
BD718XX_4TH_NODVS_BUCK_CTRL = 0x0c,
|
||||
BD718XX_BUCK1_VOLT_RUN = 0x0d,
|
||||
BD718XX_BUCK1_VOLT_IDLE = 0x0e,
|
||||
BD718XX_BUCK1_VOLT_SUSP = 0x0f,
|
||||
BD718XX_BUCK2_VOLT_RUN = 0x10,
|
||||
BD718XX_BUCK2_VOLT_IDLE = 0x11,
|
||||
BD71837_BUCK3_VOLT_RUN = 0x12,
|
||||
BD71837_BUCK4_VOLT_RUN = 0x13,
|
||||
BD718XX_1ST_NODVS_BUCK_VOLT = 0x14,
|
||||
BD718XX_2ND_NODVS_BUCK_VOLT = 0x15,
|
||||
BD718XX_3RD_NODVS_BUCK_VOLT = 0x16,
|
||||
BD718XX_4TH_NODVS_BUCK_VOLT = 0x17,
|
||||
BD718XX_LDO1_VOLT = 0x18,
|
||||
BD718XX_LDO2_VOLT = 0x19,
|
||||
BD718XX_LDO3_VOLT = 0x1a,
|
||||
BD718XX_LDO4_VOLT = 0x1b,
|
||||
BD718XX_LDO5_VOLT = 0x1c,
|
||||
BD718XX_LDO6_VOLT = 0x1d,
|
||||
BD71837_LDO7_VOLT = 0x1e,
|
||||
BD718XX_TRANS_COND0 = 0x1f,
|
||||
BD718XX_TRANS_COND1 = 0x20,
|
||||
BD718XX_VRFAULTEN = 0x21,
|
||||
BD718XX_MVRFLTMASK0 = 0x22,
|
||||
BD718XX_MVRFLTMASK1 = 0x23,
|
||||
BD718XX_MVRFLTMASK2 = 0x24,
|
||||
BD718XX_RCVCFG = 0x25,
|
||||
BD718XX_RCVNUM = 0x26,
|
||||
BD718XX_PWRONCONFIG0 = 0x27,
|
||||
BD718XX_PWRONCONFIG1 = 0x28,
|
||||
BD718XX_RESETSRC = 0x29,
|
||||
BD718XX_MIRQ = 0x2a,
|
||||
BD718XX_IRQ = 0x2b,
|
||||
BD718XX_IN_MON = 0x2c,
|
||||
BD718XX_POW_STATE = 0x2d,
|
||||
BD718XX_OUT32K = 0x2e,
|
||||
BD718XX_REGLOCK = 0x2f,
|
||||
BD718XX_MUXSW_EN = 0x30,
|
||||
BD718XX_REG_OTPVER = 0xff,
|
||||
BD718XX_MAX_REGISTER = 0x100,
|
||||
};
|
||||
|
||||
#define BD718XX_REGLOCK_PWRSEQ 0x1
|
||||
#define BD718XX_REGLOCK_VREG 0x10
|
||||
|
||||
#define BD718XX_BUCK_EN 0x01
|
||||
#define BD718XX_LDO_EN 0x40
|
||||
#define BD718XX_BUCK_SEL 0x02
|
||||
#define BD718XX_LDO_SEL 0x80
|
||||
|
||||
#define DVS_BUCK_RUN_MASK 0x3f
|
||||
#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
|
||||
#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
|
||||
#define BD718XX_4TH_NODVS_BUCK_MASK 0x3f
|
||||
|
||||
#define BD71847_BUCK3_MASK 0x07
|
||||
#define BD71847_BUCK3_RANGE_MASK 0xc0
|
||||
#define BD71847_BUCK4_MASK 0x03
|
||||
#define BD71847_BUCK4_RANGE_MASK 0x40
|
||||
|
||||
#define BD71837_BUCK5_RANGE_MASK 0x80
|
||||
#define BD71837_BUCK6_MASK 0x03
|
||||
|
||||
#define BD718XX_LDO1_MASK 0x03
|
||||
#define BD718XX_LDO1_RANGE_MASK 0x20
|
||||
#define BD718XX_LDO2_MASK 0x20
|
||||
#define BD718XX_LDO3_MASK 0x0f
|
||||
#define BD718XX_LDO4_MASK 0x0f
|
||||
#define BD718XX_LDO6_MASK 0x0f
|
||||
|
||||
#define BD71837_LDO5_MASK 0x0f
|
||||
#define BD71847_LDO5_MASK 0x0f
|
||||
#define BD71847_LDO5_RANGE_MASK 0x20
|
||||
#define BD71837_LDO7_MASK 0x0f
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user