ARM: armv7: move CONFIG_ARMV7_PSCI to Kconfig
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms can select. Then, move CONFIG_ARMV7_PSCI, which is automatically enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled. Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -816,10 +816,13 @@ config TARGET_LS1021AQDS
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bool "Support ls1021aqds"
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select CPU_V7
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select SUPPORT_SPL
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select ARCH_SUPPORT_PSCI
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config TARGET_LS1021ATWR
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bool "Support ls1021atwr"
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select CPU_V7
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select SUPPORT_SPL
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select ARCH_SUPPORT_PSCI
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config TARGET_LS1043AQDS
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bool "Support ls1043aqds"
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@ -6,6 +6,9 @@ config CPU_V7_HAS_NONSEC
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config CPU_V7_HAS_VIRT
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bool
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config ARCH_SUPPORT_PSCI
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bool
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config ARMV7_NONSEC
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bool "Enable support for booting in non-secure mode" if EXPERT
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depends on CPU_V7_HAS_NONSEC
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@ -31,6 +34,13 @@ config ARMV7_VIRT
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---help---
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Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
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config ARMV7_PSCI
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bool "Enable PSCI support" if EXPERT
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depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
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default y
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help
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Say Y here to enable PSCI support.
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config ARMV7_LPAE
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bool "Use LPAE page table format" if EXPERT
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depends on CPU_V7
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@ -5,6 +5,7 @@ config MX7
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select ROM_UNIFIED_SECTIONS
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select CPU_V7_HAS_VIRT
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select CPU_V7_HAS_NONSEC
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select ARCH_SUPPORT_PSCI
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default y
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config MX7D
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@ -8,6 +8,7 @@ config TARGET_JETSON_TK1
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bool "NVIDIA Tegra124 Jetson TK1 board"
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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config TARGET_CEI_TK1_SOM
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bool "Colorado Engineering Inc Tegra124 TK1-som board"
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@ -8,6 +8,7 @@ config ARCH_UNIPHIER_32BIT
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select ARMV7_NONSEC
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select ARCH_SUPPORT_PSCI
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config ARCH_UNIPHIER_64BIT
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bool
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@ -37,6 +37,7 @@ config MACH_SUN6I
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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@ -46,6 +47,7 @@ config MACH_SUN7I
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN4I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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@ -55,6 +57,7 @@ config MACH_SUN8I_A23
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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@ -64,6 +67,7 @@ config MACH_SUN8I_A33
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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@ -79,6 +83,7 @@ config MACH_SUN8I_H3
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select CPU_V7
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select CPU_V7_HAS_NONSEC
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select CPU_V7_HAS_VIRT
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select ARCH_SUPPORT_PSCI
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select SUNXI_GEN_SUN6I
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select SUPPORT_SPL
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select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
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@ -60,7 +60,6 @@
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#include "tegra-common-usb-gadget.h"
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#include "tegra-common-post.h"
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#define CONFIG_ARMV7_PSCI 1
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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/* Reserve top 1M for secure RAM */
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#define CONFIG_ARMV7_SECURE_BASE 0xfff00000
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@ -9,7 +9,6 @@
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#define CONFIG_LS102XA
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
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@ -9,7 +9,6 @@
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#define CONFIG_LS102XA
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS
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@ -72,7 +72,6 @@
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#define CONFIG_CMD_FUSE
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#define CONFIG_MXC_OCOTP
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#define CONFIG_ARMV7_SECURE_BASE 0x00900000
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@ -22,7 +22,6 @@
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#define CONFIG_SUNXI_USB_PHYS 3
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#define CONFIG_ARMV7_PSCI 1
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
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@ -20,7 +20,6 @@
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#define CONFIG_SUNXI_USB_PHYS 3
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#define CONFIG_ARMV7_PSCI 1
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
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#define CONFIG_ARMV7_SECURE_MAX_SIZE (64 * 1024) /* 64 KB */
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@ -27,7 +27,6 @@
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#endif
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#ifndef CONFIG_MACH_SUN8I_A83T
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#define CONFIG_ARMV7_PSCI 1
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#if defined(CONFIG_MACH_SUN8I_A23)
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#define CONFIG_ARMV7_PSCI_NR_CPUS 2
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#elif defined(CONFIG_MACH_SUN8I_A33)
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@ -11,7 +11,6 @@
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#ifndef __CONFIG_UNIPHIER_COMMON_H__
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#define __CONFIG_UNIPHIER_COMMON_H__
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#define CONFIG_ARMV7_PSCI
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#define CONFIG_ARMV7_PSCI_1_0
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#define CONFIG_ARMV7_PSCI_NR_CPUS 4
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