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Merge branch 'master' of git://git.denx.de/u-boot-avr32

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This commit is contained in:
Tom Rini
2015-06-10 08:44:36 -04:00
parent b7160fabf1 b5614f9a7f
commit 204bb1eab6
32 changed files with 7 additions and 2025 deletions
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48
board/atmel/atstk1000/Kconfig
View File

@@ -13,51 +13,3 @@ config SYS_CONFIG_NAME
default "atstk1002"
endif
if TARGET_ATSTK1003
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1003"
endif
if TARGET_ATSTK1004
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1004"
endif
if TARGET_ATSTK1006
config SYS_BOARD
default "atstk1000"
config SYS_VENDOR
default "atmel"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "atstk1006"
endif

10
board/atmel/atstk1000/MAINTAINERS
View File

@@ -1,12 +1,6 @@
ATSTK1000 BOARD
#M: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
S: Orphan (since 2014-06)
M: Andreas Bießmann <andreas.biessmann@corscience.de>
S: Maintained
F: board/atmel/atstk1000/
F: include/configs/atstk1002.h
F: configs/atstk1002_defconfig
F: include/configs/atstk1003.h
F: configs/atstk1003_defconfig
F: include/configs/atstk1004.h
F: configs/atstk1004_defconfig
F: include/configs/atstk1006.h
F: configs/atstk1006_defconfig

23
board/atmel/atstk1000/atstk1000.c
View File

@@ -30,32 +30,12 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
};
static const struct sdram_config sdram_config = {
#if defined(CONFIG_ATSTK1006)
/* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 2,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 4,
.txsr = 7,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
#ifdef CONFIG_ATSTK1004
.data_bits = SDRAM_DATA_16BIT,
#else
.data_bits = SDRAM_DATA_32BIT,
#endif
#ifdef CONFIG_ATSTK1000_16MB_SDRAM
/* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
.row_bits = 12,
#else
/* MT48LC2M32B2P-5 (8 MB) on motherboard */
.row_bits = 11,
#endif
.col_bits = 8,
@@ -69,7 +49,6 @@ static const struct sdram_config sdram_config = {
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
#endif
};
int board_early_init_f(void)

15
board/earthlcd/favr-32-ezkit/Kconfig
View File

@@ -1,15 +0,0 @@
if TARGET_FAVR_32_EZKIT
config SYS_BOARD
default "favr-32-ezkit"
config SYS_VENDOR
default "earthlcd"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "favr-32-ezkit"
endif

6
board/earthlcd/favr-32-ezkit/MAINTAINERS
View File

@@ -1,6 +0,0 @@
FAVR-32-EZKIT BOARD
#M: Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
S: Orphan (since 2014-06)
F: board/earthlcd/favr-32-ezkit/
F: include/configs/favr-32-ezkit.h
F: configs/favr-32-ezkit_defconfig

9
board/earthlcd/favr-32-ezkit/Makefile
View File

@@ -1,9 +0,0 @@
#
# (C) Copyright 2001-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2008 Atmel Corporation
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := favr-32-ezkit.o flash.o

81
board/earthlcd/favr-32-ezkit/favr-32-ezkit.c
View File

@@ -1,81 +0,0 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
/* MT48LC4M32B2P-6 (16 MB) */
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 12,
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart3(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
return 0;
}
#if defined(CONFIG_MACB) && defined(CONFIG_CMD_NET)
int board_eth_init(bd_t *bi)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
bi->bi_phy_id[0]);
}
#endif

216
board/earthlcd/favr-32-ezkit/flash.c
View File

@@ -1,216 +0,0 @@
/*
* Copyright (C) 2008 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#ifdef CONFIG_FAVR32_EZKIT_EXT_FLASH
#include <asm/arch/cacheflush.h>
#include <asm/io.h>
#include <asm/sections.h>
DECLARE_GLOBAL_DATA_PTR;
flash_info_t flash_info[1];
static void flash_identify(uint16_t *flash, flash_info_t *info)
{
unsigned long flags;
flags = disable_interrupts();
dcache_flush_unlocked();
writew(0xaa, flash + 0x555);
writew(0x55, flash + 0xaaa);
writew(0x90, flash + 0x555);
info->flash_id = readl(flash);
writew(0xff, flash);
readw(flash);
if (flags)
enable_interrupts();
}
unsigned long flash_init(void)
{
unsigned long addr;
unsigned int i;
flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
flash_info[0].sector_count = 135;
flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
flash_info[0].start[i] = addr;
for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
flash_info[0].start[i] = addr;
return CONFIG_SYS_FLASH_SIZE;
}
void flash_print_info(flash_info_t *info)
{
printf("Flash: Vendor ID: 0x%02lx, Product ID: 0x%02lx\n",
info->flash_id >> 16, info->flash_id & 0xffff);
printf("Size: %ld MB in %d sectors\n",
info->size >> 10, info->sector_count);
}
int flash_erase(flash_info_t *info, int s_first, int s_last)
{
unsigned long flags;
unsigned long start_time;
uint16_t *fb, *sb;
unsigned int i;
int ret;
uint16_t status;
if ((s_first < 0) || (s_first > s_last)
|| (s_last >= info->sector_count)) {
puts("Error: first and/or last sector out of range\n");
return ERR_INVAL;
}
for (i = s_first; i < s_last; i++)
if (info->protect[i]) {
printf("Error: sector %d is protected\n", i);
return ERR_PROTECTED;
}
fb = (uint16_t *)uncached(info->start[0]);
dcache_flush_unlocked();
for (i = s_first; (i <= s_last) && !ctrlc(); i++) {
printf("Erasing sector %3d...", i);
sb = (uint16_t *)uncached(info->start[i]);
flags = disable_interrupts();
start_time = get_timer(0);
/* Unlock sector */
writew(0xaa, fb + 0x555);
writew(0x70, sb);
/* Erase sector */
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x80, fb + 0x555);
writew(0xaa, fb + 0x555);
writew(0x55, fb + 0xaaa);
writew(0x30, sb);
/* Wait for completion */
ret = ERR_OK;
do {
/* TODO: Timeout */
status = readw(sb);
} while ((status != 0xffff) && !(status & 0x28));
writew(0xf0, fb);
/*
* Make sure the command actually makes it to the bus
* before we re-enable interrupts.
*/
readw(fb);
if (flags)
enable_interrupts();
if (status != 0xffff) {
printf("Flash erase error at address 0x%p: 0x%02x\n",
sb, status);
ret = ERR_PROG_ERROR;
break;
}
}
if (ctrlc())
printf("User interrupt!\n");
return ERR_OK;
}
int write_buff(flash_info_t *info, uchar *src,
ulong addr, ulong count)
{
unsigned long flags;
uint16_t *base, *p, *s, *end;
uint16_t word, status, status1;
int ret = ERR_OK;
if (addr < info->start[0]
|| (addr + count) > (info->start[0] + info->size)
|| (addr + count) < addr) {
puts("Error: invalid address range\n");
return ERR_INVAL;
}
if (addr & 1 || count & 1 || (unsigned int)src & 1) {
puts("Error: misaligned source, destination or count\n");
return ERR_ALIGN;
}
base = (uint16_t *)uncached(info->start[0]);
end = (uint16_t *)uncached(addr + count);
flags = disable_interrupts();
dcache_flush_unlocked();
sync_write_buffer();
for (p = (uint16_t *)uncached(addr), s = (uint16_t *)src;
p < end && !ctrlc(); p++, s++) {
word = *s;
writew(0xaa, base + 0x555);
writew(0x55, base + 0xaaa);
writew(0xa0, base + 0x555);
writew(word, p);
sync_write_buffer();
/* Wait for completion */
status1 = readw(p);
do {
/* TODO: Timeout */
status = status1;
status1 = readw(p);
} while (((status ^ status1) & 0x40) /* toggled */
&& !(status1 & 0x28)); /* error bits */
/*
* We'll need to check once again for toggle bit
* because the toggle bit may stop toggling as I/O5
* changes to "1" (ref at49bv642.pdf p9)
*/
status1 = readw(p);
status = readw(p);
if ((status ^ status1) & 0x40) {
printf("Flash write error at address 0x%p: "
"0x%02x != 0x%02x\n",
p, status,word);
ret = ERR_PROG_ERROR;
writew(0xf0, base);
readw(base);
break;
}
writew(0xf0, base);
readw(base);
}
if (flags)
enable_interrupts();
return ret;
}
#endif /* CONFIG_FAVR32_EZKIT_EXT_FLASH */

15
board/mimc/mimc200/Kconfig
View File

@@ -1,15 +0,0 @@
if TARGET_MIMC200
config SYS_BOARD
default "mimc200"
config SYS_VENDOR
default "mimc"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "mimc200"
endif

6
board/mimc/mimc200/MAINTAINERS
View File

@@ -1,6 +0,0 @@
MIMC200 BOARD
M: Mark Jackson <mpfj@mimc.co.uk>
S: Maintained
F: board/mimc/mimc200/
F: include/configs/mimc200.h
F: configs/mimc200_defconfig

6
board/mimc/mimc200/Makefile
View File

@@ -1,6 +0,0 @@
#
# Copyright (C) 2005-2006 Atmel Corporation
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := mimc200.o

197
board/mimc/mimc200/mimc200.c
View File

@@ -1,197 +0,0 @@
/*
* Copyright (C) 2006 Atmel Corporation
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
#include <atmel_lcdc.h>
#include <lcd.h>
#include "../../../arch/avr32/cpu/hsmc3.h"
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT,
.phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
#if defined(CONFIG_LCD)
/* 480x272x16 @ 72 Hz */
vidinfo_t panel_info = {
.vl_col = 480, /* Number of columns */
.vl_row = 272, /* Number of rows */
.vl_clk = 5000000, /* pixel clock in ps */
.vl_sync = ATMEL_LCDC_INVCLK_INVERTED |
ATMEL_LCDC_INVLINE_INVERTED |
ATMEL_LCDC_INVFRAME_INVERTED,
.vl_bpix = LCD_COLOR16, /* Bits per pixel, BPP = 2^n */
.vl_tft = 1, /* 0 = passive, 1 = TFT */
.vl_hsync_len = 42, /* Length of horizontal sync */
.vl_left_margin = 1, /* Time from sync to picture */
.vl_right_margin = 1, /* Time from picture to sync */
.vl_vsync_len = 1, /* Length of vertical sync */
.vl_upper_margin = 12, /* Time from sync to picture */
.vl_lower_margin = 1, /* Time from picture to sync */
.mmio = LCDC_BASE, /* Memory mapped registers */
};
void lcd_enable(void)
{
}
void lcd_disable(void)
{
}
#endif
DECLARE_GLOBAL_DATA_PTR;
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_16BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 6,
.trp = 2,
.trcd = 2,
.tras = 6,
.txsr = 6,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
};
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
/* Enable 26 address bits and NCS2 */
portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
/* de-assert "force sys reset" pin */
portmux_select_gpio(PORTMUX_PORT_D, 1 << 15,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
/* init custom i/o */
/* cpu type inputs */
portmux_select_gpio(PORTMUX_PORT_E, (1 << 19) | (1 << 20) | (1 << 23),
PORTMUX_DIR_INPUT);
/* main board type inputs */
portmux_select_gpio(PORTMUX_PORT_B, (1 << 19) | (1 << 29),
PORTMUX_DIR_INPUT);
/* DEBUG input (use weak pullup) */
portmux_select_gpio(PORTMUX_PORT_E, 1 << 21,
PORTMUX_DIR_INPUT | PORTMUX_PULL_UP);
/* are we suppressing the console ? */
if (gpio_get_value(GPIO_PIN_PE(21)) == 1)
gd->flags |= (GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE);
/* reset phys */
portmux_select_gpio(PORTMUX_PORT_E, 1 << 24, PORTMUX_DIR_INPUT);
portmux_select_gpio(PORTMUX_PORT_C, 1 << 18,
PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH);
udelay(5000);
/* release phys reset */
gpio_set_value(GPIO_PIN_PC(18), 0); /* PHY RESET (Release) */
/* setup Data Flash chip select (NCS2) */
hsmc3_writel(MODE2, 0x20121003);
hsmc3_writel(CYCLE2, 0x000a0009);
hsmc3_writel(PULSE2, 0x0a060806);
hsmc3_writel(SETUP2, 0x00030102);
/* setup FRAM chip select (NCS3) */
hsmc3_writel(MODE3, 0x10120001);
hsmc3_writel(CYCLE3, 0x001e001d);
hsmc3_writel(PULSE3, 0x08040704);
hsmc3_writel(SETUP3, 0x02050204);
#if defined(CONFIG_MACB)
/* init macb0 pins */
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_LCD)
portmux_enable_lcdc(1);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
gd->bd->bi_phy_id[1] = 0x03;
return 0;
}
int board_postclk_init(void)
{
/* Use GCLK0 as 10MHz output */
gclk_enable_output(0, PORTMUX_DRIVE_LOW);
gclk_set_rate(0, GCLK_PARENT_OSC0, 10000000);
return 0;
}
/* SPI chip select control */
#ifdef CONFIG_ATMEL_SPI
#include <spi.h>
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return (bus == 0) && (cs == 0);
}
void spi_cs_activate(struct spi_slave *slave)
{
}
void spi_cs_deactivate(struct spi_slave *slave)
{
}
#endif /* CONFIG_ATMEL_SPI */
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bi)
{
macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
return 0;
}
#endif

15
board/miromico/hammerhead/Kconfig
View File

@@ -1,15 +0,0 @@
if TARGET_HAMMERHEAD
config SYS_BOARD
default "hammerhead"
config SYS_VENDOR
default "miromico"
config SYS_SOC
default "at32ap700x"
config SYS_CONFIG_NAME
default "hammerhead"
endif

6
board/miromico/hammerhead/MAINTAINERS
View File

@@ -1,6 +0,0 @@
HAMMERHEAD BOARD
M: Alex Raimondi <alex.raimondi@miromico.ch>
S: Maintained
F: board/miromico/hammerhead/
F: include/configs/hammerhead.h
F: configs/hammerhead_defconfig

6
board/miromico/hammerhead/Makefile
View File

@@ -1,6 +0,0 @@
#
# Copyright (C) 2008 Miromico AG
#
# SPDX-License-Identifier: GPL-2.0+
obj-y := hammerhead.o

91
board/miromico/hammerhead/hammerhead.c
View File

@@ -1,91 +0,0 @@
/*
* Copyright (C) 2008 Miromico AG
*
* Mostly copied form atmel ATNGW100 sources
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
#include <asm/arch/hmatrix.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mmu.h>
#include <asm/arch/portmux.h>
DECLARE_GLOBAL_DATA_PTR;
struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
{
.virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
.nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_NONE,
}, {
.virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
.nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
.phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
| MMU_VMR_CACHE_WRBACK,
},
};
static const struct sdram_config sdram_config = {
.data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.cas = 3,
.twr = 2,
.trc = 7,
.trp = 2,
.trcd = 2,
.tras = 5,
.txsr = 5,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
};
#ifdef CONFIG_CMD_NET
int board_eth_init(bd_t *bis)
{
return macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0,
bis->bi_phy_id[0]);
}
#endif
int board_early_init_f(void)
{
/* Enable SDRAM in the EBI mux */
hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH);
sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH);
#endif
#if defined(CONFIG_MMC)
portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x01;
return 0;
}
int board_postclk_init(void)
{
/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
gclk_enable_output(3, PORTMUX_DRIVE_LOW);
gclk_set_rate(3, GCLK_PARENT_OSC0, 25000000);
return 0;
}