Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
* 'master' of git://git.denx.de/u-boot-mpc85xx: powerpc/p3060: Add SoC related support for P3060 platform powerpc/85xx: Add support for setting up RAID engine liodns on P5020 powerpc/85xx: Refactor some defines out of corenet_ds.h fm-eth: Add ability for board code to disable a port powerpc/mpc8548: Add workaround for erratum NMG_LBC103 powerpc/mpc8548: Add workaround for erratum NMG_DDR120 powerpc/mpc85xxcds: Fix PCI speed powerpc/mpc8548cds: Fix booting message powerpc/p4080: Add support for secure boot flow powerpc/85xx: Add Secure Boot support on P1010RDB for NOR, NAND & SPIFLASH powerpc/85xx: Add PBL & SECUREBOOT support on P3041/P5020DS boards powerpc/p2041rdb: remove watch dog related codes powerpc/p2041rdb: updated description of cpld command powerpc/p2041rdb: add more ddr frequencies support powerpc/p2041rdb: set sysclk according to status of physical switch SW1 powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver powerpc/mpc8xxx: Add DDR2 to unified DDR driver powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps() powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en powerpc/85xx: Refactor P2041RDB to use common p_corenet files powerpc/85xx: refactor common P-Series CoreNet files for FSL boards powerpc/85xx: Enable CMD_REGINFO on corenet boards powerpc/85xx: p2041rdb - Remove unused 'execute' perm in TLB entries powerpc/85xx: Fix USB protocol definitions for P1020RDB powerpc/corenet_ds: Use separated speed tables for UDIMM and RDIMM powerpc/mpc8xxx: Move DDR RCW overriding to common code powerpc/mpc8xxx: Extend CWL table powerpc/85xx: Cleanup how SVR_MAJ() is defined on MPC8536 powerpc/85xx: Cleanup extern in corenet_ds board code powerpc/p2041rdb: Add ethernet support on P2041RDB board powerpc/85xx: Add networking support to P1023RDS powerpc/hydra: Add ethernet support on P5020/P3041 DS boards powerpc/85xx: Add FMan ethernet support to P4080DS powerpc/85xx: Add support for FMan ethernet in Independent mode powerpc/mpc8548cds: Cleanup mpc8548cds.c powerpc/mp: add support for discontiguous cores powerpc/85xx: corenet_ds - Remove unused 'execute' perm in TLB entries fdt: Add new fdt_create_phandle helper fdt: Rename fdt_create_phandle to fdt_set_phandle powerpc/85xx: Fix compile warnings/errors if CONFIG_SYS_DPAA_FMAN isn't set fsl_ifc: Add the workaround for erratum IFC A-003399(enabled on P1010) powerpc/P1010: Add workaround for erratum P1010-A003549 (related to IFC) fsl_ifc: Add the workaround for erratum IFC-A002769 (enable on P1010) powerpc/85xx: Expanding the window of CCSRBAR in AS=1 from 4k to 1M powerpc/85xx: Add NAND/NAND_SPL support to P1010RDB nand: Freescale Integrated Flash Controller NAND support powerpc/85xx: Add basic support for P1010RDB powerpc/85xx: Add support for new P102x/P2020 RDB style boards powerpc/85xx: relocate CCSR before creating the initial RAM area powerpc/85xx: introduce and document CONFIG_SYS_CCSRBAR macros powerpc/85xx: Enable internal USB UTMI PHY on p204x/p3041/p50x0 powerpc/85xx: Add ULPI and UTMI USB Phy support for P1010/P1014
This commit is contained in:
Wolfgang Denk
141
nand_spl/board/freescale/p1010rdb/Makefile
Normal file
141
nand_spl/board/freescale/p1010rdb/Makefile
Normal file
@@ -0,0 +1,141 @@
|
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
NAND_SPL := y
|
||||
CONFIG_SYS_TEXT_BASE_SPL := 0xff800000
|
||||
PAD_TO := 0xff802000
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
||||
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
|
||||
$(LDFLAGS_FINAL)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o resetvec.o ticks.o
|
||||
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
|
||||
nand_boot.o nand_boot_fsl_ifc.o ns16550.o tlb.o tlb_table.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(nandobj)board/$(BOARDDIR)
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
|
||||
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
$(obj)cache.c:
|
||||
@rm -f $(obj)cache.c
|
||||
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
|
||||
|
||||
$(obj)cpu_init_early.c:
|
||||
@rm -f $(obj)cpu_init_early.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
|
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|
||||
$(obj)cpu_init_nand.c:
|
||||
@rm -f $(obj)cpu_init_nand.c
|
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ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
|
||||
|
||||
$(obj)fsl_law.c:
|
||||
@rm -f $(obj)fsl_law.c
|
||||
ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
|
||||
|
||||
$(obj)law.c:
|
||||
@rm -f $(obj)law.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
|
||||
|
||||
$(obj)nand_boot_fsl_ifc.c:
|
||||
@rm -f $(obj)nand_boot_fsl_ifc.c
|
||||
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_ifc.c \
|
||||
$(obj)nand_boot_fsl_ifc.c
|
||||
|
||||
$(obj)ns16550.c:
|
||||
@rm -f $(obj)ns16550.c
|
||||
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)fixed_ivor.S:
|
||||
@rm -f $(obj)fixed_ivor.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
|
||||
|
||||
$(obj)start.S: $(obj)fixed_ivor.S
|
||||
@rm -f $(obj)start.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
|
||||
|
||||
$(obj)ticks.S:
|
||||
@rm -f $(obj)ticks.S
|
||||
ln -sf $(SRCTREE)/arch/powerpc/lib/ticks.S $(obj)ticks.S
|
||||
|
||||
$(obj)tlb.c:
|
||||
@rm -f $(obj)tlb.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
|
||||
|
||||
$(obj)tlb_table.c:
|
||||
@rm -f $(obj)tlb_table.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
|
||||
|
||||
ifneq ($(OBJTREE), $(SRCTREE))
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
|
||||
endif
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
130
nand_spl/board/freescale/p1010rdb/nand_boot.c
Normal file
130
nand_spl/board/freescale/p1010rdb/nand_boot.c
Normal file
@@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <mpc85xx.h>
|
||||
#include <asm/io.h>
|
||||
#include <ns16550.h>
|
||||
#include <nand.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
#include <asm/fsl_law.h>
|
||||
|
||||
#define udelay(x) { int j; for (j = 0; j < x * 10000; j++) isync(); }
|
||||
|
||||
unsigned long ddr_freq_mhz;
|
||||
|
||||
void sdram_init(void)
|
||||
{
|
||||
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
|
||||
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
|
||||
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
|
||||
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
|
||||
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
|
||||
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
|
||||
|
||||
if (ddr_freq_mhz < 700) {
|
||||
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667);
|
||||
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667);
|
||||
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667);
|
||||
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667);
|
||||
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667);
|
||||
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667);
|
||||
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667);
|
||||
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667);
|
||||
out_be32(&ddr->ddr_wrlvl_cntl,
|
||||
CONFIG_SYS_DDR_WRLVL_CONTROL_667);
|
||||
} else {
|
||||
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800);
|
||||
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800);
|
||||
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800);
|
||||
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800);
|
||||
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800);
|
||||
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800);
|
||||
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800);
|
||||
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800);
|
||||
out_be32(&ddr->ddr_wrlvl_cntl,
|
||||
CONFIG_SYS_DDR_WRLVL_CONTROL_800);
|
||||
}
|
||||
|
||||
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
|
||||
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
|
||||
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
|
||||
|
||||
/* mimic 500us delay, with busy isync() loop */
|
||||
udelay(100);
|
||||
|
||||
/* Let the controller go */
|
||||
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
|
||||
|
||||
set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio, ddr_ratio;
|
||||
unsigned long bus_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
ddr_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO;
|
||||
ddr_ratio = ddr_ratio >> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
|
||||
ddr_freq_mhz = (CONFIG_SYS_CLK_FREQ * ddr_ratio) / 0x1000000;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* Initialize the DDR3 */
|
||||
sdram_init();
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
137
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
Normal file
137
nand_spl/board/freescale/p1_p2_rdb_pc/Makefile
Normal file
@@ -0,0 +1,137 @@
|
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# Copyright 2011 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
NAND_SPL := y
|
||||
CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
|
||||
PAD_TO := 0xff801000
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
|
||||
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
|
||||
$(LDFLAGS) $(LDFLAGS_FINAL)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o resetvec.o
|
||||
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
|
||||
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(nandobj)board/$(BOARDDIR)
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
|
||||
$(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
$(obj)cache.c:
|
||||
@rm -f $(obj)cache.c
|
||||
ln -sf $(SRCTREE)/arch/powerpc/lib/cache.c $(obj)cache.c
|
||||
|
||||
$(obj)cpu_init_early.c:
|
||||
@rm -f $(obj)cpu_init_early.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_early.c $(obj)cpu_init_early.c
|
||||
|
||||
$(obj)cpu_init_nand.c:
|
||||
@rm -f $(obj)cpu_init_nand.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/cpu_init_nand.c $(obj)cpu_init_nand.c
|
||||
|
||||
$(obj)fsl_law.c:
|
||||
@rm -f $(obj)fsl_law.c
|
||||
ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
|
||||
|
||||
$(obj)law.c:
|
||||
@rm -f $(obj)law.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
|
||||
|
||||
$(obj)nand_boot_fsl_elbc.c:
|
||||
@rm -f $(obj)nand_boot_fsl_elbc.c
|
||||
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
|
||||
$(obj)nand_boot_fsl_elbc.c
|
||||
|
||||
$(obj)ns16550.c:
|
||||
@rm -f $(obj)ns16550.c
|
||||
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/$(CPUDIR)/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)fixed_ivor.S:
|
||||
@rm -f $(obj)fixed_ivor.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/fixed_ivor.S $(obj)fixed_ivor.S
|
||||
|
||||
$(obj)start.S: $(obj)fixed_ivor.S
|
||||
@rm -f $(obj)start.S
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/start.S $(obj)start.S
|
||||
|
||||
$(obj)tlb.c:
|
||||
@rm -f $(obj)tlb.c
|
||||
ln -sf $(SRCTREE)/$(CPUDIR)/tlb.c $(obj)tlb.c
|
||||
|
||||
$(obj)tlb_table.c:
|
||||
@rm -f $(obj)tlb_table.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
|
||||
|
||||
ifneq ($(OBJTREE), $(SRCTREE))
|
||||
$(obj)nand_boot.c:
|
||||
@rm -f $(obj)nand_boot.c
|
||||
ln -s $(SRCTREE)/nand_spl/board/$(BOARDDIR)/nand_boot.c $(obj)nand_boot.c
|
||||
endif
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
134
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
Normal file
134
nand_spl/board/freescale/p1_p2_rdb_pc/nand_boot.c
Normal file
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_ddr_sdram.h>
|
||||
|
||||
#define udelay(x) {int i, j; \
|
||||
for (i = 0; i < x; i++) \
|
||||
for (j = 0; j < 10000; j++) \
|
||||
; }
|
||||
|
||||
/*
|
||||
* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*/
|
||||
void sdram_init(void)
|
||||
{
|
||||
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
|
||||
|
||||
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
|
||||
out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
|
||||
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
|
||||
out_be32(&ddr->cs1_bnds, CONFIG_SYS_DDR_CS1_BNDS);
|
||||
out_be32(&ddr->cs1_config, CONFIG_SYS_DDR_CS1_CONFIG);
|
||||
#endif
|
||||
out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
||||
out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
||||
out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
||||
out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
||||
|
||||
out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2);
|
||||
out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1);
|
||||
out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2);
|
||||
|
||||
out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
||||
out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
|
||||
out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL);
|
||||
|
||||
out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
|
||||
out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
|
||||
out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL);
|
||||
out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CONTROL);
|
||||
|
||||
/* Set, but do not enable the memory */
|
||||
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN);
|
||||
|
||||
asm volatile("sync;isync");
|
||||
udelay(500);
|
||||
|
||||
/* Let the controller go */
|
||||
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
|
||||
|
||||
set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1);
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio, bus_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
#ifndef CONFIG_QE
|
||||
ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
#ifndef CONFIG_QE
|
||||
/* init DDR3 reset signal */
|
||||
out_be32(&pgpio->gpdir, 0x02000000);
|
||||
out_be32(&pgpio->gpodr, 0x00200000);
|
||||
out_be32(&pgpio->gpdat, 0x00000000);
|
||||
udelay(1000);
|
||||
out_be32(&pgpio->gpdat, 0x00200000);
|
||||
udelay(1000);
|
||||
out_be32(&pgpio->gpdir, 0x00000000);
|
||||
#endif
|
||||
|
||||
/* Initialize the DDR3 */
|
||||
sdram_init();
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
Reference in New Issue
Block a user