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Merge git://git.denx.de/u-boot-rockchip

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This adds a new firefly-rk3399 board, MIPI support for rk3399 and
rk3288, rk818 pmic support, mkimage improvements for rockchip and a few
other things.
This commit is contained in:
Tom Rini
2017-05-10 17:40:11 -04:00
parent 102d86552a 2085de57f3
commit 1f5541c881
78 changed files with 5917 additions and 613 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/rockchip/clk_rk3036.c
View File

@@ -228,11 +228,13 @@ static ulong rockchip_mmc_get_clk(struct rk3036_cru *cru, uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDIO:
case SCLK_SDIO:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
@@ -265,6 +267,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -272,6 +275,7 @@ static ulong rockchip_mmc_set_clk(struct rk3036_cru *cru, uint clk_general_rate,
(src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDIO:
case SCLK_SDIO:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -307,6 +311,7 @@ static ulong rk3036_clk_set_rate(struct clk *clk, ulong rate)
case 0 ... 63:
return 0;
case HCLK_EMMC:
case SCLK_EMMC:
new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
clk->id, rate);
break;

12
drivers/clk/rockchip/clk_rk3188.c
View File

@@ -269,14 +269,17 @@ static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]);
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break;
case HCLK_SDIO:
case SCLK_SDIO:
con = readl(&cru->cru_clksel_con[12]);
div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK;
break;
@@ -298,16 +301,19 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
src_clk_div << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
src_clk_div << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO:
case SCLK_SDIO:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO_DIV_MASK << SDIO_DIV_SHIFT,
src_clk_div << SDIO_DIV_SHIFT);
@@ -466,6 +472,9 @@ static ulong rk3188_clk_get_rate(struct clk *clk)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ,
clk->id);
break;
@@ -505,6 +514,9 @@ static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO:
new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ,
clk->id, rate);
break;

12
drivers/clk/rockchip/clk_rk3288.c
View File

@@ -513,16 +513,19 @@ static ulong rockchip_mmc_get_clk(struct rk3288_cru *cru, uint gclk_rate,
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> EMMC_PLL_SHIFT) & EMMC_PLL_MASK;
div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK;
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->cru_clksel_con[11]);
mux = (con >> MMC0_PLL_SHIFT) & MMC0_PLL_MASK;
div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK;
break;
case HCLK_SDIO0:
case SCLK_SDIO0:
con = readl(&cru->cru_clksel_con[12]);
mux = (con >> SDIO0_PLL_SHIFT) & SDIO0_PLL_MASK;
div = (con >> SDIO0_DIV_SHIFT) & SDIO0_DIV_MASK;
@@ -556,6 +559,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
}
switch (periph) {
case HCLK_EMMC:
case SCLK_EMMC:
rk_clrsetreg(&cru->cru_clksel_con[12],
EMMC_PLL_MASK << EMMC_PLL_SHIFT |
EMMC_DIV_MASK << EMMC_DIV_SHIFT,
@@ -563,6 +567,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
(src_clk_div - 1) << EMMC_DIV_SHIFT);
break;
case HCLK_SDMMC:
case SCLK_SDMMC:
rk_clrsetreg(&cru->cru_clksel_con[11],
MMC0_PLL_MASK << MMC0_PLL_SHIFT |
MMC0_DIV_MASK << MMC0_DIV_SHIFT,
@@ -570,6 +575,7 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint gclk_rate,
(src_clk_div - 1) << MMC0_DIV_SHIFT);
break;
case HCLK_SDIO0:
case SCLK_SDIO0:
rk_clrsetreg(&cru->cru_clksel_con[12],
SDIO0_PLL_MASK << SDIO0_PLL_SHIFT |
SDIO0_DIV_MASK << SDIO0_DIV_SHIFT,
@@ -662,6 +668,9 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO0:
new_rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
break;
case SCLK_SPI0:
@@ -706,6 +715,9 @@ static ulong rk3288_clk_set_rate(struct clk *clk, ulong rate)
case HCLK_EMMC:
case HCLK_SDMMC:
case HCLK_SDIO0:
case SCLK_EMMC:
case SCLK_SDMMC:
case SCLK_SDIO0:
new_rate = rockchip_mmc_set_clk(cru, gclk_rate, clk->id, rate);
break;
case SCLK_SPI0:

8
drivers/clk/rockchip/clk_rk3328.c
View File

@@ -397,9 +397,11 @@ static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -423,9 +425,11 @@ static ulong rk3328_mmc_set_clk(struct rk3328_cru *cru,
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
con_id = 30;
break;
case HCLK_EMMC:
case SCLK_EMMC:
con_id = 32;
break;
default:
@@ -483,6 +487,8 @@ static ulong rk3328_clk_get_rate(struct clk *clk)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
rate = rk3328_mmc_get_clk(priv->cru, clk->id);
break;
case SCLK_I2C0:
@@ -511,6 +517,8 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate)
return 0;
case HCLK_SDMMC:
case HCLK_EMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3328_mmc_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_I2C0:

131
drivers/clk/rockchip/clk_rk3399.c
View File

@@ -1,5 +1,6 @@
/*
* (C) Copyright 2015 Google, Inc
* (C) 2017 Theobroma Systems Design und Consulting GmbH
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -207,12 +208,15 @@ enum {
DCLK_VOP_DIV_CON_SHIFT = 0,
/* CLKSEL_CON58 */
CLK_SPI_PLL_SEL_MASK = 1,
CLK_SPI_PLL_SEL_CPLL = 0,
CLK_SPI_PLL_SEL_GPLL = 1,
CLK_SPI_PLL_DIV_CON_MASK = 0x7f,
CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
CLK_SPI5_PLL_SEL_SHIFT = 15,
CLK_SPI_PLL_SEL_WIDTH = 1,
CLK_SPI_PLL_SEL_MASK = ((1 < CLK_SPI_PLL_SEL_WIDTH) - 1),
CLK_SPI_PLL_SEL_CPLL = 0,
CLK_SPI_PLL_SEL_GPLL = 1,
CLK_SPI_PLL_DIV_CON_WIDTH = 7,
CLK_SPI_PLL_DIV_CON_MASK = ((1 << CLK_SPI_PLL_DIV_CON_WIDTH) - 1),
CLK_SPI5_PLL_DIV_CON_SHIFT = 8,
CLK_SPI5_PLL_SEL_SHIFT = 15,
/* CLKSEL_CON59 */
CLK_SPI1_PLL_SEL_SHIFT = 15,
@@ -602,7 +606,96 @@ static ulong rk3399_i2c_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
return -EINVAL;
}
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
return rk3399_i2c_get_clk(cru, clk_id);
}
/*
* RK3399 SPI clocks have a common divider-width (7 bits) and a single bit
* to select either CPLL or GPLL as the clock-parent. The location within
* the enclosing CLKSEL_CON (i.e. div_shift and sel_shift) are variable.
*/
struct spi_clkreg {
uint8_t reg; /* CLKSEL_CON[reg] register in CRU */
uint8_t div_shift;
uint8_t sel_shift;
};
/*
* The entries are numbered relative to their offset from SCLK_SPI0.
*
* Note that SCLK_SPI3 (which is configured via PMUCRU and requires different
* logic is not supported).
*/
static const struct spi_clkreg spi_clkregs[] = {
[0] = { .reg = 59,
.div_shift = CLK_SPI0_PLL_DIV_CON_SHIFT,
.sel_shift = CLK_SPI0_PLL_SEL_SHIFT, },
[1] = { .reg = 59,
.div_shift = CLK_SPI1_PLL_DIV_CON_SHIFT,
.sel_shift = CLK_SPI1_PLL_SEL_SHIFT, },
[2] = { .reg = 60,
.div_shift = CLK_SPI2_PLL_DIV_CON_SHIFT,
.sel_shift = CLK_SPI2_PLL_SEL_SHIFT, },
[3] = { .reg = 60,
.div_shift = CLK_SPI4_PLL_DIV_CON_SHIFT,
.sel_shift = CLK_SPI4_PLL_SEL_SHIFT, },
[4] = { .reg = 58,
.div_shift = CLK_SPI5_PLL_DIV_CON_SHIFT,
.sel_shift = CLK_SPI5_PLL_SEL_SHIFT, },
};
static inline u32 extract_bits(u32 val, unsigned width, unsigned shift)
{
return (val >> shift) & ((1 << width) - 1);
}
static ulong rk3399_spi_get_clk(struct rk3399_cru *cru, ulong clk_id)
{
const struct spi_clkreg *spiclk = NULL;
u32 div, val;
switch (clk_id) {
case SCLK_SPI0 ... SCLK_SPI5:
spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
break;
default:
error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
return -EINVAL;
}
val = readl(&cru->clksel_con[spiclk->reg]);
div = extract_bits(val, CLK_SPI_PLL_DIV_CON_WIDTH, spiclk->div_shift);
return DIV_TO_RATE(GPLL_HZ, div);
}
static ulong rk3399_spi_set_clk(struct rk3399_cru *cru, ulong clk_id, uint hz)
{
const struct spi_clkreg *spiclk = NULL;
int src_clk_div;
src_clk_div = RATE_TO_DIV(GPLL_HZ, hz);
assert(src_clk_div < 127);
switch (clk_id) {
case SCLK_SPI1 ... SCLK_SPI5:
spiclk = &spi_clkregs[clk_id - SCLK_SPI0];
break;
default:
error("%s: SPI clk-id %ld not supported\n", __func__, clk_id);
return -EINVAL;
}
rk_clrsetreg(&cru->clksel_con[spiclk->reg],
((CLK_SPI_PLL_DIV_CON_MASK << spiclk->div_shift) |
(CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)),
((src_clk_div << spiclk->div_shift) |
(CLK_SPI_PLL_SEL_GPLL << spiclk->sel_shift)));
return rk3399_spi_get_clk(cru, clk_id);
}
static ulong rk3399_vop_set_clk(struct rk3399_cru *cru, ulong clk_id, u32 hz)
@@ -654,6 +747,7 @@ static ulong rk3399_mmc_get_clk(struct rk3399_cru *cru, uint clk_id)
u32 div, con;
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
con = readl(&cru->clksel_con[16]);
break;
@@ -679,6 +773,7 @@ static ulong rk3399_mmc_set_clk(struct rk3399_cru *cru,
int aclk_emmc = 198*MHz;
switch (clk_id) {
case HCLK_SDMMC:
case SCLK_SDMMC:
/* Select clk_sdmmc source from GPLL by default */
src_clk_div = GPLL_HZ / set_rate;
@@ -768,6 +863,7 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
switch (clk->id) {
case 0 ... 63:
return 0;
case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
rate = rk3399_mmc_get_clk(priv->cru, clk->id);
@@ -780,9 +876,20 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
case SCLK_I2C7:
rate = rk3399_i2c_get_clk(priv->cru, clk->id);
break;
case SCLK_SPI0...SCLK_SPI5:
rate = rk3399_spi_get_clk(priv->cru, clk->id);
break;
case SCLK_UART0:
case SCLK_UART2:
return 24000000;
break;
case PCLK_HDMI_CTRL:
break;
case DCLK_VOP0:
case DCLK_VOP1:
break;
case PCLK_EFUSE1024NS:
break;
default:
return -ENOENT;
}
@@ -798,6 +905,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
switch (clk->id) {
case 0 ... 63:
return 0;
case HCLK_SDMMC:
case SCLK_SDMMC:
case SCLK_EMMC:
ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate);
@@ -814,6 +922,13 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_I2C7:
ret = rk3399_i2c_set_clk(priv->cru, clk->id, rate);
break;
case SCLK_SPI0...SCLK_SPI5:
ret = rk3399_spi_set_clk(priv->cru, clk->id, rate);
break;
case PCLK_HDMI_CTRL:
case PCLK_VIO_GRF:
/* the PCLK gates for video are enabled by default */
break;
case DCLK_VOP0:
case DCLK_VOP1:
ret = rk3399_vop_set_clk(priv->cru, clk->id, rate);
@@ -821,6 +936,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
case SCLK_DDRCLK:
ret = rk3399_ddr_set_clk(priv->cru, rate);
break;
case PCLK_EFUSE1024NS:
break;
default:
return -ENOENT;
}

32
drivers/misc/i2c_eeprom.c
View File

@@ -10,21 +10,41 @@
#include <i2c.h>
#include <i2c_eeprom.h>
static int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf,
int size)
int i2c_eeprom_read(struct udevice *dev, int offset, uint8_t *buf, int size)
{
const struct i2c_eeprom_ops *ops = device_get_ops(dev);
if (!ops->read)
return -ENOSYS;
return ops->read(dev, offset, buf, size);
}
int i2c_eeprom_write(struct udevice *dev, int offset, uint8_t *buf, int size)
{
const struct i2c_eeprom_ops *ops = device_get_ops(dev);
if (!ops->write)
return -ENOSYS;
return ops->write(dev, offset, buf, size);
}
static int i2c_eeprom_std_read(struct udevice *dev, int offset, uint8_t *buf,
int size)
{
return dm_i2c_read(dev, offset, buf, size);
}
static int i2c_eeprom_write(struct udevice *dev, int offset,
const uint8_t *buf, int size)
static int i2c_eeprom_std_write(struct udevice *dev, int offset,
const uint8_t *buf, int size)
{
return -ENODEV;
}
struct i2c_eeprom_ops i2c_eeprom_std_ops = {
.read = i2c_eeprom_read,
.write = i2c_eeprom_write,
.read = i2c_eeprom_std_read,
.write = i2c_eeprom_std_write,
};
static int i2c_eeprom_std_ofdata_to_platdata(struct udevice *dev)

24
drivers/mmc/rockchip_dw_mmc.c
View File

@@ -44,7 +44,7 @@ static uint rockchip_dwmmc_get_mmc_clk(struct dwmci_host *host, uint freq)
ret = clk_set_rate(&priv->clk, freq);
if (ret < 0) {
debug("%s: err=%d\n", __func__, ret);
printf("%s: err=%d\n", __func__, ret);
return ret;
}
@@ -76,9 +76,25 @@ static int rockchip_dwmmc_ofdata_to_platdata(struct udevice *dev)
return -EINVAL;
priv->fifo_mode = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),
"fifo-mode");
/*
* 'clock-freq-min-max' is deprecated
* (see https://github.com/torvalds/linux/commit/b023030f10573de738bbe8df63d43acab64c9f7b)
*/
if (fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev),
"clock-freq-min-max", priv->minmax, 2))
return -EINVAL;
"clock-freq-min-max", priv->minmax, 2)) {
int val = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
"max-frequency", -EINVAL);
if (val < 0)
return val;
priv->minmax[0] = 400000; /* 400 kHz */
priv->minmax[1] = val;
} else {
debug("%s: 'clock-freq-min-max' property was deprecated.\n",
__func__);
}
#endif
return 0;
}
@@ -109,7 +125,7 @@ static int rockchip_dwmmc_probe(struct udevice *dev)
if (ret < 0)
return ret;
#else
ret = clk_get_by_index(dev, 0, &priv->clk);
ret = clk_get_by_name(dev, "ciu", &priv->clk);
if (ret < 0)
return ret;
#endif

61
drivers/pinctrl/rockchip/pinctrl_rk3399.c
View File

@@ -145,7 +145,19 @@ static int pinctrl_rk3399_spi_config(struct rk3399_grf_regs *grf,
| GRF_SPI2TPM_CLK << GRF_GPIO2B3_SEL_SHIFT
| GRF_SPI2TPM_CSN0 << GRF_GPIO2B4_SEL_SHIFT);
break;
case PERIPH_ID_SPI5:
if (cs != 0)
goto err;
rk_clrsetreg(&grf->gpio2c_iomux,
GRF_GPIO2C4_SEL_MASK | GRF_GPIO2C5_SEL_MASK
| GRF_GPIO2C6_SEL_MASK | GRF_GPIO2C7_SEL_MASK,
GRF_SPI5EXPPLUS_RXD << GRF_GPIO2C4_SEL_SHIFT
| GRF_SPI5EXPPLUS_TXD << GRF_GPIO2C5_SEL_SHIFT
| GRF_SPI5EXPPLUS_CLK << GRF_GPIO2C6_SEL_SHIFT
| GRF_SPI5EXPPLUS_CSN0 << GRF_GPIO2C7_SEL_SHIFT);
break;
default:
printf("%s: spi_id %d is not supported.\n", __func__, spi_id);
goto err;
}
@@ -232,6 +244,41 @@ static void pinctrl_rk3399_gmac_config(struct rk3399_grf_regs *grf, int mmc_id)
rk_clrsetreg(&grf->gpio3c_iomux,
GRF_GPIO3C1_SEL_MASK,
GRF_MAC_TXCLK << GRF_GPIO3C1_SEL_SHIFT);
/* Set drive strength for GMAC tx io, value 3 means 13mA */
rk_clrsetreg(&grf->gpio3_e[0],
GRF_GPIO3A0_E_MASK | GRF_GPIO3A1_E_MASK |
GRF_GPIO3A4_E_MASK | GRF_GPIO3A5_E0_MASK,
3 << GRF_GPIO3A0_E_SHIFT |
3 << GRF_GPIO3A1_E_SHIFT |
3 << GRF_GPIO3A4_E_SHIFT |
1 << GRF_GPIO3A5_E0_SHIFT);
rk_clrsetreg(&grf->gpio3_e[1],
GRF_GPIO3A5_E12_MASK,
1 << GRF_GPIO3A5_E12_SHIFT);
rk_clrsetreg(&grf->gpio3_e[2],
GRF_GPIO3B4_E_MASK,
3 << GRF_GPIO3B4_E_SHIFT);
rk_clrsetreg(&grf->gpio3_e[4],
GRF_GPIO3C1_E_MASK,
3 << GRF_GPIO3C1_E_SHIFT);
}
#endif
#if !defined(CONFIG_SPL_BUILD)
static void pinctrl_rk3399_hdmi_config(struct rk3399_grf_regs *grf, int hdmi_id)
{
switch (hdmi_id) {
case PERIPH_ID_HDMI:
rk_clrsetreg(&grf->gpio4c_iomux,
GRF_GPIO4C0_SEL_MASK | GRF_GPIO4C1_SEL_MASK,
(GRF_HDMII2C_SCL << GRF_GPIO4C0_SEL_SHIFT) |
(GRF_HDMII2C_SDA << GRF_GPIO4C1_SEL_SHIFT));
break;
default:
debug("%s: hdmi_id = %d unsupported\n", __func__, hdmi_id);
break;
}
}
#endif
@@ -259,6 +306,9 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_SPI0:
case PERIPH_ID_SPI1:
case PERIPH_ID_SPI2:
case PERIPH_ID_SPI3:
case PERIPH_ID_SPI4:
case PERIPH_ID_SPI5:
pinctrl_rk3399_spi_config(priv->grf, priv->pmugrf, func, flags);
break;
case PERIPH_ID_UART0:
@@ -280,6 +330,11 @@ static int rk3399_pinctrl_request(struct udevice *dev, int func, int flags)
case PERIPH_ID_GMAC:
pinctrl_rk3399_gmac_config(priv->grf, func);
break;
#endif
#if !defined(CONFIG_SPL_BUILD)
case PERIPH_ID_HDMI:
pinctrl_rk3399_hdmi_config(priv->grf, func);
break;
#endif
default:
return -EINVAL;
@@ -307,6 +362,8 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
return PERIPH_ID_SPI1;
case 52:
return PERIPH_ID_SPI2;
case 132:
return PERIPH_ID_SPI5;
case 57:
return PERIPH_ID_I2C0;
case 59: /* Note strange order */
@@ -324,6 +381,10 @@ static int rk3399_pinctrl_get_periph_id(struct udevice *dev,
#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP)
case 12:
return PERIPH_ID_GMAC;
#endif
#if !defined(CONFIG_SPL_BUILD)
case 23:
return PERIPH_ID_HDMI;
#endif
}
#endif

6
drivers/power/pmic/Kconfig
View File

@@ -28,7 +28,7 @@ config SPL_PMIC_CHILDREN
This allows PMICs to support child devices (such as regulators) in
SPL. This adds quite a bit of code so if you are not using this
feature you can turn it off. In this case you may need a 'back door'
to call your regulator code (e.g. see rk808.c for direct functions
to call your regulator code (e.g. see rk8xx.c for direct functions
for use in SPL).
config PMIC_ACT8846
@@ -100,8 +100,8 @@ config PMIC_PM8916
Driver binding info: doc/device-tree-bindings/pmic/pm8916.txt
config PMIC_RK808
bool "Enable support for Rockchip PMIC RK808"
config PMIC_RK8XX
bool "Enable support for Rockchip PMIC RK8XX"
depends on DM_PMIC
---help---
The Rockchip RK808 PMIC provides four buck DC-DC convertors, 8 LDOs,

2
drivers/power/pmic/Makefile
View File

@@ -15,7 +15,7 @@ obj-$(CONFIG_PMIC_ACT8846) += act8846.o
obj-$(CONFIG_PMIC_AS3722) += as3722.o
obj-$(CONFIG_PMIC_MAX8997) += max8997.o
obj-$(CONFIG_PMIC_PM8916) += pm8916.o
obj-$(CONFIG_PMIC_RK808) += rk808.o
obj-$(CONFIG_PMIC_RK8XX) += rk8xx.o
obj-$(CONFIG_PMIC_RN5T567) += rn5t567.o
obj-$(CONFIG_PMIC_TPS65090) += tps65090.o
obj-$(CONFIG_PMIC_S5M8767) += s5m8767.o

52
drivers/power/pmic/rk808.c → drivers/power/pmic/rk8xx.c
View File

@@ -10,24 +10,24 @@
#include <errno.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <power/rk808_pmic.h>
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
DECLARE_GLOBAL_DATA_PTR;
static const struct pmic_child_info pmic_children_info[] = {
{ .prefix = "DCDC_REG", .driver = "rk808_buck"},
{ .prefix = "LDO_REG", .driver = "rk808_ldo"},
{ .prefix = "SWITCH_REG", .driver = "rk808_switch"},
{ .prefix = "DCDC_REG", .driver = "rk8xx_buck"},
{ .prefix = "LDO_REG", .driver = "rk8xx_ldo"},
{ .prefix = "SWITCH_REG", .driver = "rk8xx_switch"},
{ },
};
static int rk808_reg_count(struct udevice *dev)
static int rk8xx_reg_count(struct udevice *dev)
{
return RK808_NUM_OF_REGS;
}
static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
static int rk8xx_write(struct udevice *dev, uint reg, const uint8_t *buff,
int len)
{
int ret;
@@ -41,7 +41,7 @@ static int rk808_write(struct udevice *dev, uint reg, const uint8_t *buff,
return 0;
}
static int rk808_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
static int rk8xx_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
{
int ret;
@@ -55,7 +55,7 @@ static int rk808_read(struct udevice *dev, uint reg, uint8_t *buff, int len)
}
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
static int rk808_bind(struct udevice *dev)
static int rk8xx_bind(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
int regulators_node;
@@ -80,23 +80,39 @@ static int rk808_bind(struct udevice *dev)
}
#endif
static struct dm_pmic_ops rk808_ops = {
.reg_count = rk808_reg_count,
.read = rk808_read,
.write = rk808_write,
static int rk8xx_probe(struct udevice *dev)
{
struct rk8xx_priv *priv = dev_get_priv(dev);
uint8_t msb, lsb;
/* read Chip variant */
rk8xx_read(dev, ID_MSB, &msb, 1);
rk8xx_read(dev, ID_LSB, &lsb, 1);
priv->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
return 0;
}
static struct dm_pmic_ops rk8xx_ops = {
.reg_count = rk8xx_reg_count,
.read = rk8xx_read,
.write = rk8xx_write,
};
static const struct udevice_id rk808_ids[] = {
static const struct udevice_id rk8xx_ids[] = {
{ .compatible = "rockchip,rk808" },
{ .compatible = "rockchip,rk818" },
{ }
};
U_BOOT_DRIVER(pmic_rk808) = {
.name = "rk808 pmic",
U_BOOT_DRIVER(pmic_rk8xx) = {
.name = "rk8xx pmic",
.id = UCLASS_PMIC,
.of_match = rk808_ids,
.of_match = rk8xx_ids,
#if CONFIG_IS_ENABLED(PMIC_CHILDREN)
.bind = rk808_bind,
.bind = rk8xx_bind,
#endif
.ops = &rk808_ops,
.probe = rk8xx_probe,
.ops = &rk8xx_ops,
};

8
drivers/power/regulator/Kconfig
View File

@@ -76,11 +76,11 @@ config DM_REGULATOR_GPIO
features for gpio regulators. The driver implements get/set for
voltage value.
config REGULATOR_RK808
bool "Enable driver for RK808 regulators"
depends on DM_REGULATOR && PMIC_RK808
config REGULATOR_RK8XX
bool "Enable driver for RK8XX regulators"
depends on DM_REGULATOR && PMIC_RK8XX
---help---
Enable support for the regulator functions of the RK808 PMIC. The
Enable support for the regulator functions of the RK8XX PMIC. The
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.

2
drivers/power/regulator/Makefile
View File

@@ -12,7 +12,7 @@ obj-$(CONFIG_DM_REGULATOR_PFUZE100) += pfuze100.o
obj-$(CONFIG_REGULATOR_PWM) += pwm_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_FIXED) += fixed.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_GPIO) += gpio-regulator.o
obj-$(CONFIG_REGULATOR_RK808) += rk808.o
obj-$(CONFIG_REGULATOR_RK8XX) += rk8xx.o
obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o
obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o
obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o

16
drivers/power/regulator/pwm_regulator.c
View File

@@ -24,6 +24,12 @@ struct pwm_regulator_info {
int pwm_id;
/* the period of one PWM cycle */
int period_ns;
/*
* the polarity of one PWM
* 0: normal polarity
* 1: inverted polarity
*/
bool polarity;
struct udevice *pwm;
/* initialize voltage of regulator */
unsigned int init_voltage;
@@ -49,7 +55,7 @@ static int pwm_voltage_to_duty_cycle_percentage(struct udevice *dev, int req_uV)
int max_uV = priv->max_voltage;
int diff = max_uV - min_uV;
return 100 - (((req_uV * 100) - (min_uV * 100)) / diff);
return ((req_uV * 100) - (min_uV * 100)) / diff;
}
static int pwm_regulator_get_voltage(struct udevice *dev)
@@ -67,6 +73,12 @@ static int pwm_regulator_set_voltage(struct udevice *dev, int uvolt)
duty_cycle = pwm_voltage_to_duty_cycle_percentage(dev, uvolt);
ret = pwm_set_invert(priv->pwm, priv->pwm_id, priv->polarity);
if (ret) {
dev_err(dev, "Failed to init PWM\n");
return ret;
}
ret = pwm_set_config(priv->pwm, priv->pwm_id,
(priv->period_ns / 100) * duty_cycle, priv->period_ns);
if (ret) {
@@ -97,9 +109,9 @@ static int pwm_regulator_ofdata_to_platdata(struct udevice *dev)
debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
return ret;
}
/* TODO: pwm_id here from device tree if needed */
priv->period_ns = args.args[1];
priv->polarity = args.args[2];
priv->init_voltage = fdtdec_get_int(blob, node,
"regulator-init-microvolt", -1);

142
drivers/power/regulator/rk808.c → drivers/power/regulator/rk8xx.c
View File

@@ -12,7 +12,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <power/rk808_pmic.h>
#include <power/rk8xx_pmic.h>
#include <power/pmic.h>
#include <power/regulator.h>
@@ -20,36 +20,88 @@
#define ENABLE_DRIVER
#endif
struct rk808_reg_info {
/* Field Definitions */
#define RK808_BUCK_VSEL_MASK 0x3f
#define RK808_BUCK4_VSEL_MASK 0xf
#define RK808_LDO_VSEL_MASK 0x1f
#define RK818_BUCK_VSEL_MASK 0x3f
#define RK818_BUCK4_VSEL_MASK 0x1f
#define RK818_LDO_VSEL_MASK 0x1f
#define RK818_LDO3_ON_VSEL_MASK 0xf
#define RK818_BOOST_ON_VSEL_MASK 0xe0
struct rk8xx_reg_info {
uint min_uv;
uint step_uv;
s8 vsel_reg;
u8 vsel_bits;
u8 vsel_mask;
};
static const struct rk808_reg_info rk808_buck[] = {
{ 712500, 12500, REG_BUCK1_ON_VSEL, 6, },
{ 712500, 12500, REG_BUCK2_ON_VSEL, 6, },
{ 712500, 12500, -1, 6, },
{ 1800000, 100000, REG_BUCK4_ON_VSEL, 4, },
static const struct rk8xx_reg_info rk808_buck[] = {
{ 712500, 12500, REG_BUCK1_ON_VSEL, RK808_BUCK_VSEL_MASK, },
{ 712500, 12500, REG_BUCK2_ON_VSEL, RK808_BUCK_VSEL_MASK, },
{ 712500, 12500, -1, RK808_BUCK_VSEL_MASK, },
{ 1800000, 100000, REG_BUCK4_ON_VSEL, RK808_BUCK4_VSEL_MASK, },
};
static const struct rk808_reg_info rk808_ldo[] = {
{ 1800000, 100000, LDO1_ON_VSEL, 5, },
{ 1800000, 100000, LDO2_ON_VSEL, 5, },
{ 800000, 100000, LDO3_ON_VSEL, 4, },
{ 1800000, 100000, LDO4_ON_VSEL, 5, },
{ 1800000, 100000, LDO5_ON_VSEL, 5, },
{ 800000, 100000, LDO6_ON_VSEL, 5, },
{ 800000, 100000, LDO7_ON_VSEL, 5, },
{ 1800000, 100000, LDO8_ON_VSEL, 5, },
static const struct rk8xx_reg_info rk808_ldo[] = {
{ 1800000, 100000, REG_LDO1_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO2_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO3_ON_VSEL, RK808_BUCK4_VSEL_MASK, },
{ 1800000, 100000, REG_LDO4_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO5_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO6_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO7_ON_VSEL, RK808_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO8_ON_VSEL, RK808_LDO_VSEL_MASK, },
};
static const struct rk8xx_reg_info rk818_buck[] = {
{ 712500, 12500, REG_BUCK1_ON_VSEL, RK818_BUCK_VSEL_MASK, },
{ 712500, 12500, REG_BUCK2_ON_VSEL, RK818_BUCK_VSEL_MASK, },
{ 712500, 12500, -1, RK818_BUCK_VSEL_MASK, },
{ 1800000, 100000, REG_BUCK4_ON_VSEL, RK818_BUCK4_VSEL_MASK, },
};
static const struct rk8xx_reg_info rk818_ldo[] = {
{ 1800000, 100000, REG_LDO1_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO2_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO3_ON_VSEL, RK818_LDO3_ON_VSEL_MASK, },
{ 1800000, 100000, REG_LDO4_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO5_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO6_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 800000, 100000, REG_LDO7_ON_VSEL, RK818_LDO_VSEL_MASK, },
{ 1800000, 100000, REG_LDO8_ON_VSEL, RK818_LDO_VSEL_MASK, },
};
static const struct rk8xx_reg_info *get_buck_reg(struct udevice *pmic,
int num)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
switch (priv->variant) {
case RK818_ID:
return &rk818_buck[num];
default:
return &rk808_buck[num];
}
}
static const struct rk8xx_reg_info *get_ldo_reg(struct udevice *pmic,
int num)
{
struct rk8xx_priv *priv = dev_get_priv(pmic);
switch (priv->variant) {
case RK818_ID:
return &rk818_ldo[num - 1];
default:
return &rk808_ldo[num - 1];
}
}
static int _buck_set_value(struct udevice *pmic, int buck, int uvolt)
{
const struct rk808_reg_info *info = &rk808_buck[buck - 1];
int mask = (1 << info->vsel_bits) - 1;
const struct rk8xx_reg_info *info = get_buck_reg(pmic, buck - 1);
int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
@@ -69,7 +121,7 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
buck--;
mask = 1 << buck;
if (enable) {
ret = pmic_clrsetbits(pmic, DCDC_ILMAX, 0, 3 << (buck * 2));
ret = pmic_clrsetbits(pmic, REG_DCDC_ILMAX, 0, 3 << (buck * 2));
if (ret)
return ret;
ret = pmic_clrsetbits(pmic, REG_DCDC_UV_ACT, 1 << buck, 0);
@@ -84,8 +136,8 @@ static int _buck_set_enable(struct udevice *pmic, int buck, bool enable)
static int buck_get_value(struct udevice *dev)
{
int buck = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_buck[buck];
int mask = (1 << info->vsel_bits) - 1;
const struct rk8xx_reg_info *info = get_buck_reg(dev->parent, buck);
int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == -1)
@@ -130,8 +182,8 @@ static bool buck_get_enable(struct udevice *dev)
static int ldo_get_value(struct udevice *dev)
{
int ldo = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_ldo[ldo];
int mask = (1 << info->vsel_bits) - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo);
int mask = info->vsel_mask;
int ret, val;
if (info->vsel_reg == -1)
@@ -147,8 +199,8 @@ static int ldo_get_value(struct udevice *dev)
static int ldo_set_value(struct udevice *dev, int uvolt)
{
int ldo = dev->driver_data - 1;
const struct rk808_reg_info *info = &rk808_ldo[ldo];
int mask = (1 << info->vsel_bits) - 1;
const struct rk8xx_reg_info *info = get_ldo_reg(dev->parent, ldo);
int mask = info->vsel_mask;
int val;
if (info->vsel_reg == -1)
@@ -212,7 +264,7 @@ static bool switch_get_enable(struct udevice *dev)
return ret & mask ? true : false;
}
static int rk808_buck_probe(struct udevice *dev)
static int rk8xx_buck_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
@@ -224,7 +276,7 @@ static int rk808_buck_probe(struct udevice *dev)
return 0;
}
static int rk808_ldo_probe(struct udevice *dev)
static int rk8xx_ldo_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
@@ -236,7 +288,7 @@ static int rk808_ldo_probe(struct udevice *dev)
return 0;
}
static int rk808_switch_probe(struct udevice *dev)
static int rk8xx_switch_probe(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
@@ -248,48 +300,48 @@ static int rk808_switch_probe(struct udevice *dev)
return 0;
}
static const struct dm_regulator_ops rk808_buck_ops = {
static const struct dm_regulator_ops rk8xx_buck_ops = {
.get_value = buck_get_value,
.set_value = buck_set_value,
.get_enable = buck_get_enable,
.set_enable = buck_set_enable,
};
static const struct dm_regulator_ops rk808_ldo_ops = {
static const struct dm_regulator_ops rk8xx_ldo_ops = {
.get_value = ldo_get_value,
.set_value = ldo_set_value,
.get_enable = ldo_get_enable,
.set_enable = ldo_set_enable,
};
static const struct dm_regulator_ops rk808_switch_ops = {
static const struct dm_regulator_ops rk8xx_switch_ops = {
.get_enable = switch_get_enable,
.set_enable = switch_set_enable,
};
U_BOOT_DRIVER(rk808_buck) = {
.name = "rk808_buck",
U_BOOT_DRIVER(rk8xx_buck) = {
.name = "rk8xx_buck",
.id = UCLASS_REGULATOR,
.ops = &rk808_buck_ops,
.probe = rk808_buck_probe,
.ops = &rk8xx_buck_ops,
.probe = rk8xx_buck_probe,
};
U_BOOT_DRIVER(rk808_ldo) = {
.name = "rk808_ldo",
U_BOOT_DRIVER(rk8xx_ldo) = {
.name = "rk8xx_ldo",
.id = UCLASS_REGULATOR,
.ops = &rk808_ldo_ops,
.probe = rk808_ldo_probe,
.ops = &rk8xx_ldo_ops,
.probe = rk8xx_ldo_probe,
};
U_BOOT_DRIVER(rk808_switch) = {
.name = "rk808_switch",
U_BOOT_DRIVER(rk8xx_switch) = {
.name = "rk8xx_switch",
.id = UCLASS_REGULATOR,
.ops = &rk808_switch_ops,
.probe = rk808_switch_probe,
.ops = &rk8xx_switch_ops,
.probe = rk8xx_switch_probe,
};
#endif
int rk808_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt)
{
int ret;

10
drivers/pwm/pwm-uclass.c
View File

@@ -9,6 +9,16 @@
#include <dm.h>
#include <pwm.h>
int pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
{
struct pwm_ops *ops = pwm_get_ops(dev);
if (!ops->set_invert)
return -ENOSYS;
return ops->set_invert(dev, channel, polarity);
}
int pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
uint duty_ns)
{

17
drivers/pwm/rk_pwm.c
View File

@@ -21,8 +21,22 @@ DECLARE_GLOBAL_DATA_PTR;
struct rk_pwm_priv {
struct rk3288_pwm *regs;
ulong freq;
uint enable_conf;
};
static int rk_pwm_set_invert(struct udevice *dev, uint channel, bool polarity)
{
struct rk_pwm_priv *priv = dev_get_priv(dev);
debug("%s: polarity=%u\n", __func__, polarity);
if (polarity)
priv->enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSTIVE;
else
priv->enable_conf |= PWM_DUTY_POSTIVE | PWM_INACTIVE_NEGATIVE;
return 0;
}
static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
uint duty_ns)
{
@@ -32,7 +46,7 @@ static int rk_pwm_set_config(struct udevice *dev, uint channel, uint period_ns,
debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
writel(PWM_SEL_SRC_CLK | PWM_OUTPUT_LEFT | PWM_LP_DISABLE |
PWM_CONTINUOUS | PWM_DUTY_POSTIVE | PWM_INACTIVE_POSTIVE |
PWM_CONTINUOUS | priv->enable_conf |
RK_PWM_DISABLE,
&regs->ctrl);
@@ -83,6 +97,7 @@ static int rk_pwm_probe(struct udevice *dev)
}
static const struct pwm_ops rk_pwm_ops = {
.set_invert = rk_pwm_set_invert,
.set_config = rk_pwm_set_config,
.set_enable = rk_pwm_set_enable,
};

16
drivers/pwm/sandbox_pwm.c
View File

@@ -21,6 +21,7 @@ struct sandbox_pwm_chan {
uint period_ns;
uint duty_ns;
bool enable;
bool polarity;
};
struct sandbox_pwm_priv {
@@ -56,9 +57,24 @@ static int sandbox_pwm_set_enable(struct udevice *dev, uint channel,
return 0;
}
static int sandbox_pwm_set_invert(struct udevice *dev, uint channel,
bool polarity)
{
struct sandbox_pwm_priv *priv = dev_get_priv(dev);
struct sandbox_pwm_chan *chan;
if (channel >= NUM_CHANNELS)
return -ENOSPC;
chan = &priv->chan[channel];
chan->polarity = polarity;
return 0;
}
static const struct pwm_ops sandbox_pwm_ops = {
.set_config = sandbox_pwm_set_config,
.set_enable = sandbox_pwm_set_enable,
.set_invert = sandbox_pwm_set_invert,
};
static const struct udevice_id sandbox_pwm_ids[] = {

62
drivers/spi/rk_spi.c
View File

@@ -79,12 +79,31 @@ static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
static void rkspi_set_clk(struct rockchip_spi_priv *priv, uint speed)
{
uint clk_div;
/*
* We should try not to exceed the speed requested by the caller:
* when selecting a divider, we need to make sure we round up.
*/
uint clk_div = DIV_ROUND_UP(priv->input_rate, speed);
/* The baudrate register (BAUDR) is defined as a 32bit register where
* the upper 16bit are reserved and having 'Fsclk_out' in the lower
* 16bits with 'Fsclk_out' defined as follows:
*
* Fsclk_out = Fspi_clk/ SCKDV
* Where SCKDV is any even value between 2 and 65534.
*/
if (clk_div > 0xfffe) {
clk_div = 0xfffe;
debug("%s: can't divide down to %d hz (actual will be %d hz)\n",
__func__, speed, priv->input_rate / clk_div);
}
/* Round up to the next even 16bit number */
clk_div = (clk_div + 1) & 0xfffe;
clk_div = clk_get_divisor(priv->input_rate, speed);
debug("spi speed %u, div %u\n", speed, clk_div);
writel(clk_div, &priv->regs->baudr);
clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div);
priv->last_speed_hz = speed;
}
@@ -190,6 +209,26 @@ static int rockchip_spi_ofdata_to_platdata(struct udevice *bus)
return 0;
}
static int rockchip_spi_calc_modclk(ulong max_freq)
{
unsigned div;
const unsigned long gpll_hz = 594000000UL;
/*
* We need to find an input clock that provides at least twice
* the maximum frequency and can be generated from the assumed
* speed of GPLL (594MHz) using an integer divider.
*
* To give us more achievable bitrates at higher speeds (these
* are generated by dividing by an even 16-bit integer from
* this frequency), we try to have an input frequency of at
* least 4x our max_freq.
*/
div = DIV_ROUND_UP(gpll_hz, max_freq * 4);
return gpll_hz / div;
}
static int rockchip_spi_probe(struct udevice *bus)
{
struct rockchip_spi_platdata *plat = dev_get_platdata(bus);
@@ -207,11 +246,13 @@ static int rockchip_spi_probe(struct udevice *bus)
priv->last_transaction_us = timer_get_us();
priv->max_freq = plat->frequency;
/*
* Use 99 MHz as our clock since it divides nicely into 594 MHz which
* is the assumed speed for CLK_GENERAL.
*/
ret = clk_set_rate(&priv->clk, 99000000);
/* Clamp the value from the DTS against any hardware limits */
if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE)
priv->max_freq = ROCKCHIP_SPI_MAX_RATE;
/* Find a module-input clock that fits with the max_freq setting */
ret = clk_set_rate(&priv->clk,
rockchip_spi_calc_modclk(priv->max_freq));
if (ret < 0) {
debug("%s: Failed to set clock: %d\n", __func__, ret);
return ret;
@@ -371,10 +412,10 @@ static int rockchip_spi_set_speed(struct udevice *bus, uint speed)
{
struct rockchip_spi_priv *priv = dev_get_priv(bus);
if (speed > ROCKCHIP_SPI_MAX_RATE)
return -EINVAL;
/* Clamp to the maximum frequency specified in the DTS */
if (speed > priv->max_freq)
speed = priv->max_freq;
priv->speed_hz = speed;
return 0;
@@ -403,6 +444,7 @@ static const struct dm_spi_ops rockchip_spi_ops = {
static const struct udevice_id rockchip_spi_ids[] = {
{ .compatible = "rockchip,rk3288-spi" },
{ .compatible = "rockchip,rk3399-spi" },
{ }
};

9
drivers/spi/rk_spi.h
View File

@@ -119,6 +119,13 @@ enum {
};
#define ROCKCHIP_SPI_TIMEOUT_MS 1000
#define ROCKCHIP_SPI_MAX_RATE 48000000
/*
* We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
* hardware limitation... the Linux kernel source has the following
* comment:
* "sclk_out: spi master internal logic in rk3x can support 50Mhz"
*/
#define ROCKCHIP_SPI_MAX_RATE 50000000
#endif /* __RK_SPI_H */

10
drivers/video/Kconfig
View File

@@ -425,15 +425,7 @@ config VIDEO_FSL_DCU_MAX_FB_SIZE_MB
Set maximum framebuffer size to be used for Freescale Display
Controller Unit (DCU4).
config VIDEO_ROCKCHIP
bool "Enable Rockchip video support"
depends on DM_VIDEO
help
Rockchip SoCs provide video output capabilities for High-Definition
Multimedia Interface (HDMI), Low-voltage Differential Signalling
(LVDS), embedded DisplayPort (eDP) and Display Serial Interface
(DSI). This driver supports the on-chip video output device, and
targets the Rockchip RK3288.
source "drivers/video/rockchip/Kconfig"
config VIDEO_SANDBOX_SDL
bool "Enable sandbox video console using SDL"

50
drivers/video/rockchip/Kconfig Normal file
View File

@@ -0,0 +1,50 @@
#
# Video drivers selection for rockchip soc. These configs only impact the
# compile process. You can surely check all the options. In this case, all the
# display driver will be compiled, but which drivers finally will be used is
# decided by device tree configuration. What's more, enable needed power for
# display by configure the device tree, and the vop driver will do the rest.
#
# Author: Eric Gao <eric.gao@rock-chips.com>
#
menuconfig VIDEO_ROCKCHIP
bool "Enable Rockchip Video Support"
depends on DM_VIDEO
help
Rockchip SoCs provide video output capabilities for High-Definition
Multimedia Interface (HDMI), Low-voltage Differential Signalling
(LVDS), embedded DisplayPort (eDP) and Display Serial Interface
(DSI). This driver supports the on-chip video output device, and
targets the Rockchip RK3288 and RK3399.
if VIDEO_ROCKCHIP
config DISPLAY_ROCKCHIP_EDP
bool "EDP Port"
depends on VIDEO_ROCKCHIP
help
This enables Embedded DisplayPort(EDP) display support.
config DISPLAY_ROCKCHIP_LVDS
bool "LVDS Port"
depends on VIDEO_ROCKCHIP
help
This enables Low-voltage Differential Signaling(LVDS) display
support.
config DISPLAY_ROCKCHIP_HDMI
bool "HDMI port"
depends on VIDEO_ROCKCHIP
help
This enables High-Definition Multimedia Interface display support.
config DISPLAY_ROCKCHIP_MIPI
bool "MIPI Port"
depends on VIDEO_ROCKCHIP
help
This enables Mobile Industry Processor Interface(MIPI) display
support. The mipi controller and dphy on rk3288& rk3399 support
16,18, 24 bits per pixel with upto 2k resolution ratio.
endif

8
drivers/video/rockchip/Makefile
View File

@@ -5,4 +5,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += rk_edp.o rk_hdmi.o rk_vop.o rk_lvds.o ../dw_hdmi.o
ifdef CONFIG_VIDEO_ROCKCHIP
obj-y += rk_vop.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_EDP) += rk_edp.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_LVDS) += rk_lvds.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_HDMI) += rk_hdmi.o ../dw_hdmi.o
obj-$(CONFIG_DISPLAY_ROCKCHIP_MIPI) += rk_mipi.o
endif

491
drivers/video/rockchip/rk_mipi.c Normal file
View File

@@ -0,0 +1,491 @@
/*
* Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
* Author: Eric Gao <eric.gao@rock-chips.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk.h>
#include <display.h>
#include <dm.h>
#include <fdtdec.h>
#include <panel.h>
#include <regmap.h>
#include <syscon.h>
#include <asm/gpio.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <dm/uclass-internal.h>
#include <linux/kernel.h>
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3399.h>
#include <asm/arch/grf_rk3399.h>
#include <asm/arch/rockchip_mipi_dsi.h>
#include <dt-bindings/clock/rk3288-cru.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Private information for rk mipi
*
* @regs: mipi controller address
* @grf: GRF register
* @panel: panel assined by device tree
* @ref_clk: reference clock for mipi dsi pll
* @sysclk: config clock for mipi dsi register
* @pix_clk: pixel clock for vop->dsi data transmission
* @phy_clk: mipi dphy output clock
* @txbyte_clk: clock for dsi->dphy high speed data transmission
* @txesc_clk: clock for tx esc mode
*/
struct rk_mipi_priv {
void __iomem *regs;
struct rk3399_grf_regs *grf;
struct udevice *panel;
struct mipi_dsi *dsi;
u32 ref_clk;
u32 sys_clk;
u32 pix_clk;
u32 phy_clk;
u32 txbyte_clk;
u32 txesc_clk;
};
static int rk_mipi_read_timing(struct udevice *dev,
struct display_timing *timing)
{
int ret;
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
0, timing);
if (ret) {
debug("%s: Failed to decode display timing (ret=%d)\n",
__func__, ret);
return -EINVAL;
}
return 0;
}
/*
* Register write function used only for mipi dsi controller.
* Parameter:
* @regs: mipi controller address
* @reg: combination of regaddr(16bit)|bitswidth(8bit)|offset(8bit) you can
* use define in rk_mipi.h directly for this parameter
* @val: value that will be write to specified bits of register
*/
static void rk_mipi_dsi_write(u32 regs, u32 reg, u32 val)
{
u32 dat;
u32 mask;
u32 offset = (reg >> OFFSET_SHIFT) & 0xff;
u32 bits = (reg >> BITS_SHIFT) & 0xff;
u64 addr = (reg >> ADDR_SHIFT) + regs;
/* Mask for specifiled bits,the corresponding bits will be clear */
mask = ~((0xffffffff << offset) & (0xffffffff >> (32 - offset - bits)));
/* Make sure val in the available range */
val &= ~(0xffffffff << bits);
/* Get register's original val */
dat = readl(addr);
/* Clear specified bits */
dat &= mask;
/* Fill specified bits */
dat |= val << offset;
writel(dat, addr);
}
static int rk_mipi_dsi_enable(struct udevice *dev,
const struct display_timing *timing)
{
int node, timing_node;
int val;
struct rk_mipi_priv *priv = dev_get_priv(dev);
u64 regs = (u64)priv->regs;
struct display_plat *disp_uc_plat = dev_get_uclass_platdata(dev);
u32 txbyte_clk = priv->txbyte_clk;
u32 txesc_clk = priv->txesc_clk;
txesc_clk = txbyte_clk/(txbyte_clk/txesc_clk + 1);
/* Select the video source */
switch (disp_uc_plat->source_id) {
case VOP_B:
rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
GRF_DSI0_VOP_SEL_B << GRF_DSI0_VOP_SEL_SHIFT);
break;
case VOP_L:
rk_clrsetreg(&priv->grf->soc_con20, GRF_DSI0_VOP_SEL_MASK,
GRF_DSI0_VOP_SEL_L << GRF_DSI0_VOP_SEL_SHIFT);
break;
default:
debug("%s: Invalid VOP id\n", __func__);
return -EINVAL;
}
/* Set Controller as TX mode */
val = GRF_DPHY_TX0_RXMODE_DIS << GRF_DPHY_TX0_RXMODE_SHIFT;
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_RXMODE_MASK, val);
/* Exit tx stop mode */
val |= GRF_DPHY_TX0_TXSTOPMODE_DIS << GRF_DPHY_TX0_TXSTOPMODE_SHIFT;
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TXSTOPMODE_MASK, val);
/* Disable turnequest */
val |= GRF_DPHY_TX0_TURNREQUEST_DIS << GRF_DPHY_TX0_TURNREQUEST_SHIFT;
rk_clrsetreg(&priv->grf->soc_con22, GRF_DPHY_TX0_TURNREQUEST_MASK, val);
/* Set Display timing parameter */
rk_mipi_dsi_write(regs, VID_HSA_TIME, timing->hsync_len.typ);
rk_mipi_dsi_write(regs, VID_HBP_TIME, timing->hback_porch.typ);
rk_mipi_dsi_write(regs, VID_HLINE_TIME, (timing->hsync_len.typ
+ timing->hback_porch.typ + timing->hactive.typ
+ timing->hfront_porch.typ));
rk_mipi_dsi_write(regs, VID_VSA_LINES, timing->vsync_len.typ);
rk_mipi_dsi_write(regs, VID_VBP_LINES, timing->vback_porch.typ);
rk_mipi_dsi_write(regs, VID_VFP_LINES, timing->vfront_porch.typ);
rk_mipi_dsi_write(regs, VID_ACTIVE_LINES, timing->vactive.typ);
/* Set Signal Polarity */
val = (timing->flags & DISPLAY_FLAGS_HSYNC_LOW) ? 1 : 0;
rk_mipi_dsi_write(regs, HSYNC_ACTIVE_LOW, val);
val = (timing->flags & DISPLAY_FLAGS_VSYNC_LOW) ? 1 : 0;
rk_mipi_dsi_write(regs, VSYNC_ACTIVE_LOW, val);
val = (timing->flags & DISPLAY_FLAGS_DE_LOW) ? 1 : 0;
rk_mipi_dsi_write(regs, DISPLAY_FLAGS_DE_LOW, val);
val = (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) ? 1 : 0;
rk_mipi_dsi_write(regs, COLORM_ACTIVE_LOW, val);
/* Set video mode */
rk_mipi_dsi_write(regs, CMD_VIDEO_MODE, VIDEO_MODE);
/* Set video mode transmission type as burst mode */
rk_mipi_dsi_write(regs, VID_MODE_TYPE, BURST_MODE);
/* Set pix num in a video package */
rk_mipi_dsi_write(regs, VID_PKT_SIZE, 0x4b0);
/* Set dpi color coding depth 24 bit */
timing_node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(dev),
"display-timings");
node = fdt_first_subnode(gd->fdt_blob, timing_node);
val = fdtdec_get_int(gd->fdt_blob, node, "bits-per-pixel", -1);
switch (val) {
case 16:
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_16BIT_CFG_1);
break;
case 24:
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
break;
case 30:
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_30BIT);
break;
default:
rk_mipi_dsi_write(regs, DPI_COLOR_CODING, DPI_24BIT);
}
/* Enable low power mode */
rk_mipi_dsi_write(regs, LP_CMD_EN, 1);
rk_mipi_dsi_write(regs, LP_HFP_EN, 1);
rk_mipi_dsi_write(regs, LP_VACT_EN, 1);
rk_mipi_dsi_write(regs, LP_VFP_EN, 1);
rk_mipi_dsi_write(regs, LP_VBP_EN, 1);
rk_mipi_dsi_write(regs, LP_VSA_EN, 1);
/* Division for timeout counter clk */
rk_mipi_dsi_write(regs, TO_CLK_DIVISION, 0x0a);
/* Tx esc clk division from txbyte clk */
rk_mipi_dsi_write(regs, TX_ESC_CLK_DIVISION, txbyte_clk/txesc_clk);
/* Timeout count for hs<->lp transation between Line period */
rk_mipi_dsi_write(regs, HSTX_TO_CNT, 0x3e8);
/* Phy State transfer timing */
rk_mipi_dsi_write(regs, PHY_STOP_WAIT_TIME, 32);
rk_mipi_dsi_write(regs, PHY_TXREQUESTCLKHS, 1);
rk_mipi_dsi_write(regs, PHY_HS2LP_TIME, 0x14);
rk_mipi_dsi_write(regs, PHY_LP2HS_TIME, 0x10);
rk_mipi_dsi_write(regs, MAX_RD_TIME, 0x2710);
/* Power on */
rk_mipi_dsi_write(regs, SHUTDOWNZ, 1);
return 0;
}
/* rk mipi dphy write function. It is used to write test data to dphy */
static void rk_mipi_phy_write(u32 regs, unsigned char test_code,
unsigned char *test_data, unsigned char size)
{
int i = 0;
/* Write Test code */
rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
rk_mipi_dsi_write(regs, PHY_TESTDIN, test_code);
rk_mipi_dsi_write(regs, PHY_TESTEN, 1);
rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
rk_mipi_dsi_write(regs, PHY_TESTEN, 0);
/* Write Test data */
for (i = 0; i < size; i++) {
rk_mipi_dsi_write(regs, PHY_TESTCLK, 0);
rk_mipi_dsi_write(regs, PHY_TESTDIN, test_data[i]);
rk_mipi_dsi_write(regs, PHY_TESTCLK, 1);
}
}
/*
* Mipi dphy config function. Calculate the suitable prediv, feedback div,
* fsfreqrang value ,cap ,lpf and so on according to the given pix clk rate,
* and then enable phy.
*/
static int rk_mipi_phy_enable(struct udevice *dev)
{
int i;
struct rk_mipi_priv *priv = dev_get_priv(dev);
u64 regs = (u64)priv->regs;
u64 fbdiv;
u64 prediv = 1;
u32 max_fbdiv = 512;
u32 max_prediv, min_prediv;
u64 ddr_clk = priv->phy_clk;
u32 refclk = priv->ref_clk;
u32 remain = refclk;
unsigned char test_data[2] = {0};
int freq_rang[][2] = {
{90, 0x01}, {100, 0x10}, {110, 0x20}, {130, 0x01},
{140, 0x11}, {150, 0x21}, {170, 0x02}, {180, 0x12},
{200, 0x22}, {220, 0x03}, {240, 0x13}, {250, 0x23},
{270, 0x04}, {300, 0x14}, {330, 0x05}, {360, 0x15},
{400, 0x25}, {450, 0x06}, {500, 0x16}, {550, 0x07},
{600, 0x17}, {650, 0x08}, {700, 0x18}, {750, 0x09},
{800, 0x19}, {850, 0x29}, {900, 0x39}, {950, 0x0a},
{1000, 0x1a}, {1050, 0x2a}, {1100, 0x3a}, {1150, 0x0b},
{1200, 0x1b}, {1250, 0x2b}, {1300, 0x3b}, {1350, 0x0c},
{1400, 0x1c}, {1450, 0x2c}, {1500, 0x3c}
};
/* Shutdown mode */
rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 0);
rk_mipi_dsi_write(regs, PHY_RSTZ, 0);
rk_mipi_dsi_write(regs, PHY_TESTCLR, 1);
/* Pll locking */
rk_mipi_dsi_write(regs, PHY_TESTCLR, 0);
/* config cp and lfp */
test_data[0] = 0x80 | (ddr_clk / (200 * MHz)) << 3 | 0x3;
rk_mipi_phy_write(regs, CODE_PLL_VCORANGE_VCOCAP, test_data, 1);
test_data[0] = 0x8;
rk_mipi_phy_write(regs, CODE_PLL_CPCTRL, test_data, 1);
test_data[0] = 0x80 | 0x40;
rk_mipi_phy_write(regs, CODE_PLL_LPF_CP, test_data, 1);
/* select the suitable value for fsfreqrang reg */
for (i = 0; i < ARRAY_SIZE(freq_rang); i++) {
if (ddr_clk / (MHz) >= freq_rang[i][0])
break;
}
if (i == ARRAY_SIZE(freq_rang)) {
debug("%s: Dphy freq out of range!\n", __func__);
return -EINVAL;
}
test_data[0] = freq_rang[i][1] << 1;
rk_mipi_phy_write(regs, CODE_HS_RX_LANE0, test_data, 1);
/*
* Calculate the best ddrclk and it's corresponding div value. If the
* given pixelclock is great than 250M, ddrclk will be fix 1500M.
* Otherwise,
* it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
* according to spec.
*/
max_prediv = (refclk / (5 * MHz));
min_prediv = ((refclk / (40 * MHz)) ? (refclk / (40 * MHz) + 1) : 1);
debug("%s: DEBUG: max_prediv=%u, min_prediv=%u\n", __func__, max_prediv,
min_prediv);
if (max_prediv < min_prediv) {
debug("%s: Invalid refclk value\n", __func__);
return -EINVAL;
}
/* Calculate the best refclk and feedback division value for dphy pll */
for (i = min_prediv; i < max_prediv; i++) {
if ((ddr_clk * i % refclk < remain) &&
(ddr_clk * i / refclk) < max_fbdiv) {
prediv = i;
remain = ddr_clk * i % refclk;
}
}
fbdiv = ddr_clk * prediv / refclk;
ddr_clk = refclk * fbdiv / prediv;
priv->phy_clk = ddr_clk;
debug("%s: DEBUG: refclk=%u, refclk=%llu, fbdiv=%llu, phyclk=%llu\n",
__func__, refclk, prediv, fbdiv, ddr_clk);
/* config prediv and feedback reg */
test_data[0] = prediv - 1;
rk_mipi_phy_write(regs, CODE_PLL_INPUT_DIV_RAT, test_data, 1);
test_data[0] = (fbdiv - 1) & 0x1f;
rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
test_data[0] = (fbdiv - 1) >> 5 | 0x80;
rk_mipi_phy_write(regs, CODE_PLL_LOOP_DIV_RAT, test_data, 1);
test_data[0] = 0x30;
rk_mipi_phy_write(regs, CODE_PLL_INPUT_LOOP_DIV_RAT, test_data, 1);
/* rest config */
test_data[0] = 0x4d;
rk_mipi_phy_write(regs, CODE_BANDGAP_BIAS_CTRL, test_data, 1);
test_data[0] = 0x3d;
rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
test_data[0] = 0xdf;
rk_mipi_phy_write(regs, CODE_TERMINATION_CTRL, test_data, 1);
test_data[0] = 0x7;
rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
test_data[0] = 0x80 | 0x7;
rk_mipi_phy_write(regs, CODE_AFE_BIAS_BANDGAP_ANOLOG, test_data, 1);
test_data[0] = 0x80 | 15;
rk_mipi_phy_write(regs, CODE_HSTXDATALANEREQUSETSTATETIME,
test_data, 1);
test_data[0] = 0x80 | 85;
rk_mipi_phy_write(regs, CODE_HSTXDATALANEPREPARESTATETIME,
test_data, 1);
test_data[0] = 0x40 | 10;
rk_mipi_phy_write(regs, CODE_HSTXDATALANEHSZEROSTATETIME,
test_data, 1);
/* enter into stop mode */
rk_mipi_dsi_write(regs, N_LANES, 0x03);
rk_mipi_dsi_write(regs, PHY_ENABLECLK, 1);
rk_mipi_dsi_write(regs, PHY_FORCEPLL, 1);
rk_mipi_dsi_write(regs, PHY_SHUTDOWNZ, 1);
rk_mipi_dsi_write(regs, PHY_RSTZ, 1);
return 0;
}
/*
* This function is called by rk_display_init() using rk_mipi_dsi_enable() and
* rk_mipi_phy_enable() to initialize mipi controller and dphy. If success,
* enable backlight.
*/
static int rk_display_enable(struct udevice *dev, int panel_bpp,
const struct display_timing *timing)
{
int ret;
struct rk_mipi_priv *priv = dev_get_priv(dev);
/* Fill the mipi controller parameter */
priv->ref_clk = 24 * MHz;
priv->sys_clk = priv->ref_clk;
priv->pix_clk = timing->pixelclock.typ;
priv->phy_clk = priv->pix_clk * 6;
priv->txbyte_clk = priv->phy_clk / 8;
priv->txesc_clk = 20 * MHz;
/* Config and enable mipi dsi according to timing */
ret = rk_mipi_dsi_enable(dev, timing);
if (ret) {
debug("%s: rk_mipi_dsi_enable() failed (err=%d)\n",
__func__, ret);
return ret;
}
/* Config and enable mipi phy */
ret = rk_mipi_phy_enable(dev);
if (ret) {
debug("%s: rk_mipi_phy_enable() failed (err=%d)\n",
__func__, ret);
return ret;
}
/* Enable backlight */
ret = panel_enable_backlight(priv->panel);
if (ret) {
debug("%s: panel_enable_backlight() failed (err=%d)\n",
__func__, ret);
return ret;
}
return 0;
}
static int rk_mipi_ofdata_to_platdata(struct udevice *dev)
{
struct rk_mipi_priv *priv = dev_get_priv(dev);
priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (priv->grf <= 0) {
debug("%s: Get syscon grf failed (ret=%llu)\n",
__func__, (u64)priv->grf);
return -ENXIO;
}
priv->regs = (void *)dev_get_addr(dev);
if (priv->regs <= 0) {
debug("%s: Get MIPI dsi address failed (ret=%llu)\n", __func__,
(u64)priv->regs);
return -ENXIO;
}
return 0;
}
/*
* Probe function: check panel existence and readingit's timing. Then config
* mipi dsi controller and enable it according to the timing parameter.
*/
static int rk_mipi_probe(struct udevice *dev)
{
int ret;
struct rk_mipi_priv *priv = dev_get_priv(dev);
ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
&priv->panel);
if (ret) {
debug("%s: Can not find panel (err=%d)\n", __func__, ret);
return ret;
}
return 0;
}
static const struct dm_display_ops rk_mipi_dsi_ops = {
.read_timing = rk_mipi_read_timing,
.enable = rk_display_enable,
};
static const struct udevice_id rk_mipi_dsi_ids[] = {
{ .compatible = "rockchip,rk3399_mipi_dsi" },
{ }
};
U_BOOT_DRIVER(rk_mipi_dsi) = {
.name = "rk_mipi_dsi",
.id = UCLASS_DISPLAY,
.of_match = rk_mipi_dsi_ids,
.ofdata_to_platdata = rk_mipi_ofdata_to_platdata,
.probe = rk_mipi_probe,
.ops = &rk_mipi_dsi_ops,
.priv_auto_alloc_size = sizeof(struct rk_mipi_priv),
};

30
drivers/video/rockchip/rk_vop.c
View File

@@ -117,6 +117,10 @@ void rkvop_mode_set(struct rk3288_vop *regs,
clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
V_RGB_OUT_EN(1));
break;
case VOP_MODE_MIPI:
clrsetbits_le32(&regs->sys_ctrl, M_ALL_OUT_EN,
V_MIPI_OUT_EN(1));
break;
}
if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP)
@@ -177,13 +181,11 @@ void rkvop_mode_set(struct rk3288_vop *regs,
*
* @dev: VOP device that we want to connect to the display
* @fbbase: Frame buffer address
* @l2bpp Log2 of bits-per-pixels for the display
* @ep_node: Device tree node to process - this is the offset of an endpoint
* node within the VOP's 'port' list.
* @return 0 if OK, -ve if something went wrong
*/
int rk_display_init(struct udevice *dev, ulong fbbase,
enum video_log2_bpp l2bpp, int ep_node)
int rk_display_init(struct udevice *dev, ulong fbbase, int ep_node)
{
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
const void *blob = gd->fdt_blob;
@@ -195,6 +197,7 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
int ret, remote, i, offset;
struct display_plat *disp_uc_plat;
struct clk clk;
enum video_log2_bpp l2bpp;
vop_id = fdtdec_get_int(blob, ep_node, "reg", -1);
debug("vop_id=%d\n", vop_id);
@@ -244,11 +247,24 @@ int rk_display_init(struct udevice *dev, ulong fbbase,
ret = clk_get_by_index(dev, 1, &clk);
if (!ret)
ret = clk_set_rate(&clk, timing.pixelclock.typ);
if (ret) {
if (IS_ERR_VALUE(ret)) {
debug("%s: Failed to set pixel clock: ret=%d\n", __func__, ret);
return ret;
}
/* Set bitwidth for vop display according to vop mode */
switch (vop_id) {
case VOP_MODE_EDP:
case VOP_MODE_HDMI:
case VOP_MODE_LVDS:
l2bpp = VIDEO_BPP16;
break;
case VOP_MODE_MIPI:
l2bpp = VIDEO_BPP32;
break;
default:
l2bpp = VIDEO_BPP16;
}
rkvop_mode_set(regs, &timing, vop_id);
rkvop_enable(regs, fbbase, 1 << l2bpp, &timing);
@@ -326,7 +342,7 @@ static int rk_vop_probe(struct udevice *dev)
for (node = fdt_first_subnode(blob, port);
node > 0;
node = fdt_next_subnode(blob, node)) {
ret = rk_display_init(dev, plat->base, VIDEO_BPP16, node);
ret = rk_display_init(dev, plat->base, node);
if (ret)
debug("Device failed: ret=%d\n", ret);
if (!ret)
@@ -341,7 +357,7 @@ static int rk_vop_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
plat->size = 1920 * 1080 * 2;
plat->size = 1920 * 1200 * 4;
return 0;
}
@@ -350,6 +366,8 @@ static const struct video_ops rk_vop_ops = {
};
static const struct udevice_id rk_vop_ids[] = {
{ .compatible = "rockchip,rk3399-vop-big" },
{ .compatible = "rockchip,rk3399-vop-lit" },
{ .compatible = "rockchip,rk3288-vop" },
{ }
};