Merge branch 'at91' of git://git.denx.de/u-boot-atmel
This commit is contained in:
Wolfgang Denk
commit
1ed3b710d0
@ -573,6 +573,10 @@ Rishi Bhattacharya <rishi@ti.com>
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omap5912osk ARM926EJS
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Andreas Bießmann <andreas.devel@gmail.com>
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at91rm9200ek at91rm9200
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Cliff Brake <cliff.brake@gmail.com>
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pxa255_idp xscale
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@ -11,47 +11,46 @@
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* (at your option) any later version.
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/io.h>
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#include <asm/arch/at91_pmc.h>
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#include <asm/arch/clk.h>
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static unsigned long cpu_clk_rate_hz;
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static unsigned long main_clk_rate_hz;
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static unsigned long mck_rate_hz;
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static unsigned long plla_rate_hz;
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static unsigned long pllb_rate_hz;
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static u32 at91_pllb_usb_init;
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#if !defined(CONFIG_AT91FAMILY)
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# error You need to define CONFIG_AT91FAMILY in your board config!
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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unsigned long get_cpu_clk_rate(void)
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{
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return cpu_clk_rate_hz;
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return gd->cpu_clk_rate_hz;
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}
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unsigned long get_main_clk_rate(void)
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{
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return main_clk_rate_hz;
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return gd->main_clk_rate_hz;
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}
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unsigned long get_mck_clk_rate(void)
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{
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return mck_rate_hz;
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return gd->mck_rate_hz;
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}
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unsigned long get_plla_clk_rate(void)
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{
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return plla_rate_hz;
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return gd->plla_rate_hz;
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}
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unsigned long get_pllb_clk_rate(void)
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{
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return pllb_rate_hz;
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return gd->pllb_rate_hz;
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}
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u32 get_pllb_init(void)
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{
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return at91_pllb_usb_init;
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return gd->at91_pllb_usb_init;
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}
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static unsigned long at91_css_to_rate(unsigned long css)
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@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
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case AT91_PMC_MCKR_CSS_SLOW:
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return AT91_SLOW_CLOCK;
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case AT91_PMC_MCKR_CSS_MAIN:
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return main_clk_rate_hz;
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return gd->main_clk_rate_hz;
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case AT91_PMC_MCKR_CSS_PLLA:
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return plla_rate_hz;
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return gd->plla_rate_hz;
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case AT91_PMC_MCKR_CSS_PLLB:
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return pllb_rate_hz;
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return gd->pllb_rate_hz;
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}
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return 0;
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@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
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main_clock = tmp * (AT91_SLOW_CLOCK / 16);
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}
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#endif
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main_clk_rate_hz = main_clock;
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gd->main_clk_rate_hz = main_clock;
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/* report if PLLA is more than mildly overclocked */
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plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
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gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
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#ifdef CONFIG_USB_ATMEL
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/*
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@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
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*
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* REVISIT: assumes MCK doesn't derive from PLLB!
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*/
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at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
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gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
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AT91_PMC_PLLBR_USBDIV_2;
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pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
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gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
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#endif
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/*
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@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
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mckr = readl(&pmc->mckr);
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#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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/* plla divisor by 2 */
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plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
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gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
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#endif
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mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
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freq = mck_rate_hz;
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gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
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freq = gd->mck_rate_hz;
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freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
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#if defined(CONFIG_AT91RM9200)
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/* mdiv */
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mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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#elif defined(CONFIG_AT91SAM9G20)
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/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
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mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
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gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
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freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
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if (mckr & AT91_PMC_MCKR_MDIV_MASK)
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freq /= 2; /* processor clock division */
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#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
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mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
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gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
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(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
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? freq / 3
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: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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#else
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mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
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#endif
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cpu_clk_rate_hz = freq;
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gd->cpu_clk_rate_hz = freq;
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return 0;
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}
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@ -30,55 +30,63 @@
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#include <asm/arch/io.h>
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#include <div64.h>
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#if !defined(CONFIG_AT91FAMILY)
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# error You need to define CONFIG_AT91FAMILY in your board config!
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
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* setting the 20 bit counter period to its maximum (0xfffff).
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* (See the relevant data sheets to understand that this really works)
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*
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* We do also mimic the typical powerpc way of incrementing
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* two 32 bit registers called tbl and tbu.
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*
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* Those registers increment at 1/16 the main clock rate.
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*/
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#define TIMER_LOAD_VAL 0xfffff
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static ulong timestamp;
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static ulong lastinc;
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static ulong timer_freq;
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#define TIMER_LOAD_VAL 0xfffff
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static inline unsigned long long tick_to_time(unsigned long long tick)
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{
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tick *= CONFIG_SYS_HZ;
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do_div(tick, timer_freq);
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do_div(tick, gd->timer_rate_hz);
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return tick;
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}
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static inline unsigned long long usec_to_tick(unsigned long long usec)
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{
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usec *= timer_freq;
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usec *= gd->timer_rate_hz;
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do_div(usec, 1000000);
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return usec;
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}
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/* nothing really to do with interrupts, just starts up a counter. */
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/*
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* Use the PITC in full 32 bit incrementing mode
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*/
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int timer_init(void)
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{
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at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
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at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
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/*
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* Enable PITC Clock
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* The clock is already enabled for system controller in boot
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*/
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/* Enable PITC Clock */
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writel(1 << AT91_ID_SYS, &pmc->pcer);
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/* Enable PITC */
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writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
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reset_timer_masked();
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timer_freq = get_mck_clk_rate() >> 4;
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gd->timer_rate_hz = gd->mck_rate_hz / 16;
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gd->tbu = gd->tbl = 0;
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return 0;
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}
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/*
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* timer without interrupts
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* Get the current 64 bit timer tick count
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*/
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unsigned long long get_ticks(void)
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{
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@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
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ulong now = readl(&pit->piir);
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if (now >= lastinc) /* normal mode (non roll) */
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/* move stamp forward with absolut diff ticks */
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timestamp += (now - lastinc);
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else /* we have rollover of incrementer */
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timestamp += (0xFFFFFFFF - lastinc) + now;
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lastinc = now;
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return timestamp;
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}
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void reset_timer_masked(void)
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{
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/* reset time */
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at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
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/* capture current incrementer value time */
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lastinc = readl(&pit->piir);
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timestamp = 0; /* start "advancing" time stamp from 0 */
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}
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ulong get_timer_masked(void)
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{
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return tick_to_time(get_ticks());
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/* increment tbu if tbl has rolled over */
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if (now < gd->tbl)
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gd->tbu++;
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gd->tbl = now;
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return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
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}
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void __udelay(unsigned long usec)
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@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
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tmp = get_ticks() + tmo; /* get current timestamp */
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while (get_ticks() < tmp) /* loop till event */
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/*NOP*/;
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;
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}
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/*
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* reset_timer() and get_timer(base) are a pair of functions that are used by
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* some timeout/sleep mechanisms in u-boot.
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*
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* reset_timer() marks the current time as epoch and
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* get_timer(base) works relative to that epoch.
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*
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* The time is used in CONFIG_SYS_HZ units!
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*/
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void reset_timer(void)
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{
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reset_timer_masked();
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gd->timer_reset_value = get_ticks();
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}
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ulong get_timer(ulong base)
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{
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return get_timer_masked () - base;
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return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
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}
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/*
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* This function is derived from PowerPC code (timebase clock frequency).
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* On ARM it returns the number of timer ticks per second.
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* Return the number of timer ticks per second.
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*/
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ulong get_tbclk(void)
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{
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return timer_freq;
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return gd->timer_rate_hz;
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}
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@ -18,6 +18,7 @@
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#if defined(CONFIG_AT91RM9200)
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#include <asm/arch-at91/at91rm9200.h>
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#define AT91_PMC_UHP AT91RM9200_PMC_UHP
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#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
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#include <asm/arch/at91sam9260.h>
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#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
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@ -47,6 +47,20 @@ typedef struct global_data {
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#ifdef CONFIG_FSL_ESDHC
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unsigned long sdhc_clk;
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#endif
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#ifdef CONFIG_AT91FAMILY
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/* "static data" needed by at91's clock.c */
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unsigned long cpu_clk_rate_hz;
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unsigned long main_clk_rate_hz;
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unsigned long mck_rate_hz;
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unsigned long plla_rate_hz;
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unsigned long pllb_rate_hz;
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unsigned long at91_pllb_usb_init;
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/* "static data" needed by at91's timer.c */
|
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unsigned long timer_rate_hz;
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unsigned long tbl;
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unsigned long tbu;
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unsigned long long timer_reset_value;
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#endif
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#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
|
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unsigned long relocaddr; /* Start address of U-Boot in RAM */
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phys_size_t ram_size; /* RAM size */
|
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|
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@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
|
||||
|
||||
COBJS-y += $(BOARD).o
|
||||
COBJS-y += led.o
|
||||
COBJS-y += misc.o
|
||||
ifdef CONFIG_HAS_DATAFLASH
|
||||
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
|
||||
COBJS-y += partition.o
|
||||
endif
|
||||
|
||||
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
|
||||
OBJS := $(addprefix $(obj),$(COBJS-y))
|
||||
|
||||
@ -1,4 +1,8 @@
|
||||
/*
|
||||
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
|
||||
*
|
||||
* derived from previous work
|
||||
*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
@ -23,78 +27,44 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <exports.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/at91_pio.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
#include <asm/io.h>
|
||||
#if defined(CONFIG_DRIVER_ETHER)
|
||||
#include <at91rm9200_net.h>
|
||||
#include <dm9161.h>
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/*
|
||||
* Miscelaneous platform dependent initialisations
|
||||
*/
|
||||
|
||||
int board_init (void)
|
||||
int board_init(void)
|
||||
{
|
||||
/* Enable Ctrlc */
|
||||
console_init_f ();
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
|
||||
/*
|
||||
* Correct IRDA resistor problem
|
||||
* Set PA23_TXD in Output
|
||||
*/
|
||||
writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
|
||||
|
||||
/*
|
||||
* memory and cpu-speed are setup before relocation
|
||||
* so we do _nothing_ here
|
||||
*/
|
||||
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
|
||||
|
||||
/* arch number of AT91RM9200EK-Board */
|
||||
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
|
||||
/* adress of boot parameters */
|
||||
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
|
||||
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dram_init (void)
|
||||
{
|
||||
gd->bd->bi_dram[0].start = PHYS_SDRAM;
|
||||
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
|
||||
/* dram_init must store complete ramsize in gd->ram_size */
|
||||
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
|
||||
CONFIG_SYS_SDRAM_SIZE);
|
||||
return 0;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
|
||||
/*
|
||||
* Name:
|
||||
* at91rm9200_GetPhyInterface
|
||||
* Description:
|
||||
* Initialise the interface functions to the PHY
|
||||
* Arguments:
|
||||
* None
|
||||
* Return value:
|
||||
* None
|
||||
*/
|
||||
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
|
||||
{
|
||||
p_phyops->Init = dm9161_InitPhy;
|
||||
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
|
||||
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
|
||||
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DRIVER_AT91EMAC
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
int rc = 0;
|
||||
rc = at91emac_register(bis, 0);
|
||||
return rc;
|
||||
return at91emac_register(bis, (u32) AT91_EMAC_BASE);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -1 +1,2 @@
|
||||
CONFIG_SYS_TEXT_BASE = 0x21f00000
|
||||
# currently only NOR flash booting is supported
|
||||
CONFIG_SYS_TEXT_BASE = 0x10000000
|
||||
|
||||
@ -3,6 +3,9 @@
|
||||
* Atmel Nordic AB <www.atmel.com>
|
||||
* Ulf Samuelsson <ulf@atmel.com>
|
||||
*
|
||||
* (C) Copyright 2010
|
||||
* Andreas Bießmann <andreas.devel@gmail.com>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
@ -23,67 +26,62 @@
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/at91_pmc.h>
|
||||
|
||||
#define GREEN_LED AT91C_PIO_PB0
|
||||
#define YELLOW_LED AT91C_PIO_PB1
|
||||
#define RED_LED AT91C_PIO_PB2
|
||||
/* bit mask in PIO port B */
|
||||
#define GREEN_LED (1<<0)
|
||||
#define YELLOW_LED (1<<1)
|
||||
#define RED_LED (1<<2)
|
||||
|
||||
void green_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(GREEN_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(GREEN_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void yellow_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(YELLOW_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(YELLOW_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void red_LED_on(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(RED_LED, PIOB->PIO_CODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(RED_LED, &pio->piob.codr);
|
||||
}
|
||||
|
||||
void green_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(GREEN_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(GREEN_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
void yellow_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(YELLOW_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(YELLOW_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
void red_LED_off(void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
|
||||
writel(RED_LED, PIOB->PIO_SODR);
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
writel(RED_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
|
||||
void coloured_LED_init (void)
|
||||
{
|
||||
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
|
||||
AT91PS_PMC PMC = AT91C_BASE_PMC;
|
||||
at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
|
||||
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
|
||||
|
||||
/* Enable PIOB clock */
|
||||
writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
|
||||
writel(1 << AT91_ID_PIOB, &pmc->pcer);
|
||||
|
||||
/* Disable peripherals on LEDs */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
|
||||
/* Enable pins as outputs */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
|
||||
/* Turn all LEDs OFF */
|
||||
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
|
||||
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
|
||||
}
|
||||
|
||||
@ -1,50 +0,0 @@
|
||||
/*
|
||||
* (C) Copyright 2002
|
||||
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
|
||||
* Marius Groeger <mgroeger@sysgo.de>
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/arch/AT91RM9200.h>
|
||||
#include <at91rm9200_net.h>
|
||||
#include <dm9161.h>
|
||||
#include <net.h>
|
||||
|
||||
int board_late_init(void)
|
||||
{
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
|
||||
eth_init(gd->bd);
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* checks if addr is in RAM */
|
||||
int addr2ram(ulong addr)
|
||||
{
|
||||
int result = 0;
|
||||
|
||||
if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
|
||||
result = 1;
|
||||
|
||||
return result;
|
||||
}
|
||||
@ -1,38 +0,0 @@
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <asm/io.h>
|
||||
#include <dataflash.h>
|
||||
|
||||
int AT91F_GetMuxStatus(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
|
||||
if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
|
||||
return 1;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void AT91F_SelectMMC(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
/* Set Output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_SODR);
|
||||
}
|
||||
|
||||
void AT91F_SelectSPI(void)
|
||||
{
|
||||
/* Set in PIO mode */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
|
||||
/* Configure in output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
|
||||
/* Clear Output */
|
||||
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_CODR);
|
||||
}
|
||||
@ -1,38 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <config.h>
|
||||
#include <asm/hardware.h>
|
||||
#include <dataflash.h>
|
||||
|
||||
AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
|
||||
|
||||
struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
|
||||
{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
|
||||
};
|
||||
|
||||
/*define the area offsets*/
|
||||
dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
|
||||
{0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
|
||||
{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
|
||||
{0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
|
||||
{0x00042000, 0x00251FFF, FLAG_PROTECT_CLEAR, 0, "Kernel"},
|
||||
{0x00252000, 0xFFFFFFFF, FLAG_PROTECT_CLEAR, 0, "FS"},
|
||||
};
|
||||
@ -344,7 +344,7 @@ modnet50 arm arm720t
|
||||
lpc2292sodimm arm arm720t - - lpc2292
|
||||
eb_cpux9k2 arm arm920t - BuS at91
|
||||
at91rm9200dk arm arm920t - atmel at91rm9200
|
||||
at91rm9200ek arm arm920t - atmel at91rm9200
|
||||
at91rm9200ek arm arm920t - atmel at91
|
||||
sbc2410x arm arm920t - - s3c24x0
|
||||
smdk2400 arm arm920t - samsung s3c24x0
|
||||
smdk2410 arm arm920t - samsung s3c24x0
|
||||
|
||||
@ -1,4 +1,8 @@
|
||||
/*
|
||||
* Copyright (C) 2010 Andreas Bießmann <biessmann.devel@googlemail.com>
|
||||
*
|
||||
* based on previous work by
|
||||
*
|
||||
* Ulf Samuelsson <ulf@atmel.com>
|
||||
* Rick Bronson <rick@efn.org>
|
||||
*
|
||||
@ -23,40 +27,52 @@
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
#ifndef __AT91RM9200EK_CONFIG_H__
|
||||
#define __AT91RM9200EK_CONFIG_H__
|
||||
|
||||
#define CONFIG_AT91_LEGACY
|
||||
#include <asm/sizes.h>
|
||||
|
||||
/* ARM asynchronous clock */
|
||||
/*
|
||||
* from 18.432 MHz crystal
|
||||
* (18432000 / 4 * 39)
|
||||
* AT91C_XTAL_CLOCK is the frequency of external xtal in hertz
|
||||
* AT91C_MAIN_CLOCK is the frequency of PLLA output
|
||||
* AT91C_MASTER_CLOCK is the peripherial clock
|
||||
* CONFIG_SYS_HZ_CLOCK is the value for CCR in tc0 (divider 2 is implicitely
|
||||
* set in arch/arm/cpu/arm920t/at91/timer.c)
|
||||
* CONFIG_SYS_HZ is the tick rate for timer tc0
|
||||
*/
|
||||
#define AT91C_MAIN_CLOCK 179712000
|
||||
#define AT91C_XTAL_CLOCK 18432000
|
||||
#define AT91C_MAIN_CLOCK ((AT91C_XTAL_CLOCK / 4) * 39)
|
||||
#define AT91C_MASTER_CLOCK (AT91C_MAIN_CLOCK / 3 )
|
||||
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
|
||||
/* CPU configuration */
|
||||
#define CONFIG_ARM920T
|
||||
#define CONFIG_AT91RM9200
|
||||
#define CONFIG_AT91RM9200EK
|
||||
#define CONFIG_CPUAT91
|
||||
#define USE_920T_MMU
|
||||
|
||||
#define CONFIG_CMDLINE_TAG
|
||||
#define CONFIG_SETUP_MEMORY_TAGS
|
||||
#define CONFIG_INITRD_TAG
|
||||
|
||||
/*
|
||||
* peripheral clock
|
||||
* (AT91C_MASTER_CLOCK / 3)
|
||||
* Memory Configuration
|
||||
*/
|
||||
#define AT91C_MASTER_CLOCK 59904000
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define CONFIG_SYS_SDRAM_BASE 0x20000000
|
||||
#define CONFIG_SYS_SDRAM_SIZE SZ_32M
|
||||
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
|
||||
#define CONFIG_AT91RM9200 1 /* It's an Atmel AT91RM9200 SoC */
|
||||
#define CONFIG_AT91RM9200EK 1 /* on an AT91RM9200EK Board */
|
||||
#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
|
||||
#define USE_920T_MMU 1
|
||||
|
||||
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
|
||||
#define CONFIG_SETUP_MEMORY_TAGS 1
|
||||
#define CONFIG_INITRD_TAG 1
|
||||
#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + CONFIG_SYS_SDRAM_SIZE - SZ_256K)
|
||||
|
||||
/*
|
||||
* LowLevel Init
|
||||
*/
|
||||
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
#define CONFIG_SYS_USE_MAIN_OSCILLATOR 1
|
||||
#define CONFIG_SYS_USE_MAIN_OSCILLATOR
|
||||
/* flash */
|
||||
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
|
||||
#define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
|
||||
@ -73,50 +89,26 @@
|
||||
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
|
||||
#define CONFIG_SYS_EBI_CSA_VAL 0x00000002 /* CS1=CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_CR_VAL 0x2188c155 /* set up the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM 0x20000000 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM1 0x20000080 /* address of the CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
|
||||
#define CONFIG_SYS_SDRAM1 CONFIG_SYS_SDRAM_BASE /* address of the SDRAM */
|
||||
#define CONFIG_SYS_SDRAM_VAL 0x00000000 /* value written to CONFIG_SYS_SDRAM */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL 0x00000002 /* Precharge All */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
|
||||
#define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
|
||||
#define CONFIG_SYS_SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
|
||||
#else
|
||||
#define CONFIG_SKIP_RELOCATE_UBOOT
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
/* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
|
||||
#define CONFIG_SYS_AT91C_BRGR_DIVISOR 33
|
||||
|
||||
/*
|
||||
* Memory Configuration
|
||||
*/
|
||||
#define CONFIG_NR_DRAM_BANKS 1
|
||||
#define PHYS_SDRAM 0x20000000
|
||||
#define PHYS_SDRAM_SIZE 0x02000000 /* 32 megs */
|
||||
|
||||
#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
|
||||
#define CONFIG_SYS_MEMTEST_END \
|
||||
(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
|
||||
|
||||
/*
|
||||
* Hardware drivers
|
||||
*/
|
||||
|
||||
/*
|
||||
* UART Configuration
|
||||
*
|
||||
* define one of these to choose the DBGU,
|
||||
* USART0 or USART1 as console
|
||||
* Choose a USART for serial console
|
||||
* CONFIG_DBGU is DBGU unit on J10
|
||||
* CONFIG_USART1 is USART1 on J14
|
||||
*/
|
||||
#define CONFIG_AT91RM9200_USART
|
||||
#define CONFIG_DBGU
|
||||
#undef CONFIG_USART0
|
||||
#undef CONFIG_USART1
|
||||
/* don't include RTS/CTS flow control support */
|
||||
#undef CONFIG_HWFLOW
|
||||
/* disable modem initialization stuff */
|
||||
#undef CONFIG_MODEM_SUPPORT
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
|
||||
#define CONFIG_BAUDRATE 115200
|
||||
@ -130,156 +122,75 @@
|
||||
#define CONFIG_CMD_FAT
|
||||
#define CONFIG_CMD_MII
|
||||
#define CONFIG_CMD_PING
|
||||
|
||||
#undef CONFIG_CMD_BDI
|
||||
#undef CONFIG_CMD_IMI
|
||||
#define CONFIG_CMD_USB
|
||||
#undef CONFIG_CMD_FPGA
|
||||
#undef CONFIG_CMD_MISC
|
||||
#undef CONFIG_CMD_LOADS
|
||||
|
||||
#include <asm/arch/AT91RM9200.h> /* needed for port definitions */
|
||||
/* Options for MMC/SD Card */
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#undef CONFIG_MMC
|
||||
#define CONFIG_SYS_MMC_BASE 0xFFFB4000
|
||||
#define CONFIG_SYS_MMC_BLOCKSIZE 512
|
||||
|
||||
/*
|
||||
* Network Driver Setting
|
||||
*/
|
||||
#define CONFIG_NET_MULTI 1
|
||||
#ifdef CONFIG_NET_MULTI
|
||||
#define CONFIG_DRIVER_AT91EMAC 1
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 8
|
||||
#else
|
||||
#define CONFIG_DRIVER_ETHER 1
|
||||
#endif
|
||||
#define CONFIG_NET_RETRY_COUNT 20
|
||||
#define CONFIG_AT91C_USE_RMII
|
||||
|
||||
/*
|
||||
* AC Characteristics
|
||||
* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
|
||||
*/
|
||||
#define DATAFLASH_TCSS (0xC << 16)
|
||||
#define DATAFLASH_TCHS (0x1 << 24)
|
||||
|
||||
#if defined(CONFIG_HAS_DATAFLASH)
|
||||
#define CONFIG_SYS_SPI_WRITE_TOUT (5 * CONFIG_SYS_HZ)
|
||||
#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
|
||||
#define CONFIG_SYS_MAX_DATAFLASH_PAGES 16384
|
||||
/* Logical adress for CS0 */
|
||||
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000
|
||||
/* Logical adress for CS3 */
|
||||
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000
|
||||
#define CONFIG_SYS_SUPPORT_BLOCK_ERASE 1
|
||||
#define CONFIG_SYS_DATAFLASH_MMC_PIO AT91C_PIO_PB22
|
||||
#endif
|
||||
#define CONFIG_NET_MULTI
|
||||
#define CONFIG_DRIVER_AT91EMAC
|
||||
#define CONFIG_SYS_RX_ETH_BUFFER 16
|
||||
#define CONFIG_RMII
|
||||
#define CONFIG_MII
|
||||
|
||||
/*
|
||||
* NOR Flash
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define PHYS_FLASH_SIZE 0x800000 /* 8MB */
|
||||
#define CONFIG_SYS_FLASH_CFI 1
|
||||
#define CONFIG_FLASH_CFI_DRIVER 1
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_BASE 0x10000000
|
||||
#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
|
||||
#define PHYS_FLASH_SIZE SZ_8M
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 256
|
||||
#define CONFIG_SYS_FLASH_PROTECTION
|
||||
|
||||
/*
|
||||
* Environment Settings
|
||||
*/
|
||||
#ifdef CONFIG_ENV_IS_IN_DATAFLASH
|
||||
/*
|
||||
* Datasflash Environment Settings
|
||||
*/
|
||||
#define CONFIG_ENV_OFFSET 0x4200
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
|
||||
/* 8 * 1056 really , but start.s is not OK with this*/
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
|
||||
#else
|
||||
/*
|
||||
* NOR Flash Environment Settings
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/*
|
||||
* between boot.bin and u-boot.bin.gz
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0xe000)
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
#else
|
||||
/*
|
||||
* after u-boot.bin
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SIZE 0x10000 /* sectors are 64K here */
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN \
|
||||
(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#endif /* CONFIG_ENV_IS_IN_DATAFLASH */
|
||||
|
||||
/*
|
||||
* Boot option
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
#ifdef CONFIG_SKIP_LOWLEVEL_INIT
|
||||
/* boot.bin, env, u-boot.bin.gz */
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x6000 /* 24 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE (CONFIG_SYS_FLASH_BASE + 0x10000)
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x10000 /* 64 KBytes */
|
||||
#else
|
||||
/* u-boot.bin */
|
||||
#define CONFIG_SYS_BOOT_SIZE 0x0 /* 0 KBytes */
|
||||
#define CONFIG_SYS_U_BOOT_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_U_BOOT_SIZE 0x40000 /* 128 KBytes */
|
||||
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
|
||||
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
|
||||
#define CONFIG_ENV_OVERWRITE 1
|
||||
|
||||
/*
|
||||
* USB Config
|
||||
*/
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_USB_KEYBOARD 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
#define CONFIG_USB_ATMEL 1
|
||||
#define CONFIG_USB_OHCI_NEW 1
|
||||
#define CONFIG_USB_KEYBOARD 1
|
||||
#define CONFIG_USB_STORAGE 1
|
||||
#define CONFIG_DOS_PARTITION 1
|
||||
|
||||
#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
|
||||
#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
|
||||
#define CONFIG_SYS_USB_OHCI_REGS_BASE AT91_USB_HOST_BASE
|
||||
#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91rm9200"
|
||||
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
|
||||
|
||||
/*
|
||||
* I2C
|
||||
* Environment Settings
|
||||
*/
|
||||
#define CONFIG_HARD_I2C
|
||||
#define CONFIG_ENV_IS_IN_FLASH
|
||||
|
||||
#ifdef CONFIG_HARD_I2C
|
||||
#define CONFIG_CMD_I2C
|
||||
#define CONFIG_SYS_I2C_SPEED 0 /* not used */
|
||||
#define CONFIG_SYS_I2C_SLAVE 0 /* not used */
|
||||
#endif
|
||||
/*
|
||||
* after u-boot.bin
|
||||
*/
|
||||
#define CONFIG_ENV_ADDR \
|
||||
(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
|
||||
#define CONFIG_ENV_SIZE SZ_64K /* sectors are 64K here */
|
||||
/* The following #defines are needed to get flash environment right */
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_MONITOR_LEN SZ_256K
|
||||
|
||||
/*
|
||||
* Boot option
|
||||
*/
|
||||
#define CONFIG_BOOTDELAY 3
|
||||
|
||||
/* default load address */
|
||||
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + SZ_16M
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
/*
|
||||
* Shell Settings
|
||||
*/
|
||||
#define CONFIG_CMDLINE_EDITING 1
|
||||
#define CONFIG_SYS_LONGHELP 1
|
||||
#define CONFIG_AUTO_COMPLETE 1
|
||||
#define CONFIG_SYS_HUSH_PARSER 1
|
||||
#define CONFIG_CMDLINE_EDITING
|
||||
#define CONFIG_SYS_LONGHELP
|
||||
#define CONFIG_AUTO_COMPLETE
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
#define CONFIG_SYS_PROMPT "U-Boot> "
|
||||
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
@ -288,41 +199,18 @@
|
||||
#define CONFIG_SYS_PBSIZE \
|
||||
(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
/*-----------------------------------------------------------------------
|
||||
* Board specific extension for bd_info
|
||||
*
|
||||
* This structure is embedded in the global bd_info (bd_t) structure
|
||||
* and can be used by the board specific code (eg board/...)
|
||||
*/
|
||||
|
||||
struct bd_info_ext {
|
||||
/* helper variable for board environment handling
|
||||
*
|
||||
* env_crc_valid == 0 => uninitialised
|
||||
* env_crc_valid > 0 => environment crc in flash is valid
|
||||
* env_crc_valid < 0 => environment crc in flash is invalid
|
||||
*/
|
||||
int env_crc_valid;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_HZ 1000
|
||||
/*
|
||||
* AT91C_TC0_CMR is implicitly set to
|
||||
* AT91C_TC_TIMER_DIV1_CLOCK
|
||||
*/
|
||||
#define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
|
||||
|
||||
/*
|
||||
* Size of malloc() pool
|
||||
*/
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
|
||||
, 0x1000)
|
||||
#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + SZ_128K, \
|
||||
SZ_4K)
|
||||
/* size in bytes reserved for initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128
|
||||
|
||||
#define CONFIG_STACKSIZE (32 * 1024) /* regular stack */
|
||||
#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* Unsure if to big or to small*/
|
||||
#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* Unsure if to big or to small*/
|
||||
#endif
|
||||
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
|
||||
- CONFIG_SYS_GBL_DATA_SIZE)
|
||||
|
||||
#define CONFIG_STACKSIZE SZ_32K /* regular stack */
|
||||
#define CONFIG_STACKSIZE_IRQ SZ_4K /* Unsure if to big or to small*/
|
||||
#define CONFIG_STACKSIZE_FIQ SZ_4K /* Unsure if to big or to small*/
|
||||
#endif /* __AT91RM9200EK_CONFIG_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user