ARM: tegra: Rename pcie-controller to pcie
Recent versions of DTC have checks for PCI host bridge device tree nodes that are named something other than "pci" or "pcie". Fix all occurrences of such nodes for Tegra boards to avoid potential warnings from DTC. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -77,7 +77,7 @@
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reg = <0x0 0x80000000 0x0 0x80000000>;
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};
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pcie-controller@01003000 {
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pcie@1003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05>;
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avdd-pex-pll-supply = <&vdd_1v05>;
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@ -29,7 +29,7 @@
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reg = <0x80000000 0x80000000>;
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};
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pcie-controller@01003000 {
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pcie@1003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05_run>;
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@ -29,7 +29,7 @@
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reg = <0x80000000 0x80000000>;
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};
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pcie-controller@01003000 {
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pcie@1003000 {
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status = "okay";
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avddio-pex-supply = <&vdd_1v05_run>;
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@ -14,7 +14,7 @@
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interrupt-parent = <&lic>;
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pcie-controller@01003000 {
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pcie@1003000 {
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compatible = "nvidia,tegra124-pcie";
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device_type = "pci";
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reg = <0x01003000 0x00000800 /* PADS registers */
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@ -11,7 +11,7 @@
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power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
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};
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pcie-controller@10003000 {
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pcie@10003000 {
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status = "okay";
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pci@1,0 {
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@ -11,7 +11,7 @@
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power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
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};
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pcie-controller@10003000 {
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pcie@10003000 {
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status = "okay";
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pci@1,0 {
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@ -217,7 +217,7 @@
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#interrupt-cells = <2>;
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};
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pcie-controller@10003000 {
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pcie@10003000 {
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compatible = "nvidia,tegra186-pcie";
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device_type = "pci";
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reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */
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@ -599,7 +599,7 @@
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nvidia,sys-clock-req-active-high;
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};
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pcie-controller@80003000 {
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pcie@80003000 {
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status = "okay";
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avdd-pex-supply = <&pci_vdd_reg>;
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@ -30,7 +30,7 @@
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spi-max-frequency = <25000000>;
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};
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pcie-controller@80003000 {
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pcie@80003000 {
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status = "okay";
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avdd-pex-supply = <&pci_vdd_reg>;
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@ -580,7 +580,7 @@
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reset-names = "fuse";
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};
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pcie-controller@80003000 {
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pcie@80003000 {
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compatible = "nvidia,tegra20-pcie";
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device_type = "pci";
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reg = <0x80003000 0x00000800 /* PADS registers */
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@ -21,7 +21,7 @@
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reg = <0x0 0x80000000 0x0 0xc0000000>;
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};
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pcie-controller@01003000 {
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pcie@1003000 {
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status = "okay";
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pci@1,0 {
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@ -11,7 +11,7 @@
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#address-cells = <2>;
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#size-cells = <2>;
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pcie-controller@01003000 {
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pcie@1003000 {
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compatible = "nvidia,tegra210-pcie";
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device_type = "pci";
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reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */
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@ -32,7 +32,7 @@
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reg = <0x80000000 0x40000000>;
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};
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pcie-controller@00003000 {
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pcie@3000 {
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status = "okay";
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avdd-pexa-supply = <&vdd2_reg>;
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vdd-pexa-supply = <&vdd2_reg>;
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@ -28,7 +28,7 @@
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reg = <0x80000000 0x7ff00000>;
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};
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pcie-controller@00003000 {
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pcie@3000 {
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status = "okay";
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avdd-pexa-supply = <&ldo1_reg>;
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@ -27,7 +27,7 @@
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reg = <0x80000000 0x40000000>;
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};
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pcie-controller@00003000 {
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pcie@3000 {
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status = "okay";
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/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
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@ -10,7 +10,7 @@
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compatible = "nvidia,tegra30";
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interrupt-parent = <&lic>;
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pcie-controller@00003000 {
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pcie@3000 {
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compatible = "nvidia,tegra30-pcie";
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device_type = "pci";
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reg = <0x00003000 0x00000800 /* PADS registers */
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