ARM: tegra: Rename pcie-controller to pcie

Recent versions of DTC have checks for PCI host bridge device tree nodes
that are named something other than "pci" or "pcie". Fix all occurrences
of such nodes for Tegra boards to avoid potential warnings from DTC.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Thierry Reding 2019-04-15 11:32:37 +02:00 committed by Tom Warren
parent c79aa81dbc
commit 1e669b4808
16 changed files with 16 additions and 16 deletions

View File

@ -77,7 +77,7 @@
reg = <0x0 0x80000000 0x0 0x80000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05>;
avdd-pex-pll-supply = <&vdd_1v05>;

View File

@ -29,7 +29,7 @@
reg = <0x80000000 0x80000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;

View File

@ -29,7 +29,7 @@
reg = <0x80000000 0x80000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
avddio-pex-supply = <&vdd_1v05_run>;

View File

@ -14,7 +14,7 @@
interrupt-parent = <&lic>;
pcie-controller@01003000 {
pcie@1003000 {
compatible = "nvidia,tegra124-pcie";
device_type = "pci";
reg = <0x01003000 0x00000800 /* PADS registers */

View File

@ -11,7 +11,7 @@
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 5) GPIO_ACTIVE_HIGH>;
};
pcie-controller@10003000 {
pcie@10003000 {
status = "okay";
pci@1,0 {

View File

@ -11,7 +11,7 @@
power-gpios = <&gpio_main TEGRA_MAIN_GPIO(P, 6) GPIO_ACTIVE_HIGH>;
};
pcie-controller@10003000 {
pcie@10003000 {
status = "okay";
pci@1,0 {

View File

@ -217,7 +217,7 @@
#interrupt-cells = <2>;
};
pcie-controller@10003000 {
pcie@10003000 {
compatible = "nvidia,tegra186-pcie";
device_type = "pci";
reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */

View File

@ -599,7 +599,7 @@
nvidia,sys-clock-req-active-high;
};
pcie-controller@80003000 {
pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;

View File

@ -30,7 +30,7 @@
spi-max-frequency = <25000000>;
};
pcie-controller@80003000 {
pcie@80003000 {
status = "okay";
avdd-pex-supply = <&pci_vdd_reg>;

View File

@ -580,7 +580,7 @@
reset-names = "fuse";
};
pcie-controller@80003000 {
pcie@80003000 {
compatible = "nvidia,tegra20-pcie";
device_type = "pci";
reg = <0x80003000 0x00000800 /* PADS registers */

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@ -21,7 +21,7 @@
reg = <0x0 0x80000000 0x0 0xc0000000>;
};
pcie-controller@01003000 {
pcie@1003000 {
status = "okay";
pci@1,0 {

View File

@ -11,7 +11,7 @@
#address-cells = <2>;
#size-cells = <2>;
pcie-controller@01003000 {
pcie@1003000 {
compatible = "nvidia,tegra210-pcie";
device_type = "pci";
reg = <0x0 0x01003000 0x0 0x00000800 /* PADS registers */

View File

@ -32,7 +32,7 @@
reg = <0x80000000 0x40000000>;
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
avdd-pexa-supply = <&vdd2_reg>;
vdd-pexa-supply = <&vdd2_reg>;

View File

@ -28,7 +28,7 @@
reg = <0x80000000 0x7ff00000>;
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
avdd-pexa-supply = <&ldo1_reg>;

View File

@ -27,7 +27,7 @@
reg = <0x80000000 0x40000000>;
};
pcie-controller@00003000 {
pcie@3000 {
status = "okay";
/* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */

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@ -10,7 +10,7 @@
compatible = "nvidia,tegra30";
interrupt-parent = <&lic>;
pcie-controller@00003000 {
pcie@3000 {
compatible = "nvidia,tegra30-pcie";
device_type = "pci";
reg = <0x00003000 0x00000800 /* PADS registers */