nds32/ag102: add header support of ag102 soc
Add device address offsets header of ag102 soc. Add ag102 into mach-types.h. Add asm-offsets.c for helping convert C headers into asm. Signed-off-by: Macpaul Lin <macpaul@andestech.com>
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Macpaul Lin
Macpaul Lin
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2790bf69dc
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54
arch/nds32/cpu/n1213/ag102/asm-offsets.c
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54
arch/nds32/cpu/n1213/ag102/asm-offsets.c
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/*
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* Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
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*
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* Generate definitions needed by assembly language modules.
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* This code generates raw asm output which is post-processed to extract
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* and format the required data.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <linux/kbuild.h>
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int main(void)
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{
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#ifdef CONFIG_FTSMC020
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OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
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OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
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#endif
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BLANK();
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#ifdef CONFIG_FTAHBC020S
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OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
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OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
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#endif
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BLANK();
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#ifdef CONFIG_ANDES_PCU
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OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
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#endif
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BLANK();
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#ifdef CONFIG_DWCDDR21MCTL
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OFFSET(DWCDDR21MCTL_CCR, dwcddr21mctl, ccr); /* 0x04 */
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OFFSET(DWCDDR21MCTL_DCR, dwcddr21mctl, dcr); /* 0x04 */
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OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr); /* 0x08 */
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OFFSET(DWCDDR21MCTL_CSR, dwcddr21mctl, csr); /* 0x0c */
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OFFSET(DWCDDR21MCTL_DRR, dwcddr21mctl, drr); /* 0x10 */
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OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
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OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
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OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
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OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
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OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
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OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
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OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
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OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
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OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
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OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
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OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
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OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
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OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar); /* 0xa4 */
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OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
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#endif
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return 0;
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}
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97
arch/nds32/include/asm/arch-ag102/ag102.h
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arch/nds32/include/asm/arch-ag102/ag102.h
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __AG102_H
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#define __AG102_H
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/*
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* Hardware register bases
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*/
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/* PCI Controller */
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#define CONFIG_FTPCI100_BASE 0x90000000
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/* LPC Controller */
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#define CONFIG_LPC_IO_BASE 0x90100000
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/* LPC Controller */
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#define CONFIG_LPC_BASE 0x90200000
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/* NDS32 Data Local Memory 01 */
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#define CONFIG_NDS_DLM1_BASE 0x90300000
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/* NDS32 Data Local Memory 02 */
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#define CONFIG_NDS_DLM2_BASE 0x90400000
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/* Synopsys DWC DDR2/1 Controller */
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#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
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/* DMA Controller */
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#define CONFIG_FTDMAC020_BASE 0x90600000
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/* FTIDE020_S IDE (ATA) Controller */
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#define CONFIG_FTIDE020S_BASE 0x90700000
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/* USB OTG Controller */
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#define CONFIG_FZOTG266HD0A_BASE 0x90800000
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/* Andes L2 Cache Controller */
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#define CONFIG_NCEL2C100_BASE 0x90900000
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/* XGI XG22 GPU */
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#define CONFIG_XGI_XG22_BASE 0x90A00000
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/* GMAC Ethernet Controller */
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#define CONFIG_FTGMAC100_BASE 0x90B00000
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/* AHB Controller */
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#define CONFIG_FTAHBC020S_BASE 0x90C00000
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/* AHB-to-APB Bridge Controller */
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#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
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/* External AHB2AHB Controller */
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#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
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/* Andes Multi-core Interrupt Controller */
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#define CONFIG_NCEMIC100_BASE 0x90F00000
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/*
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* APB Device definitions
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*/
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/* Compat Flash Controller */
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#define CONFIG_FTCFC010_BASE 0x94000000
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/* APB - SSP (SPI) (without AC97) Controller */
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#define CONFIG_FTSSP010_01_BASE 0x94100000
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/* UART1 - APB STUART Controller (UART0 in Linux) */
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#define CONFIG_FTUART010_01_BASE 0x94200000
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/* FTSDC010 SD Controller */
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#define CONFIG_FTSDC010_BASE 0x94400000
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/* APB - SSP with HDA/AC97 Controller */
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#define CONFIG_FTSSP010_02_BASE 0x94500000
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/* UART2 - APB STUART Controller (UART1 in Linux) */
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#define CONFIG_FTUART010_02_BASE 0x94600000
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/* PCU Controller */
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#define CONFIG_ANDES_PCU_BASE 0x94800000
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/* FTTMR010 Timer */
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#define CONFIG_FTTMR010_BASE 0x94900000
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/* Watch Dog Controller */
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#define CONFIG_FTWDT010_BASE 0x94A00000
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/* FTRTC010 Real Time Clock */
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#define CONFIG_FTRTC010_BASE 0x98B00000
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/* GPIO Controller */
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#define CONFIG_FTGPIO010_BASE 0x94C00000
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/* I2C Controller */
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#define CONFIG_FTIIC010_BASE 0x94E00000
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/* PWM - Pulse Width Modulator Controller */
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#define CONFIG_FTPWM010_BASE 0x94F00000
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/* Debug LED */
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#define CONFIG_DEBUG_LED 0x902FFFFC
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/* Power Management Unit */
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#define CONFIG_FTPMU010_BASE 0x98100000
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#endif /* __AG102_H */
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@ -40,4 +40,18 @@ extern unsigned int __machine_arch_type;
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# define machine_is_adpag101p() (1)
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#endif
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#define MACH_TYPE_ADPAG102 2
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#ifdef CONFIG_ARCH_ADPAG102
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# ifdef machine_arch_type
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# undef machine_arch_type
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# define machine_arch_type __machine_arch_type
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# else
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# define machine_arch_type MACH_TYPE_ADPAG102
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# endif
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# define machine_is_adpag102() (machine_arch_type == MACH_TYPE_ADPAG102)
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#else
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# define machine_is_adpag102() (2)
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#endif
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#endif /* __ASM_NDS32_MACH_TYPE_H */
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