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clk: versal: Enable only GATE type clocks

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Clocks should be enabled or disabled only if they are of GATE type
clocks. If they are not of GATE type clocks, don't touch them.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1632808827-6109-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
T Karthik Reddy 2021-09-28 11:30:27 +05:30 committed by Michal Simek
parent 0285d75a93
commit 1db1acbb84
1 changed files with 4 additions and 1 deletions
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5
drivers/clk/clk_versal.c
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@ -725,7 +725,10 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[clk->id].clk_id;
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
if (versal_clock_gate(clk_id))
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0, NULL);
return 0;
}
static struct clk_ops versal_clk_ops = {