Patch by Steven Scholz, 16 Aug 2004:
- Introducing the concept of SoCs "./cpu/$(CPU)/$(SOC)" - creating subdirs for SoCs ./cpu/arm920t/imx and ./cpu/arm920t/s3c24x0 - moving SoC specific code out of cpu/arm920t/ into cpu/arm920t/$(SOC)/ - moving drivers/s3c24x0_i2c.c and drivers/serial_imx.c out of drivers/ into cpu/arm920t/$(SOC)/
This commit is contained in:
wdenk
@@ -26,11 +26,7 @@ include $(TOPDIR)/config.mk
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LIB = lib$(CPU).a
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START = start.o
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OBJS = cpu.o \
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imx_generic.o imx_interrupts.o imx_speed.o \
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interrupts.o \
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s3c24x0_interrupts.o s3c24x0_serial.o s3c24x0_speed.o \
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usb_ohci.o
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OBJS = cpu.o interrupts.o
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all: .depend $(START) $(LIB)
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42
cpu/arm920t/imx/Makefile
Normal file
42
cpu/arm920t/imx/Makefile
Normal file
@@ -0,0 +1,42 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# See file CREDITS for list of people who contributed to this
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# project.
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License as
|
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# published by the Free Software Foundation; either version 2 of
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||||
# the License, or (at your option) any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(SOC).a
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OBJS = generic.o interrupts.o serial.o speed.o
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all: .depend $(LIB)
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$(LIB): $(OBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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201
cpu/arm920t/imx/serial.c
Normal file
201
cpu/arm920t/imx/serial.c
Normal file
@@ -0,0 +1,201 @@
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/*
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* (c) 2004 Sascha Hauer <sascha@saschahauer.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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||||
* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#if defined (CONFIG_IMX)
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#include <asm/arch/imx-regs.h>
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#ifndef CONFIG_IMX_SERIAL_NONE
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#if defined CONFIG_IMX_SERIAL1
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#define UART_BASE IMX_UART1_BASE
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#elif defined CONFIG_IMX_SERIAL2
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#define UART_BASE IMX_UART2_BASE
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#else
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#error "define CONFIG_IMX_SERIAL1, CONFIG_IMX_SERIAL2 or CONFIG_IMX_SERIAL_NONE"
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#endif
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struct imx_serial {
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volatile uint32_t urxd[16];
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volatile uint32_t utxd[16];
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volatile uint32_t ucr1;
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volatile uint32_t ucr2;
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volatile uint32_t ucr3;
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volatile uint32_t ucr4;
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volatile uint32_t ufcr;
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volatile uint32_t usr1;
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volatile uint32_t usr2;
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volatile uint32_t uesc;
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volatile uint32_t utim;
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volatile uint32_t ubir;
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volatile uint32_t ubmr;
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volatile uint32_t ubrc;
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volatile uint32_t bipr[4];
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volatile uint32_t bmpr[4];
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volatile uint32_t uts;
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};
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void serial_setbrg (void)
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{
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serial_init();
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}
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extern void imx_gpio_mode(int gpio_mode);
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/*
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* Initialise the serial port with the given baudrate. The settings
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* are always 8 data bits, no parity, 1 stop bit, no start bits.
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*
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*/
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int serial_init (void)
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{
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volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
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#ifdef CONFIG_IMX_SERIAL1
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imx_gpio_mode(PC11_PF_UART1_TXD);
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imx_gpio_mode(PC12_PF_UART1_RXD);
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#else
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imx_gpio_mode(PB30_PF_UART2_TXD);
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imx_gpio_mode(PB31_PF_UART2_RXD);
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#endif
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/* Disable UART */
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base->ucr1 &= ~UCR1_UARTEN;
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/* Set to default POR state */
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base->ucr1 = 0x00000004;
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base->ucr2 = 0x00000000;
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base->ucr3 = 0x00000000;
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base->ucr4 = 0x00008040;
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base->uesc = 0x0000002B;
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base->utim = 0x00000000;
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base->ubir = 0x00000000;
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base->ubmr = 0x00000000;
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base->uts = 0x00000000;
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/* Set clocks */
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base->ucr4 |= UCR4_REF16;
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/* Configure FIFOs */
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base->ufcr = 0xa81;
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/* Set the numerator value minus one of the BRM ratio */
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base->ubir = (CONFIG_BAUDRATE / 100) - 1;
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/* Set the denominator value minus one of the BRM ratio */
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base->ubmr = 10000 - 1;
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/* Set to 8N1 */
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base->ucr2 &= ~UCR2_PREN;
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base->ucr2 |= UCR2_WS;
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base->ucr2 &= ~UCR2_STPB;
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/* Ignore RTS */
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base->ucr2 |= UCR2_IRTS;
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/* Enable UART */
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base->ucr1 |= UCR1_UARTEN | UCR1_UARTCLKEN;
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/* Enable FIFOs */
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base->ucr2 |= UCR2_SRST | UCR2_RXEN | UCR2_TXEN;
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/* Clear status flags */
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base->usr2 |= USR2_ADET |
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USR2_DTRF |
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USR2_IDLE |
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USR2_IRINT |
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USR2_WAKE |
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USR2_RTSF |
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USR2_BRCD |
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USR2_ORE |
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USR2_RDR;
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/* Clear status flags */
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base->usr1 |= USR1_PARITYERR |
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USR1_RTSD |
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USR1_ESCF |
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USR1_FRAMERR |
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USR1_AIRINT |
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USR1_AWAKE;
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return (0);
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}
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/*
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* Read a single byte from the serial port. Returns 1 on success, 0
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* otherwise. When the function is successful, the character read is
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* written into its argument c.
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*/
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int serial_getc (void)
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{
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volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
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unsigned char ch;
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while(base->uts & UTS_RXEMPTY);
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ch = (char)base->urxd[0];
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return ch;
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}
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#ifdef CONFIG_HWFLOW
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static int hwflow = 0; /* turned off by default */
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int hwflow_onoff(int on)
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{
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}
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#endif
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/*
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* Output a single byte to the serial port.
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*/
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void serial_putc (const char c)
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{
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volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
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/* Wait for Tx FIFO not full */
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while (base->uts & UTS_TXFULL);
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base->utxd[0] = c;
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/* If \n, also do \r */
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if (c == '\n')
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serial_putc ('\r');
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}
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/*
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* Test whether a character is in the RX buffer
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*/
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int serial_tstc (void)
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{
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volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
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/* If receive fifo is empty, return false */
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if (base->uts & UTS_RXEMPTY)
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return 0;
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return 1;
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}
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void
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serial_puts (const char *s)
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{
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while (*s) {
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serial_putc (*s++);
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}
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}
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#endif /* CONFIG_IMX_SERIAL_NONE */
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#endif /* defined CONFIG_IMX */
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43
cpu/arm920t/s3c24x0/Makefile
Normal file
43
cpu/arm920t/s3c24x0/Makefile
Normal file
@@ -0,0 +1,43 @@
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#
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# (C) Copyright 2000, 2001, 2002
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
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#
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# See file CREDITS for list of people who contributed to this
|
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# project.
|
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#
|
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# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
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# This program is distributed in the hope that it will be useful,
|
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
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# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
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# MA 02111-1307 USA
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#
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include $(TOPDIR)/config.mk
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LIB = lib$(SOC).a
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OBJS = i2c.o interrupts.o serial.o speed.o \
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usb_ohci.o
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all: .depend $(LIB)
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$(LIB): $(OBJS)
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$(AR) crv $@ $(OBJS)
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#########################################################################
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.depend: Makefile $(OBJS:.o=.c)
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$(CC) -M $(CFLAGS) $(OBJS:.o=.c) > $@
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sinclude .depend
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#########################################################################
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447
cpu/arm920t/s3c24x0/i2c.c
Normal file
447
cpu/arm920t/s3c24x0/i2c.c
Normal file
@@ -0,0 +1,447 @@
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/*
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* (C) Copyright 2002
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* David Mueller, ELSOFT AG, d.mueller@elsoft.ch
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*
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* See file CREDITS for list of people who contributed to this
|
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* project.
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*
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* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
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*/
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/* This code should work for both the S3C2400 and the S3C2410
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* as they seem to have the same I2C controller inside.
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* The different address mapping is handled by the s3c24xx.h files below.
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*/
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#include <common.h>
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#ifdef CONFIG_DRIVER_S3C24X0_I2C
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#if defined(CONFIG_S3C2400)
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#include <s3c2400.h>
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#elif defined(CONFIG_S3C2410)
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#include <s3c2410.h>
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#endif
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#include <i2c.h>
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#ifdef CONFIG_HARD_I2C
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#define I2C_WRITE 0
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#define I2C_READ 1
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#define I2C_OK 0
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#define I2C_NOK 1
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#define I2C_NACK 2
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#define I2C_NOK_LA 3 /* Lost arbitration */
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#define I2C_NOK_TOUT 4 /* time out */
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#define I2CSTAT_BSY 0x20 /* Busy bit */
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#define I2CSTAT_NACK 0x01 /* Nack bit */
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#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
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#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
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#define I2C_MODE_MR 0x80 /* Master Receive Mode */
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#define I2C_START_STOP 0x20 /* START / STOP */
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#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
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#define I2C_TIMEOUT 1 /* 1 second */
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static int GetI2CSDA(void)
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{
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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#ifdef CONFIG_S3C2410
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return (gpio->GPEDAT & 0x8000) >> 15;
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#endif
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#ifdef CONFIG_S3C2400
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return (gpio->PGDAT & 0x0020) >> 5;
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#endif
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}
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#if 0
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static void SetI2CSDA(int x)
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{
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rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
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}
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#endif
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static void SetI2CSCL(int x)
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{
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S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
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#ifdef CONFIG_S3C2410
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gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
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#endif
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#ifdef CONFIG_S3C2400
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gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
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#endif
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}
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static int WaitForXfer (void)
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{
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S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
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int i, status;
|
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i = I2C_TIMEOUT * 10000;
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status = i2c->IICCON;
|
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while ((i > 0) && !(status & I2CCON_IRPND)) {
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udelay (100);
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status = i2c->IICCON;
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i--;
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}
|
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return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
|
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}
|
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static int IsACK (void)
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{
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S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
|
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|
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return (!(i2c->IICSTAT & I2CSTAT_NACK));
|
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}
|
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|
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static void ReadWriteByte (void)
|
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{
|
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S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
|
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|
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i2c->IICCON &= ~I2CCON_IRPND;
|
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}
|
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|
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void i2c_init (int speed, int slaveadd)
|
||||
{
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S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
|
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S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO ();
|
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ulong freq, pres = 16, div;
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int i, status;
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|
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/* wait for some time to give previous transfer a chance to finish */
|
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|
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i = I2C_TIMEOUT * 1000;
|
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status = i2c->IICSTAT;
|
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while ((i > 0) && (status & I2CSTAT_BSY)) {
|
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udelay (1000);
|
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status = i2c->IICSTAT;
|
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i--;
|
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}
|
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|
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if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
|
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#ifdef CONFIG_S3C2410
|
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ulong old_gpecon = gpio->GPECON;
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#endif
|
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#ifdef CONFIG_S3C2400
|
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ulong old_gpecon = gpio->PGCON;
|
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#endif
|
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/* bus still busy probably by (most) previously interrupted transfer */
|
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|
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#ifdef CONFIG_S3C2410
|
||||
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
|
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gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C2400
|
||||
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
|
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gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00000c00;
|
||||
#endif
|
||||
|
||||
/* toggle I2CSCL until bus idle */
|
||||
SetI2CSCL (0);
|
||||
udelay (1000);
|
||||
i = 10;
|
||||
while ((i > 0) && (GetI2CSDA () != 1)) {
|
||||
SetI2CSCL (1);
|
||||
udelay (1000);
|
||||
SetI2CSCL (0);
|
||||
udelay (1000);
|
||||
i--;
|
||||
}
|
||||
SetI2CSCL (1);
|
||||
udelay (1000);
|
||||
|
||||
/* restore pin functions */
|
||||
#ifdef CONFIG_S3C2410
|
||||
gpio->GPECON = old_gpecon;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C2400
|
||||
gpio->PGCON = old_gpecon;
|
||||
#endif
|
||||
}
|
||||
|
||||
/* calculate prescaler and divisor values */
|
||||
freq = get_PCLK ();
|
||||
if ((freq / pres / (16 + 1)) > speed)
|
||||
/* set prescaler to 512 */
|
||||
pres = 512;
|
||||
|
||||
div = 0;
|
||||
while ((freq / pres / (div + 1)) > speed)
|
||||
div++;
|
||||
|
||||
/* set prescaler, divisor according to freq, also set
|
||||
* ACKGEN, IRQ */
|
||||
i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
|
||||
|
||||
/* init to SLAVE REVEIVE and set slaveaddr */
|
||||
i2c->IICSTAT = 0;
|
||||
i2c->IICADD = slaveadd;
|
||||
/* program Master Transmit (and implicit STOP) */
|
||||
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
* cmd_type is 0 for write, 1 for read.
|
||||
*
|
||||
* addr_len can take any value from 0-255, it is only limited
|
||||
* by the char, we could make it larger if needed. If it is
|
||||
* 0 we skip the address write cycle.
|
||||
*/
|
||||
static
|
||||
int i2c_transfer (unsigned char cmd_type,
|
||||
unsigned char chip,
|
||||
unsigned char addr[],
|
||||
unsigned char addr_len,
|
||||
unsigned char data[], unsigned short data_len)
|
||||
{
|
||||
S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
|
||||
int i, status, result;
|
||||
|
||||
if (data == 0 || data_len == 0) {
|
||||
/*Don't support data transfer of no length or to address 0 */
|
||||
printf ("i2c_transfer: bad call\n");
|
||||
return I2C_NOK;
|
||||
}
|
||||
|
||||
/* Check I2C bus idle */
|
||||
i = I2C_TIMEOUT * 1000;
|
||||
status = i2c->IICSTAT;
|
||||
while ((i > 0) && (status & I2CSTAT_BSY)) {
|
||||
udelay (1000);
|
||||
status = i2c->IICSTAT;
|
||||
i--;
|
||||
}
|
||||
|
||||
if (status & I2CSTAT_BSY)
|
||||
return I2C_NOK_TOUT;
|
||||
|
||||
i2c->IICCON |= 0x80;
|
||||
result = I2C_OK;
|
||||
|
||||
switch (cmd_type) {
|
||||
case I2C_WRITE:
|
||||
if (addr && addr_len) {
|
||||
i2c->IICDS = chip;
|
||||
/* send START */
|
||||
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
|
||||
i = 0;
|
||||
while ((i < addr_len) && (result == I2C_OK)) {
|
||||
result = WaitForXfer ();
|
||||
i2c->IICDS = addr[i];
|
||||
ReadWriteByte ();
|
||||
i++;
|
||||
}
|
||||
i = 0;
|
||||
while ((i < data_len) && (result == I2C_OK)) {
|
||||
result = WaitForXfer ();
|
||||
i2c->IICDS = data[i];
|
||||
ReadWriteByte ();
|
||||
i++;
|
||||
}
|
||||
} else {
|
||||
i2c->IICDS = chip;
|
||||
/* send START */
|
||||
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
|
||||
i = 0;
|
||||
while ((i < data_len) && (result = I2C_OK)) {
|
||||
result = WaitForXfer ();
|
||||
i2c->IICDS = data[i];
|
||||
ReadWriteByte ();
|
||||
i++;
|
||||
}
|
||||
}
|
||||
|
||||
if (result == I2C_OK)
|
||||
result = WaitForXfer ();
|
||||
|
||||
/* send STOP */
|
||||
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||
ReadWriteByte ();
|
||||
break;
|
||||
|
||||
case I2C_READ:
|
||||
if (addr && addr_len) {
|
||||
i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
|
||||
i2c->IICDS = chip;
|
||||
/* send START */
|
||||
i2c->IICSTAT |= I2C_START_STOP;
|
||||
result = WaitForXfer ();
|
||||
if (IsACK ()) {
|
||||
i = 0;
|
||||
while ((i < addr_len) && (result == I2C_OK)) {
|
||||
i2c->IICDS = addr[i];
|
||||
ReadWriteByte ();
|
||||
result = WaitForXfer ();
|
||||
i++;
|
||||
}
|
||||
|
||||
i2c->IICDS = chip;
|
||||
/* resend START */
|
||||
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA |
|
||||
I2C_START_STOP;
|
||||
ReadWriteByte ();
|
||||
result = WaitForXfer ();
|
||||
i = 0;
|
||||
while ((i < data_len) && (result == I2C_OK)) {
|
||||
/* disable ACK for final READ */
|
||||
if (i == data_len - 1)
|
||||
i2c->IICCON &= ~0x80;
|
||||
ReadWriteByte ();
|
||||
result = WaitForXfer ();
|
||||
data[i] = i2c->IICDS;
|
||||
i++;
|
||||
}
|
||||
} else {
|
||||
result = I2C_NACK;
|
||||
}
|
||||
|
||||
} else {
|
||||
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||
i2c->IICDS = chip;
|
||||
/* send START */
|
||||
i2c->IICSTAT |= I2C_START_STOP;
|
||||
result = WaitForXfer ();
|
||||
|
||||
if (IsACK ()) {
|
||||
i = 0;
|
||||
while ((i < data_len) && (result == I2C_OK)) {
|
||||
/* disable ACK for final READ */
|
||||
if (i == data_len - 1)
|
||||
i2c->IICCON &= ~0x80;
|
||||
ReadWriteByte ();
|
||||
result = WaitForXfer ();
|
||||
data[i] = i2c->IICDS;
|
||||
i++;
|
||||
}
|
||||
} else {
|
||||
result = I2C_NACK;
|
||||
}
|
||||
}
|
||||
|
||||
/* send STOP */
|
||||
i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
|
||||
ReadWriteByte ();
|
||||
break;
|
||||
|
||||
default:
|
||||
printf ("i2c_transfer: bad call\n");
|
||||
result = I2C_NOK;
|
||||
break;
|
||||
}
|
||||
|
||||
return (result);
|
||||
}
|
||||
|
||||
int i2c_probe (uchar chip)
|
||||
{
|
||||
uchar buf[1];
|
||||
|
||||
buf[0] = 0;
|
||||
|
||||
/*
|
||||
* What is needed is to send the chip address and verify that the
|
||||
* address was <ACK>ed (i.e. there was a chip at that address which
|
||||
* drove the data line low).
|
||||
*/
|
||||
return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
|
||||
}
|
||||
|
||||
int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
int ret;
|
||||
|
||||
if (alen > 4) {
|
||||
printf ("I2C read: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if (alen > 0)
|
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
if ((ret =
|
||||
i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
|
||||
buffer, len)) != 0) {
|
||||
printf ("I2c read: failed %d\n", ret);
|
||||
return 1;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
|
||||
{
|
||||
uchar xaddr[4];
|
||||
|
||||
if (alen > 4) {
|
||||
printf ("I2C write: addr len %d not supported\n", alen);
|
||||
return 1;
|
||||
}
|
||||
|
||||
if (alen > 0) {
|
||||
xaddr[0] = (addr >> 24) & 0xFF;
|
||||
xaddr[1] = (addr >> 16) & 0xFF;
|
||||
xaddr[2] = (addr >> 8) & 0xFF;
|
||||
xaddr[3] = addr & 0xFF;
|
||||
}
|
||||
#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
|
||||
/*
|
||||
* EEPROM chips that implement "address overflow" are ones
|
||||
* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
|
||||
* address and the extra bits end up in the "chip address"
|
||||
* bit slots. This makes a 24WC08 (1Kbyte) chip look like
|
||||
* four 256 byte chips.
|
||||
*
|
||||
* Note that we consider the length of the address field to
|
||||
* still be one byte because the extra address bits are
|
||||
* hidden in the chip address.
|
||||
*/
|
||||
if (alen > 0)
|
||||
chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
|
||||
#endif
|
||||
return (i2c_transfer
|
||||
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
|
||||
len) != 0);
|
||||
}
|
||||
#endif /* CONFIG_HARD_I2C */
|
||||
|
||||
#endif /* CONFIG_DRIVER_S3C24X0_I2C */
|
||||
Reference in New Issue
Block a user