Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
This commit is contained in:
Wolfgang Denk
commit
1d96cfe8f5
3
MAKEALL
3
MAKEALL
@ -387,6 +387,9 @@ LIST_83xx=" \
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||||
LIST_85xx=" \
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ATUM8548 \
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MPC8536DS \
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MPC8536DS_NAND \
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MPC8536DS_SDCARD \
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MPC8536DS_SPIFLASH \
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MPC8540ADS \
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MPC8540EVAL \
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MPC8541CDS \
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3
Makefile
3
Makefile
@ -2433,6 +2433,9 @@ vme8349_config: unconfig
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ATUM8548_config: unconfig
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@$(MKCONFIG) $(@:_config=) ppc mpc85xx atum8548
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MPC8536DS_NAND_config \
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MPC8536DS_SDCARD_config \
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MPC8536DS_SPIFLASH_config \
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MPC8536DS_36BIT_config \
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MPC8536DS_config: unconfig
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@$(MKCONFIG) -t $(@:_config=) MPC8536DS ppc mpc85xx mpc8536ds freescale
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@ -23,8 +23,27 @@
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#
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# mpc8536ds board
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#
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ifndef NAND_SPL
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ifeq ($(CONFIG_MK_NAND), y)
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TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
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LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
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endif
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endif
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ifeq ($(CONFIG_MK_SDCARD), y)
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TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
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RESET_VECTOR_ADDRESS = 0xf8fffffc
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endif
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ifeq ($(CONFIG_MK_SPIFLASH), y)
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TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
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RESET_VECTOR_ADDRESS = 0xf8fffffc
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endif
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ifndef TEXT_BASE
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TEXT_BASE = 0xeff80000
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endif
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ifndef RESET_VECTOR_ADDRESS
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RESET_VECTOR_ADDRESS = 0xeffffffc
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endif
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@ -71,6 +71,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
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SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 4, BOOKE_PAGESZ_1M, 1),
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#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
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/* *I*G - L2SRAM */
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 5, BOOKE_PAGESZ_256K, 1),
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SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
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CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, 6, BOOKE_PAGESZ_256K, 1),
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#endif
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};
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int num_tlb_entries = ARRAY_SIZE(tlb_table);
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@ -24,5 +24,5 @@
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# sbc8548 board
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#
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ifndef TEXT_BASE
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TEXT_BASE = 0xfff80000
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TEXT_BASE = 0xfffa0000
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endif
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127
doc/README.mpc8536ds
Normal file
127
doc/README.mpc8536ds
Normal file
@ -0,0 +1,127 @@
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Overview:
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=========
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The MPC8536E integrates a PowerPC processor core with system logic
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required for imaging, networking, and communications applications.
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Boot from NAND:
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===============
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The MPC8536E is capable of booting from NAND flash which uses the image
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u-boot-nand.bin. This image contains two parts: a first stage image(also
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call 4K NAND loader and a second stage image. The former is appended to
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the latter to produce u-boot-nand.bin.
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The bootup process can be divided into two stages: the first stage will
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configure the L2SRAM, then copy the second stage image to L2SRAM and jump
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to it. The second stage image is to configure all the hardware and boot up
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to U-Boot command line.
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The 4K NAND loader's code comes from the corresponding nand_spl directory,
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along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
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is mainly used to shrink the code size to the 4K size limitation.
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The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
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second stage image. It's set in the board config file when boot from NAND
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is selected.
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Build and boot steps
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--------------------
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1. Building image
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make MPC8536DS_NAND_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 1011
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SW9[1-3] = 101
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Note: 1 stands for 'on', 0 stands for 'off'
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3. Flash image
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tftp 1000000 u-boot-nand.bin
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nand erase 0 a0000
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nand write 1000000 0 a0000
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Boot from On-chip ROM:
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======================
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The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
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and boot from eSPI. When power on, the porcessor excutes the ROM code to
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initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
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the memory device that interfaced to the controller, such as the SDCard or
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SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
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The memory device should contain a specific data structure with control word
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and config word at the fixed address. The config word direct the process how
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to config the memory device, and the control word direct the processor where
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to find the image on the memory device, or where copy the main image to. The
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user can use any method to store the data structure to the memory device, only
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if store it on the assigned address.
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Build and boot steps
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--------------------
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For boot from eSDHC:
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1. Build image
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make MPC8536DS_SDCARD_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 0111
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SW3[1] = 0
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SW8[7] = 0 - The on-board SD/MMC slot is active
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SW8[7] = 1 - The externel SD/MMC slot is active
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3. Put image to SDCard
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Put the follwing info at the assigned address on the SDCard:
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Offset | Data | Description
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--------------------------------------------------------
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| 0x40-0x43 | 0x424F4F54 | BOOT signature |
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--------------------------------------------------------
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| 0x48-0x4B | 0x00080000 | u-boot.bin's size |
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--------------------------------------------------------
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| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
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--------------------------------------------------------
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| 0x58-0x5B | 0xF8F80000 | Target Address |
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-------------------------------------------------------
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| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
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--------------------------------------------------------
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| 0x68-0x6B | 0x6 | Number of Config Addr/Data |
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--------------------------------------------------------
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| 0x80-0x83 | 0xFF720100 | Config Addr 1 |
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| 0x84-0x87 | 0xF8F80000 | Config Data 1 |
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--------------------------------------------------------
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| 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
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| 0x8c-0x8f | 0x0000000C | Config Data 2 |
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--------------------------------------------------------
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| 0x90-0x93 | 0xFF720000 | Config Addr 3 |
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| 0x94-0x97 | 0x80010000 | Config Data 3 |
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--------------------------------------------------------
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| 0x98-0x9b | 0xFF72e40e | Config Addr 4 |
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| 0x9c-0x9f | 0x00000040 | Config Data 4 |
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--------------------------------------------------------
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| 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
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| 0xa4-0xa7 | 0x00000100 | Config Data 5 |
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--------------------------------------------------------
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| 0xa8-0xab | 0x80000001 | Config Addr 6 |
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| 0xac-0xaf | 0x80000001 | Config Data 6 |
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--------------------------------------------------------
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| ...... |
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--------------------------------------------------------
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| 0x???????? | u-boot.bin |
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--------------------------------------------------------
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then insert the SDCard to the active slot to boot up.
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For boot from eSPI:
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1. Build image
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make MPC8536DS_SPIFLASH_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 0110
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3. Put image to SPI flash
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Put the info in the above table onto the SPI flash, then
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boot up.
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@ -63,6 +63,30 @@ a 33MHz PCI configuration is currently untested.)
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=>
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Updating U-boot with U-boot:
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============================
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Note that versions of u-boot up to and including 2009.08 had u-boot stored
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at 0xfff8_0000 -> 0xffff_ffff (512k). Currently it is being stored from
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0xfffa_0000 -> 0xffff_ffff (384k). If you use an old macro/script to
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update u-boot with u-boot and it uses the old address, you will render
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your board inoperable, and you will require JTAG recovery.
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The following steps list how to update with the current address:
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tftp u-boot.bin
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md 200000 10
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protect off all
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erase fffa0000 ffffffff
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cp.b 200000 fffa0000 60000
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md fffa0000 10
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protect on all
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The "md" steps in the above are just a precautionary step that allow
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you to confirm the u-boot version that was downloaded, and then confirm
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that it was copied to flash.
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Hardware Reference:
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===================
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@ -79,6 +79,7 @@ void disable_law(u8 idx)
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return;
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}
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#ifndef CONFIG_NAND_SPL
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static int get_law_entry(u8 i, struct law_entry *e)
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{
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volatile ccsr_local_t *ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
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@ -96,6 +97,7 @@ static int get_law_entry(u8 i, struct law_entry *e)
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return 1;
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}
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#endif
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#else
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void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
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{
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@ -130,6 +132,7 @@ void disable_law(u8 idx)
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return;
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}
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#ifndef CONFIG_NAND_SPL
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static int get_law_entry(u8 i, struct law_entry *e)
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{
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volatile u32 *base = (volatile u32 *)(CONFIG_SYS_IMMR + 0xc08);
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@ -149,6 +152,7 @@ static int get_law_entry(u8 i, struct law_entry *e)
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return 1;
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}
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#endif
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#endif
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int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
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{
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File diff suppressed because it is too large
Load Diff
@ -31,6 +31,22 @@
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#define CONFIG_PHYS_64BIT 1
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#endif
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#ifdef CONFIG_MK_NAND
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#define CONFIG_NAND_U_BOOT 1
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#define CONFIG_RAMBOOT_NAND 1
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#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f82000
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#endif
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#ifdef CONFIG_MK_SDCARD
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#define CONFIG_RAMBOOT_SDCARD 1
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#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
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#endif
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#ifdef CONFIG_MK_SPIFLASH
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#define CONFIG_RAMBOOT_SPIFLASH 1
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#define CONFIG_RAMBOOT_TEXT_BASE 0xf8f80000
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#endif
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/* High Level Configuration Options */
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#define CONFIG_BOOKE 1 /* BOOKE */
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#define CONFIG_E500 1 /* BOOKE e500 family */
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@ -86,27 +102,44 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
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#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
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#endif
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#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
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#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
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#define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */
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#define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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/*
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* Config the L2 Cache as L2 SRAM
|
||||
*/
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||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
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||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
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#else
|
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#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#endif
|
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#define CONFIG_SYS_L2_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
|
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#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
|
||||
#endif
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
|
||||
|
||||
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
|
||||
#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
|
||||
#else
|
||||
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR + 0x8000)
|
||||
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR + 0xa000)
|
||||
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR + 0x9000)
|
||||
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR + 0xb000)
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
@ -131,9 +164,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
|
||||
/* These are used when DDR doesn't use SPD. */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
|
||||
@ -145,7 +178,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
|
||||
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
|
||||
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x04400010
|
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
|
||||
@ -190,24 +223,36 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR0_PRELIM 0xf8000ff7
|
||||
#define CONFIG_FLASH_BR_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_BR1_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
|
||||
CONFIG_SYS_FLASH_BASE_PHYS }
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
|
||||
|
||||
#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
|
||||
|| defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
@ -224,7 +269,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
|
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */
|
||||
@ -260,6 +305,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
|
||||
#define PIXIS_LED 0x25 /* LED Register */
|
||||
|
||||
#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
|
||||
|
||||
/* old pixis referenced names */
|
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
|
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
|
||||
@ -270,18 +317,28 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xfff00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
|
||||
CONFIG_SYS_NAND_BASE + 0x40000, \
|
||||
CONFIG_SYS_NAND_BASE + 0x80000, \
|
||||
@ -292,43 +349,66 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
/* NAND boot: 4K NAND loader config */
|
||||
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START \
|
||||
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
#define CONFIG_NAND_BR_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#ifdef CONFIG_RAMBOOT_NAND
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#else
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR4_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR6_PRELIM \
|
||||
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
@ -344,8 +424,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
|
||||
|
||||
/* Use the HUSH parser */
|
||||
#define CONFIG_SYS_HUSH_PARSER
|
||||
@ -360,8 +440,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_OF_BOARD_SETUP 1
|
||||
#define CONFIG_OF_STDOUT_VIA_ALIAS 1
|
||||
|
||||
#define CONFIG_SYS_64BIT_STRTOUL 1
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1
|
||||
#define CONFIG_SYS_64BIT_STRTOUL 1
|
||||
#define CONFIG_SYS_64BIT_VSPRINTF 1
|
||||
|
||||
|
||||
/*
|
||||
@ -526,15 +606,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_CMD_EXT2
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_CMD_USB
|
||||
#define CONFIG_USB_STORAGE
|
||||
#define CONFIG_USB_EHCI
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#ifndef CONFIG_NET_MULTI
|
||||
@ -569,14 +640,27 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_NAND)
|
||||
#define CONFIG_ENV_IS_IN_NAND 1
|
||||
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
|
||||
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
|
||||
#define CONFIG_ENV_ADDR 0xfff80000
|
||||
#else
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
#endif
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
@ -617,7 +701,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LONGHELP /* undef to save memory */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_CMDLINE_EDITING /* Command-line editing */
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
@ -625,9 +709,10 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
|
||||
+ sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
|
||||
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
|
||||
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
|
||||
|
||||
/*
|
||||
@ -635,7 +720,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
* have to be in the first 16 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
|
||||
|
||||
/*
|
||||
* Internal Definitions
|
||||
@ -671,7 +756,7 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy);
|
||||
#define CONFIG_HOSTNAME unknown
|
||||
#define CONFIG_ROOTPATH /opt/nfsroot
|
||||
#define CONFIG_BOOTFILE uImage
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
|
||||
@ -330,7 +330,14 @@
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
/*
|
||||
* For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
|
||||
* one for env+bootpg (TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
|
||||
* flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
|
||||
* (TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
|
||||
* thing for MONITOR_LEN in both cases.
|
||||
*/
|
||||
#define CONFIG_SYS_MONITOR_LEN (~TEXT_BASE + 1)
|
||||
#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
|
||||
|
||||
/* Serial Port */
|
||||
@ -448,9 +455,16 @@
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
|
||||
#define CONFIG_ENV_SIZE 0x2000
|
||||
#if TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
|
||||
#elif TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
|
||||
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
|
||||
#else
|
||||
#warning undefined environment size/location.
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
127
nand_spl/board/freescale/mpc8536ds/Makefile
Normal file
127
nand_spl/board/freescale/mpc8536ds/Makefile
Normal file
@ -0,0 +1,127 @@
|
||||
#
|
||||
# (C) Copyright 2007
|
||||
# Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
#
|
||||
# Copyright 2009 Freescale Semiconductor, Inc.
|
||||
#
|
||||
# See file CREDITS for list of people who contributed to this
|
||||
# project.
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or
|
||||
# modify it under the terms of the GNU General Public License as
|
||||
# published by the Free Software Foundation; either version 2 of
|
||||
# the License, or (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
# MA 02111-1307 USA
|
||||
#
|
||||
|
||||
NAND_SPL := y
|
||||
TEXT_BASE := 0xfff00000
|
||||
PAD_TO := 0xfff01000
|
||||
|
||||
include $(TOPDIR)/config.mk
|
||||
|
||||
LDSCRIPT= $(TOPDIR)/cpu/$(CPU)/u-boot-nand_spl.lds
|
||||
LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
|
||||
AFLAGS += -DCONFIG_NAND_SPL
|
||||
CFLAGS += -DCONFIG_NAND_SPL
|
||||
|
||||
SOBJS = start.o resetvec.o
|
||||
COBJS = cache.o cpu_init_early.o cpu_init_nand.o fsl_law.o law.o \
|
||||
nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
|
||||
|
||||
SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c))
|
||||
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
|
||||
__OBJS := $(SOBJS) $(COBJS)
|
||||
LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
|
||||
|
||||
nandobj := $(OBJTREE)/nand_spl/
|
||||
|
||||
ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
|
||||
|
||||
all: $(obj).depend $(ALL)
|
||||
|
||||
$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
|
||||
$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
|
||||
|
||||
$(nandobj)u-boot-spl: $(OBJS)
|
||||
cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
|
||||
-Map $(nandobj)u-boot-spl.map \
|
||||
-o $(nandobj)u-boot-spl
|
||||
|
||||
# create symbolic links for common files
|
||||
|
||||
$(obj)cache.c:
|
||||
@rm -f $(obj)cache.c
|
||||
ln -sf $(SRCTREE)/lib_ppc/cache.c $(obj)cache.c
|
||||
|
||||
$(obj)cpu_init_early.c:
|
||||
@rm -f $(obj)cpu_init_early.c
|
||||
ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_early.c $(obj)cpu_init_early.c
|
||||
|
||||
$(obj)cpu_init_nand.c:
|
||||
@rm -f $(obj)cpu_init_nand.c
|
||||
ln -sf $(SRCTREE)/cpu/mpc85xx/cpu_init_nand.c $(obj)cpu_init_nand.c
|
||||
|
||||
$(obj)fsl_law.c:
|
||||
@rm -f $(obj)fsl_law.c
|
||||
ln -sf $(SRCTREE)/drivers/misc/fsl_law.c $(obj)fsl_law.c
|
||||
|
||||
$(obj)law.c:
|
||||
@rm -f $(obj)law.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/law.c $(obj)law.c
|
||||
|
||||
$(obj)nand_boot_fsl_elbc.c:
|
||||
@rm -f $(obj)nand_boot_fsl_elbc.c
|
||||
ln -sf $(SRCTREE)/nand_spl/nand_boot_fsl_elbc.c \
|
||||
$(obj)nand_boot_fsl_elbc.c
|
||||
|
||||
$(obj)ns16550.c:
|
||||
@rm -f $(obj)ns16550.c
|
||||
ln -sf $(SRCTREE)/drivers/serial/ns16550.c $(obj)ns16550.c
|
||||
|
||||
$(obj)resetvec.S:
|
||||
@rm -f $(obj)resetvec.S
|
||||
ln -s $(SRCTREE)/cpu/$(CPU)/resetvec.S $(obj)resetvec.S
|
||||
|
||||
$(obj)fixed_ivor.S:
|
||||
@rm -f $(obj)fixed_ivor.S
|
||||
ln -sf $(SRCTREE)/cpu/mpc85xx/fixed_ivor.S $(obj)fixed_ivor.S
|
||||
|
||||
$(obj)start.S: $(obj)fixed_ivor.S
|
||||
@rm -f $(obj)start.S
|
||||
ln -sf $(SRCTREE)/cpu/mpc85xx/start.S $(obj)start.S
|
||||
|
||||
$(obj)tlb.c:
|
||||
@rm -f $(obj)tlb.c
|
||||
ln -sf $(SRCTREE)/cpu/mpc85xx/tlb.c $(obj)tlb.c
|
||||
|
||||
$(obj)tlb_table.c:
|
||||
@rm -f $(obj)tlb_table.c
|
||||
ln -sf $(SRCTREE)/board/$(BOARDDIR)/tlb.c $(obj)tlb_table.c
|
||||
|
||||
#########################################################################
|
||||
|
||||
$(obj)%.o: $(obj)%.S
|
||||
$(CC) $(AFLAGS) -c -o $@ $<
|
||||
|
||||
$(obj)%.o: $(obj)%.c
|
||||
$(CC) $(CFLAGS) -c -o $@ $<
|
||||
|
||||
# defines $(obj).depend target
|
||||
include $(SRCTREE)/rules.mk
|
||||
|
||||
sinclude $(obj).depend
|
||||
|
||||
#########################################################################
|
||||
83
nand_spl/board/freescale/mpc8536ds/nand_boot.c
Normal file
83
nand_spl/board/freescale/mpc8536ds/nand_boot.c
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
*
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
|
||||
u32 sysclk_tbl[] = {
|
||||
33333000, 39999600, 49999500, 66666000,
|
||||
83332500, 99999000, 133332000, 166665000
|
||||
};
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
int px_spd;
|
||||
u32 plat_ratio, bus_clk, sys_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
|
||||
/* for FPGA */
|
||||
out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
|
||||
out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
|
||||
#else
|
||||
#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
|
||||
sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK];
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
bus_clk = sys_clk * plat_ratio / 2;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
|
||||
CONFIG_SYS_NAND_U_BOOT_RELOC);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user