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global: Migrate CONFIG_MAX_MEM_MAPPED to CFG

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Perform a simple rename of CONFIG_MAX_MEM_MAPPED to CFG_MAX_MEM_MAPPED

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-12-04 10:04:50 -05:00
parent dd5b58c491
commit 1d457dbb91
17 changed files with 50 additions and 50 deletions
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6
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -1308,13 +1308,13 @@ phys_size_t get_effective_memsize(void)
* allocated from first region. If the memory extends to the second * allocated from first region. If the memory extends to the second
* region (or the third region if applicable), Management Complex (MC) * region (or the third region if applicable), Management Complex (MC)
* memory should be put into the highest region, i.e. the end of DDR * memory should be put into the highest region, i.e. the end of DDR
* memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so * memory. CFG_MAX_MEM_MAPPED is set to the size of first region so
* U-Boot doesn't relocate itself into higher address. Should DDR be * U-Boot doesn't relocate itself into higher address. Should DDR be
* configured to skip the first region, this function needs to be * configured to skip the first region, this function needs to be
* adjusted. * adjusted.
*/ */
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
ea_size = CONFIG_MAX_MEM_MAPPED; ea_size = CFG_MAX_MEM_MAPPED;
rem = gd->ram_size - ea_size; rem = gd->ram_size - ea_size;
} else { } else {
ea_size = gd->ram_size; ea_size = gd->ram_size;

14
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -36,7 +36,7 @@
/* DDR */ /* DDR */
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000 #define GICD_BASE 0x06000000
@ -121,7 +121,7 @@
/* DDR */ /* DDR */
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ /* DCFG - GUR */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
@ -147,7 +147,7 @@
/* DDR */ /* DDR */
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* Generic Interrupt Controller Definitions */ /* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000 #define GICD_BASE 0x06000000
@ -191,7 +191,7 @@
/* DDR */ /* DDR */
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SEC */ /* SEC */
@ -211,7 +211,7 @@
#define CFG_SYS_NUM_FM1_DTSEC 7 #define CFG_SYS_NUM_FM1_DTSEC 7
#define CFG_SYS_NUM_FM1_10GEC 1 #define CFG_SYS_NUM_FM1_10GEC 1
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#define QE_MURAM_SIZE 0x6000UL #define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1 #define MAX_QE_RISC 1
@ -250,14 +250,14 @@
#define GICD_BASE 0x01401000 #define GICD_BASE 0x01401000
#define GICC_BASE 0x01402000 #define GICC_BASE 0x01402000
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
#elif defined(CONFIG_ARCH_LS1046A) #elif defined(CONFIG_ARCH_LS1046A)
#define CFG_SYS_NUM_FMAN 1 #define CFG_SYS_NUM_FMAN 1
#define CFG_SYS_NUM_FM1_DTSEC 8 #define CFG_SYS_NUM_FM1_DTSEC 8
#define CFG_SYS_NUM_FM1_10GEC 2 #define CFG_SYS_NUM_FM1_10GEC 2
#define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CFG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
#define CONFIG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE #define CFG_MAX_MEM_MAPPED CFG_SYS_DDR_BLOCK1_SIZE
/* SMMU Defintions */ /* SMMU Defintions */
#define SMMU_BASE 0x09000000 #define SMMU_BASE 0x09000000

2
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -70,7 +70,7 @@
/* SATA */ /* SATA */
#define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000) #define AHCI_BASE_ADDR (CONFIG_SYS_IMMR + 0x02200000)
#ifdef CONFIG_DDR_SPD #ifdef CONFIG_DDR_SPD
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#endif #endif
#define DCU_LAYER_MAX_NUM 16 #define DCU_LAYER_MAX_NUM 16

14
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -616,12 +616,12 @@ static int reset_tlb(phys_addr_t p_addr, u32 size, phys_addr_t *phys_offset)
/* /*
* slide the testing window up to test another area * slide the testing window up to test another area
* for 32_bit system, the maximum testable memory is limited to * for 32_bit system, the maximum testable memory is limited to
* CONFIG_MAX_MEM_MAPPED * CFG_MAX_MEM_MAPPED
*/ */
int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset) int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{ {
phys_addr_t test_cap, p_addr; phys_addr_t test_cap, p_addr;
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
#if !defined(CONFIG_PHYS_64BIT) || \ #if !defined(CONFIG_PHYS_64BIT) || \
!defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
@ -632,7 +632,7 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
#endif #endif
p_addr = (*vstart) + (*size) + (*phys_offset); p_addr = (*vstart) + (*size) + (*phys_offset);
if (p_addr < test_cap - 1) { if (p_addr < test_cap - 1) {
p_size = min(test_cap - p_addr, CONFIG_MAX_MEM_MAPPED); p_size = min(test_cap - p_addr, CFG_MAX_MEM_MAPPED);
if (reset_tlb(p_addr, p_size, phys_offset) == -1) if (reset_tlb(p_addr, p_size, phys_offset) == -1)
return -1; return -1;
*vstart = CFG_SYS_DDR_SDRAM_BASE; *vstart = CFG_SYS_DDR_SDRAM_BASE;
@ -649,18 +649,18 @@ int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
/* initialization for testing area */ /* initialization for testing area */
int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{ {
phys_size_t p_size = min(gd->ram_size, CONFIG_MAX_MEM_MAPPED); phys_size_t p_size = min(gd->ram_size, CFG_MAX_MEM_MAPPED);
*vstart = CFG_SYS_DDR_SDRAM_BASE; *vstart = CFG_SYS_DDR_SDRAM_BASE;
*size = (u32) p_size; /* CONFIG_MAX_MEM_MAPPED < 4G */ *size = (u32) p_size; /* CFG_MAX_MEM_MAPPED < 4G */
*phys_offset = 0; *phys_offset = 0;
#if !defined(CONFIG_PHYS_64BIT) || \ #if !defined(CONFIG_PHYS_64BIT) || \
!defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \ !defined(CFG_SYS_INIT_RAM_ADDR_PHYS) || \
(CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull) (CFG_SYS_INIT_RAM_ADDR_PHYS < 0x100000000ull)
if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) { if (gd->ram_size > CFG_MAX_MEM_MAPPED) {
puts("Cannot test more than "); puts("Cannot test more than ");
print_size(CONFIG_MAX_MEM_MAPPED, print_size(CFG_MAX_MEM_MAPPED,
" without proper 36BIT support.\n"); " without proper 36BIT support.\n");
} }
#endif #endif

4
arch/powerpc/cpu/mpc85xx/mp.c
View File

@ -193,8 +193,8 @@ u32 determine_mp_bootpg(unsigned int *pagesize)
/* use last 4K of mapped memory */ /* use last 4K of mapped memory */
bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? bootpg = ((gd->ram_size > CFG_MAX_MEM_MAPPED) ?
CONFIG_MAX_MEM_MAPPED : gd->ram_size) + CFG_MAX_MEM_MAPPED : gd->ram_size) +
CFG_SYS_SDRAM_BASE - 4096; CFG_SYS_SDRAM_BASE - 4096;
if (pagesize) if (pagesize)
*pagesize = 4096; *pagesize = 4096;

8
arch/powerpc/cpu/mpc85xx/tlb.c
View File

@ -306,12 +306,12 @@ unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
u64 memsize = (u64)memsize_in_meg << 20; u64 memsize = (u64)memsize_in_meg << 20;
u64 size; u64 size;
size = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED); size = min(memsize, (u64)CFG_MAX_MEM_MAPPED);
size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM); size = tlb_map_range(ram_tlb_address, p_addr, size, TLB_MAP_RAM);
if (size || memsize > CONFIG_MAX_MEM_MAPPED) { if (size || memsize > CFG_MAX_MEM_MAPPED) {
print_size(memsize > CONFIG_MAX_MEM_MAPPED ? print_size(memsize > CFG_MAX_MEM_MAPPED ?
memsize - CONFIG_MAX_MEM_MAPPED + size : size, memsize - CFG_MAX_MEM_MAPPED + size : size,
" of DDR memory left unmapped in U-Boot\n"); " of DDR memory left unmapped in U-Boot\n");
#ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SPL_BUILD
puts(" "); puts(" ");

2
arch/powerpc/cpu/mpc8xxx/pamu_table.c
View File

@ -17,7 +17,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries)
tbl->start_addr[i] = tbl->start_addr[i] =
(uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE);
tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); tbl->size[i] = (phys_size_t)(min(gd->ram_size, CFG_MAX_MEM_MAPPED));
tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1;
i++; i++;

6
arch/powerpc/include/asm/config.h
View File

@ -14,13 +14,13 @@
#define HWCONFIG_BUFFER_SIZE 256 #define HWCONFIG_BUFFER_SIZE 256
#endif #endif
#ifndef CONFIG_MAX_MEM_MAPPED #ifndef CFG_MAX_MEM_MAPPED
#if defined(CONFIG_E500) || \ #if defined(CONFIG_E500) || \
defined(CONFIG_MPC86xx) || \ defined(CONFIG_MPC86xx) || \
defined(CONFIG_E300) defined(CONFIG_E300)
#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) #define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
#else #else
#define CONFIG_MAX_MEM_MAPPED (256 << 20) #define CFG_MAX_MEM_MAPPED (256 << 20)
#endif #endif
#endif #endif

2
arch/xtensa/include/asm/config.h
View File

@ -14,7 +14,7 @@
* restricting used physical memory to the first 128MB. * restricting used physical memory to the first 128MB.
*/ */
#if XCHAL_HAVE_PTP_MMU #if XCHAL_HAVE_PTP_MMU
#define CONFIG_MAX_MEM_MAPPED (128 << 20) #define CFG_MAX_MEM_MAPPED (128 << 20)
#endif #endif
#endif #endif

14
board/ti/dra7xx/evm.c
View File

@ -277,13 +277,13 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
case DRA752_ES2_0: case DRA752_ES2_0:
switch (emif_nr) { switch (emif_nr) {
case 1: case 1:
if (ram_size > CONFIG_MAX_MEM_MAPPED) if (ram_size > CFG_MAX_MEM_MAPPED)
*regs = &emif1_ddr3_532_mhz_1cs_2G; *regs = &emif1_ddr3_532_mhz_1cs_2G;
else else
*regs = &emif1_ddr3_532_mhz_1cs; *regs = &emif1_ddr3_532_mhz_1cs;
break; break;
case 2: case 2:
if (ram_size > CONFIG_MAX_MEM_MAPPED) if (ram_size > CFG_MAX_MEM_MAPPED)
*regs = &emif2_ddr3_532_mhz_1cs_2G; *regs = &emif2_ddr3_532_mhz_1cs_2G;
else else
*regs = &emif2_ddr3_532_mhz_1cs; *regs = &emif2_ddr3_532_mhz_1cs;
@ -301,7 +301,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
case DRA722_ES1_0: case DRA722_ES1_0:
case DRA722_ES2_0: case DRA722_ES2_0:
case DRA722_ES2_1: case DRA722_ES2_1:
if (ram_size < CONFIG_MAX_MEM_MAPPED) if (ram_size < CFG_MAX_MEM_MAPPED)
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1; *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
else else
*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2; *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es2;
@ -360,7 +360,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
case DRA752_ES1_0: case DRA752_ES1_0:
case DRA752_ES1_1: case DRA752_ES1_1:
case DRA752_ES2_0: case DRA752_ES2_0:
if (ram_size > CONFIG_MAX_MEM_MAPPED) if (ram_size > CFG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_dra7_2GB; *dmm_lisa_regs = &lisa_map_dra7_2GB;
else else
*dmm_lisa_regs = &lisa_map_dra7_1536MB; *dmm_lisa_regs = &lisa_map_dra7_1536MB;
@ -369,7 +369,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
case DRA722_ES2_0: case DRA722_ES2_0:
case DRA722_ES2_1: case DRA722_ES2_1:
default: default:
if (ram_size < CONFIG_MAX_MEM_MAPPED) if (ram_size < CFG_MAX_MEM_MAPPED)
*dmm_lisa_regs = &lisa_map_2G_x_2; *dmm_lisa_regs = &lisa_map_2G_x_2;
else else
*dmm_lisa_regs = &lisa_map_2G_x_4; *dmm_lisa_regs = &lisa_map_2G_x_4;
@ -644,9 +644,9 @@ int dram_init_banksize(void)
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = get_effective_memsize(); gd->bd->bi_dram[0].size = get_effective_memsize();
if (ram_size > CONFIG_MAX_MEM_MAPPED) { if (ram_size > CFG_MAX_MEM_MAPPED) {
gd->bd->bi_dram[1].start = 0x200000000; gd->bd->bi_dram[1].start = 0x200000000;
gd->bd->bi_dram[1].size = ram_size - CONFIG_MAX_MEM_MAPPED; gd->bd->bi_dram[1].size = ram_size - CFG_MAX_MEM_MAPPED;
} }
return 0; return 0;

6
common/memsize.c
View File

@ -106,11 +106,11 @@ phys_size_t __weak get_effective_memsize(void)
if (gd->ram_base + ram_size < gd->ram_base) if (gd->ram_base + ram_size < gd->ram_base)
ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base; ram_size = ((phys_size_t)~0xfffULL) - gd->ram_base;
#ifndef CONFIG_MAX_MEM_MAPPED #ifndef CFG_MAX_MEM_MAPPED
return ram_size; return ram_size;
#else #else
/* limit stack to what we can reasonable map */ /* limit stack to what we can reasonable map */
return ((ram_size > CONFIG_MAX_MEM_MAPPED) ? return ((ram_size > CFG_MAX_MEM_MAPPED) ?
CONFIG_MAX_MEM_MAPPED : ram_size); CFG_MAX_MEM_MAPPED : ram_size);
#endif #endif
} }

6
drivers/ddr/fsl/util.c
View File

@ -139,10 +139,10 @@ __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
} }
#if !defined(CONFIG_PHYS_64BIT) #if !defined(CONFIG_PHYS_64BIT)
if (base >= CONFIG_MAX_MEM_MAPPED) if (base >= CFG_MAX_MEM_MAPPED)
return; return;
if ((base + size) >= CONFIG_MAX_MEM_MAPPED) if ((base + size) >= CFG_MAX_MEM_MAPPED)
size = CONFIG_MAX_MEM_MAPPED - base; size = CFG_MAX_MEM_MAPPED - base;
#endif #endif
if (set_ddr_laws(base, size, law_memctl) < 0) { if (set_ddr_laws(base, size, law_memctl) < 0) {
printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num, printf("%s: ERROR (ctrl #%d, TRGT ID=%x)\n", __func__, ctrl_num,

2
include/configs/dra7xx_evm.h
View File

@ -13,7 +13,7 @@
#include <environment/ti/dfu.h> #include <environment/ti/dfu.h>
#define CONFIG_MAX_MEM_MAPPED 0x80000000 #define CFG_MAX_MEM_MAPPED 0x80000000
#ifndef CONFIG_QSPI_BOOT #ifndef CONFIG_QSPI_BOOT
/* MMC ENV related defines */ /* MMC ENV related defines */

2
include/configs/mt7621.h
View File

@ -10,7 +10,7 @@
#define CFG_SYS_SDRAM_BASE 0x80000000 #define CFG_SYS_SDRAM_BASE 0x80000000
#define CONFIG_MAX_MEM_MAPPED 0x1c000000 #define CFG_MAX_MEM_MAPPED 0x1c000000
#define CFG_SYS_INIT_SP_OFFSET 0x800000 #define CFG_SYS_INIT_SP_OFFSET 0x800000

2
include/configs/rcar-gen3-common.h
View File

@ -28,7 +28,7 @@
#define DRAM_RSV_SIZE 0x08000000 #define DRAM_RSV_SIZE 0x08000000
#define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_BASE (0x40000000 + DRAM_RSV_SIZE)
#define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE) #define CFG_SYS_SDRAM_SIZE (0x80000000u - DRAM_RSV_SIZE)
#define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE) #define CFG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
/* ENV setting */ /* ENV setting */

2
include/configs/synquacer.h
View File

@ -14,7 +14,7 @@
#define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */ #define CFG_SYS_SDRAM_BASE (0x80000000) /* Start address of DDR3 */
#define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */ #define PHYS_SDRAM_SIZE (0x7c000000) /* Default size (2GB - Secure memory) */
#define CONFIG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE #define CFG_MAX_MEM_MAPPED PHYS_SDRAM_SIZE
#define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */ #define SQ_DRAMINFO_BASE (0x2e00ffc0) /* DRAM info from TF-A */

8
include/configs/xtfpga.h
View File

@ -27,7 +27,7 @@
#else #else
#define CFG_SYS_MEMORY_BASE 0x60000000 #define CFG_SYS_MEMORY_BASE 0x60000000
#define CFG_SYS_IO_BASE 0x90000000 #define CFG_SYS_IO_BASE 0x90000000
#define CONFIG_MAX_MEM_MAPPED 0x10000000 #define CFG_MAX_MEM_MAPPED 0x10000000
#endif #endif
/* Onboard RAM sizes: /* Onboard RAM sizes:
@ -53,10 +53,10 @@
/* Memory test is destructive so default must not overlap vectors or U-Boot*/ /* Memory test is destructive so default must not overlap vectors or U-Boot*/
#if defined(CONFIG_MAX_MEM_MAPPED) && \ #if defined(CFG_MAX_MEM_MAPPED) && \
CONFIG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE CFG_MAX_MEM_MAPPED < CFG_SYS_SDRAM_SIZE
#define XTENSA_SYS_TEXT_ADDR \ #define XTENSA_SYS_TEXT_ADDR \
(MEMADDR(CONFIG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN) (MEMADDR(CFG_MAX_MEM_MAPPED) - CONFIG_SYS_MONITOR_LEN)
#else #else
#define XTENSA_SYS_TEXT_ADDR \ #define XTENSA_SYS_TEXT_ADDR \
(MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN) (MEMADDR(CFG_SYS_SDRAM_SIZE) - CONFIG_SYS_MONITOR_LEN)